VSF Documented
device.h
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1/*****************************************************************************
2 * Copyright(C)2009-2022 by VSF Team *
3 * *
4 * Licensed under the Apache License, Version 2.0 (the "License"); *
5 * you may not use this file except in compliance with the License. *
6 * You may obtain a copy of the License at *
7 * *
8 * http://www.apache.org/licenses/LICENSE-2.0 *
9 * *
10 * Unless required by applicable law or agreed to in writing, software *
11 * distributed under the License is distributed on an "AS IS" BASIS, *
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
13 * See the License for the specific language governing permissions and *
14 * limitations under the License. *
15 * *
16 ****************************************************************************/
17
18/*============================ INCLUDES ======================================*/
19
20#include "hal/vsf_hal_cfg.h"
21
22/*============================ MACROS ========================================*/
23
24#ifdef __VSF_HEADER_ONLY_SHOW_ARCH_INFO__
25
26/*\note first define basic info for arch. */
28# define VSF_ARCH_PRI_NUM 16
29# define VSF_ARCH_PRI_BIT 4
30
31// software interrupt provided by a dedicated device
32#define VSF_DEV_SWI_NUM 9
33
34#else
35
36#ifndef __HAL_DEVICE_NUVOTON_M484_H__
37#define __HAL_DEVICE_NUVOTON_M484_H__
38
39// software interrupt provided by a dedicated device
40#define VSF_DEV_SWI_LIST 5, 45, 50, 69, 81, 83, 91, 94, 95
41
42/*============================ INCLUDES ======================================*/
43
44/*\note this is should be the only place where __common.h is included.*/
45#include "../common/__common.h"
46
47/*============================ MACROS ========================================*/
48
49// user configurations with default value
50#ifndef M480_PLL_FREQ_HZ
51# define M480_PLL_FREQ_HZ (384 * 1000 * 1000)
52#endif
53
54#ifndef M480_HCLK_FREQ_HZ
55# define M480_HCLK_FREQ_HZ (192 * 1000 * 1000)
56#endif
57
58#ifndef M480_HXT_FREQ_HZ
59# define M480_HXT_FREQ_HZ (12 * 1000 * 1000)
60#endif
61
62#ifndef M480_PCLK0_FREQ_HZ
63# define M480_PCLK0_FREQ_HZ (96 * 1000 * 1000)
64#endif
65
66#ifndef M480_PCLK1_FREQ_HZ
67# define M480_PCLK1_FREQ_HZ (96 * 1000 * 1000)
68#endif
69
70// bit0 - bit7 : __bit_offset (0 .. 255)
71// bit8 - bit12 : __bit_len (0 .. 31)
72// bit13 : __is_wprotect
73#define M480_BIT_FIELD(__name, __bit_offset, __bit_len, __is_wprotect) \
74 __name = (__bit_offset) | ((__bit_len) << 8) | ((__is_wprotect) << 13)
75
76#define M480_BIT_FIELD_GET_BITLEN(__bf) (((__bf) >> 8) & 0x1F)
77
78#define VSF_HAL_USE_GPIO ENABLED
79#define VSF_HW_GPIO_COUNT 4
80#define VSF_HW_GPIO0_ADDRESS GPIOA_BASE
81#define VSF_HW_GPIO0_PIN_NUM 16
82
83#define VSF_HW_GPIO1_ADDRESS GPIOB_BASE
84#define VSF_HW_GPIO1_PIN_NUM 16
85
86#define VSF_HW_GPIO2_ADDRESS GPIOC_BASE
87#define VSF_HW_GPIO2_PIN_NUM 16
88
89#define VSF_HW_GPIO3_ADDRESS GPIOD_BASE
90#define VSF_HW_GPIO3_PIN_NUM 16
91
92/*
93#define PIO_PORTE
94#define PIO_PORTF
95#define PIO_PORTG
96#define PIO_PORTH
97*/
98
99#define VSF_HW_SPI_COUNT 0x02
100#define VSF_HW_SPI0_DMA_TX_CHANNEL 0
101#define VSF_HW_SPI0_DMA_RX_CHANNEL 1
102#define VSF_HW_SPI1_DMA_TX_CHANNEL 2
103#define VSF_HW_SPI1_DMA_RX_CHANNEL 3
104#define VSF_HW_SPI2_DMA_TX_CHANNEL 4
105#define VSF_HW_SPI2_DMA_RX_CHANNEL 5
106
107#define VSF_HW_USB_HC_COUNT 1
108#define VSF_HW_USB_HC_OHCI_COUNT 1
109
110#define VSF_HW_USB_HC0_TYPE ohci
111#define VSF_HW_USB_HC0_IRQHandler OHCI_IRQHandler
112#define VSF_HW_USB_HC0_CONFIG \
113 .reg = USBH, \
114 .sclk = SCLK_USBH_IDX, \
115 .pclk = PCLK_USB_IDX, \
116 .phy = M480_USBPHY_FS, \
117 .irq = USBH_IRQn, \
118 \
119 .dp.pin_index = PA14, \
120 .dp.function = 14, \
121 .dm.pin_index = PA13, \
122 .dm.function = 14,
123
124#define VSF_HW_USB_DC_COUNT 1
125#define VSF_HW_USB_DC_HS_COUNT 1
126#define VSF_HW_USB_DC_FS_COUNT 0
127
128
129#define VSF_HW_USB_DC0_TYPE usbd_hs
130#define VSF_HW_USB_DC0_IRQHandler USBD20_IRQHandler
131#define VSF_HW_USB_DC0_EP_NUM 14
132#define VSF_HW_USB_DC0_CONFIG \
133 .reg = HSUSBD, \
134 .sclk = SCLK_USBD_IDX, \
135 .phy = M480_USBPHY_HS, \
136 .irq = USBD20_IRQn,
137
138
139#define VSF_HW_USART_COUNT 5
140/* RST */
141#define VSF_HW_USART0_RST ((4ul << 24) | SYS_IPRST1_UART0RST_Pos)
142#define VSF_HW_USART1_RST ((4ul << 24) | SYS_IPRST1_UART1RST_Pos)
143#define VSF_HW_USART2_RST ((4ul << 24) | SYS_IPRST1_UART2RST_Pos)
144#define VSF_HW_USART3_RST ((4ul << 24) | SYS_IPRST1_UART3RST_Pos)
145#define VSF_HW_USART4_RST ((4ul << 24) | SYS_IPRST1_UART4RST_Pos)
146#define VSF_HW_USART5_RST ((4ul << 24) | SYS_IPRST1_UART5RST_Pos)
147/* Module */
148#define VSF_HW_USART0_MODULE ((1ul << 30) | (1ul << 28) | (0x3ul << 25) | (24ul << 20) | (0ul << 18) | (0xFul << 10) | (8ul << 5) |(16ul << 0))
149#define VSF_HW_USART1_MODULE ((1ul << 30) | (1ul << 28) | (0x3ul << 25) | (26ul << 20) | (0ul << 18) | (0xFul << 10) | (12ul << 5) |(17ul << 0))
150#define VSF_HW_USART2_MODULE ((1ul << 30) | (3ul << 28) | (0x3ul << 25) | (24ul << 20) | (3ul << 18) | (0xFul << 10) | (0ul << 5) |(18ul << 0))
151#define VSF_HW_USART3_MODULE ((1ul << 30) | (3ul << 28) | (0x3ul << 25) | (26ul << 20) | (3ul << 18) | (0xFul << 10) | (4ul << 5) |(19ul << 0))
152#define VSF_HW_USART4_MODULE ((1ul << 30) | (3ul << 28) | (0x3ul << 25) | (28ul << 20) | (3ul << 18) | (0xFul << 10) | (8ul << 5) |(20ul << 0))
153#define VSF_HW_USART5_MODULE ((1ul << 30) | (3ul << 28) | (0x3ul << 25) | (30ul << 20) | (3ul << 18) | (0xFul << 10) | (12ul << 5) |(21ul << 0))
154/* SEL */
155#define VSF_HW_USART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos)
156#define VSF_HW_USART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos)
157#define VSF_HW_USART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos)
158#define VSF_HW_USART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos)
159#define VSF_HW_USART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos)
160#define VSF_HW_USART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos)
161#define VSF_HW_USART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos)
162#define VSF_HW_USART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos)
163#define VSF_HW_USART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos)
164#define VSF_HW_USART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos)
165#define VSF_HW_USART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos)
166#define VSF_HW_USART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos)
167#define VSF_HW_USART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos)
168#define VSF_HW_USART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos)
169#define VSF_HW_USART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos)
170#define VSF_HW_USART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos)
171#define VSF_HW_USART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos)
172#define VSF_HW_USART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos)
173#define VSF_HW_USART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos)
174#define VSF_HW_USART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos)
175#define VSF_HW_USART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos)
176#define VSF_HW_USART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos)
177#define VSF_HW_USART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos)
178#define VSF_HW_USART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos)
179
180/*============================ MACROFIED FUNCTIONS ===========================*/
181/*============================ TYPES =========================================*/
182
183/*============================ GLOBAL VARIABLES ==============================*/
184/*============================ LOCAL VARIABLES ===============================*/
185/*============================ PROTOTYPES ====================================*/
186
187
188#endif // __HAL_DEVICE_NUVOTON_M484_H__
189#endif // __VSF_HEADER_ONLY_SHOW_ARCH_INFO__
190/* EOF */
vsf_hal_cfg.h
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