18#ifndef __I_REG_PWM_H__
19#define __I_REG_PWM_H__
36#ifndef __AIC8800_PWM_USE_BIT_FIELD
37# define __AIC8800_PWM_USE_BIT_FIELD DISABLED
58#define PWM_TMR_MODE_MASK ((reg32_t)(0x1 << PWM_TMR_MODE))
61#define PWM_TMR_RUN_MASK ((reg32_t)(0x1 << PWM_TMR_RUN))
65#define PWM_TMR_INT_EN 0
66#define PWM_TMR_INT_EN_MASK ((reg32_t)(0x1 << PWM_TMR_INT_EN))
68#define PWM_TMR_INT_RAW 1
69#define PWM_TMR_INT_RAW_MASK ((reg32_t)(0x1 << PWM_TMR_INT_RAW))
71#define PWM_TMR_INT_STATUS 2
72#define PWM_TMR_INT_STATUS_MASK ((reg32_t)(0x1 << PWM_TMR_INT_STATUS))
74#define PWM_TMR_INT_CLR 3
75#define PWM_TMR_INT_CLR_MASK ((reg32_t)(0x1 << PWM_TMR_INT_CLR))
80#define PWM_PWM_RUN_MASK ((reg32_t)(0x1 << PWM_PWM_RUN))
82#define PWM_PWM_INC_MODE 1
83#define PWM_PWM_INC_MODE_MASK ((reg32_t)(0x1 << PWM_PWM_INC_MODE))
85#define PWM_PWM_DEFAULT_VAL 2
86#define PWM_PWM_DEFAULT_VAL_MASK ((reg32_t)(0x1 << PWM_PWM_DEFAULT_VAL))
88#define PWM_PWM_UPDATE 31
89#define PWM_PWM_UPDATE_MASK ((reg32_t)(0x1 << PWM_PWM_UPDATE))
93#if __AIC8800_PWM_USE_BIT_FIELD == ENABLED
94# define DEF_PWM_REG(__NAME, __TOTAL_SIZE, ...) \
96 reg##__TOTAL_SIZE##_t VALUE; \
102# define DEF_PWM_REG(__NAME, __TOTAL_SIZE, ...) \
103 __VA_ARGS__ reg##__TOTAL_SIZE##_t __NAME
#define REG_RSVD_U32
Definition i_io_systick.h:138
#define REG_RSVD_U32N(__N)
Definition i_io_systick.h:142
#define __IOM
Definition i_reg_pwm.h:52
Definition i_reg_pwm.h:119
DEF_PWM_REG(cfg, 32, __IOM)
DEF_PWM_REG(end_val, 32, __IOM)
DEF_PWM_REG(int_ctrl, 32, __IOM)
DEF_PWM_REG(sta_val, 32, __IOM)
DEF_PWM_REG(step_cfg0, 32, __IOM)
DEF_PWM_REG(step_cnt, 32, __IOM)
DEF_PWM_REG(end_val_use, 32, __IOM)
DEF_PWM_REG(step_cfg1, 32, __IOM)
Definition i_reg_pwm.h:108
DEF_PWM_REG(ld_value, 32, __IOM)
REG_RSVD_U32 DEF_PWM_REG(cfg, 32, __IOM)
DEF_PWM_REG(cnt_read, 32, __IOM)
DEF_PWM_REG(int_ctrl, 32, __IOM)
REG_RSVD_U32 DEF_PWM_REG(cnt_value, 32, __IOM)
Definition i_reg_pwm.h:130
__PWM_REG_T PWM[6]
Definition i_reg_pwm.h:133
__TMR_REG_T TMR[3]
Definition i_reg_pwm.h:131