VSF Documented
i_reg_pwm.h
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1/*****************************************************************************
2 * Copyright(C)2009-2022 by VSF Team *
3 * *
4 * Licensed under the Apache License, Version 2.0 (the "License"); *
5 * you may not use this file except in compliance with the License. *
6 * You may obtain a copy of the License at *
7 * *
8 * http://www.apache.org/licenses/LICENSE-2.0 *
9 * *
10 * Unless required by applicable law or agreed to in writing, software *
11 * distributed under the License is distributed on an "AS IS" BASIS, *
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
13 * See the License for the specific language governing permissions and *
14 * limitations under the License. *
15 * *
16 ****************************************************************************/
17
18#ifndef __I_REG_PWM_H__
19#define __I_REG_PWM_H__
20
21/*============================ INCLUDES ======================================*/
22
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34/*============================ MACROS ========================================*/
35
36#ifndef __AIC8800_PWM_USE_BIT_FIELD
37# define __AIC8800_PWM_USE_BIT_FIELD DISABLED
38#endif
39
40/* Define structure member permissions : 'read only' */
41#ifndef __IM
42# define __IM const
43#endif
44
45/* Define structure member permissions : 'write only' */
46#ifndef __OM
47# define __OM
48#endif
49
50/* Define structure member permissions : 'read or write' */
51#ifndef __IOM
52# define __IOM
53#endif
54
55/* -------------------- tmr cfg register ------------------------------------ */
56
57#define PWM_TMR_MODE 0 /* 0x00000001 */
58#define PWM_TMR_MODE_MASK ((reg32_t)(0x1 << PWM_TMR_MODE))
59
60#define PWM_TMR_RUN 1 /* 0x00000002 */
61#define PWM_TMR_RUN_MASK ((reg32_t)(0x1 << PWM_TMR_RUN))
62
63/* -------------------- tmr int_ctrl register ------------------------------- */
64
65#define PWM_TMR_INT_EN 0 /* 0x00000001 */
66#define PWM_TMR_INT_EN_MASK ((reg32_t)(0x1 << PWM_TMR_INT_EN))
67
68#define PWM_TMR_INT_RAW 1 /* 0x00000002 */
69#define PWM_TMR_INT_RAW_MASK ((reg32_t)(0x1 << PWM_TMR_INT_RAW))
70
71#define PWM_TMR_INT_STATUS 2 /* 0x00000004 */
72#define PWM_TMR_INT_STATUS_MASK ((reg32_t)(0x1 << PWM_TMR_INT_STATUS))
73
74#define PWM_TMR_INT_CLR 3 /* 0x00000008 */
75#define PWM_TMR_INT_CLR_MASK ((reg32_t)(0x1 << PWM_TMR_INT_CLR))
76
77/* -------------------- pwm_cfg --------------------------------------------- */
78
79#define PWM_PWM_RUN 0
80#define PWM_PWM_RUN_MASK ((reg32_t)(0x1 << PWM_PWM_RUN))
81
82#define PWM_PWM_INC_MODE 1
83#define PWM_PWM_INC_MODE_MASK ((reg32_t)(0x1 << PWM_PWM_INC_MODE))
84
85#define PWM_PWM_DEFAULT_VAL 2
86#define PWM_PWM_DEFAULT_VAL_MASK ((reg32_t)(0x1 << PWM_PWM_DEFAULT_VAL))
87
88#define PWM_PWM_UPDATE 31
89#define PWM_PWM_UPDATE_MASK ((reg32_t)(0x1 << PWM_PWM_UPDATE))
90
91/*============================ MACROFIED FUNCTIONS ===========================*/
92
93#if __AIC8800_PWM_USE_BIT_FIELD == ENABLED
94# define DEF_PWM_REG(__NAME, __TOTAL_SIZE, ...) \
95 union { \
96 reg##__TOTAL_SIZE##_t VALUE; \
97 struct { \
98 __VA_ARGS__ \
99 }; \
100 } __NAME
101#else
102# define DEF_PWM_REG(__NAME, __TOTAL_SIZE, ...) \
103 __VA_ARGS__ reg##__TOTAL_SIZE##_t __NAME
104#endif
105
106/*============================ TYPES =========================================*/
107
108typedef struct __TMR_REG_T {
109 DEF_PWM_REG(ld_value, 32, __IOM);
111 DEF_PWM_REG(cnt_value, 32, __IOM);
114 DEF_PWM_REG(int_ctrl, 32, __IOM);
115 DEF_PWM_REG(cnt_read, 32, __IOM);
118
119typedef struct __PWM_REG_T {
120 DEF_PWM_REG(sta_val, 32, __IOM);
121 DEF_PWM_REG(end_val, 32, __IOM);
122 DEF_PWM_REG(step_cfg0, 32, __IOM);
123 DEF_PWM_REG(step_cfg1, 32, __IOM);
125 DEF_PWM_REG(int_ctrl, 32, __IOM);
126 DEF_PWM_REG(end_val_use, 32, __IOM);
127 DEF_PWM_REG(step_cnt, 32, __IOM);
129
130typedef struct PWM_REG_T {
132 REG_RSVD_U32N(40)
135
136#ifdef __cplusplus
137}
138#endif
139#endif
140/* EOF */
#define REG_RSVD_U32
Definition i_io_systick.h:138
#define REG_RSVD_U32N(__N)
Definition i_io_systick.h:142
#define __IOM
Definition i_reg_pwm.h:52
Definition i_reg_pwm.h:119
DEF_PWM_REG(cfg, 32, __IOM)
DEF_PWM_REG(end_val, 32, __IOM)
DEF_PWM_REG(int_ctrl, 32, __IOM)
DEF_PWM_REG(sta_val, 32, __IOM)
DEF_PWM_REG(step_cfg0, 32, __IOM)
DEF_PWM_REG(step_cnt, 32, __IOM)
DEF_PWM_REG(end_val_use, 32, __IOM)
DEF_PWM_REG(step_cfg1, 32, __IOM)
Definition i_reg_pwm.h:108
DEF_PWM_REG(ld_value, 32, __IOM)
REG_RSVD_U32 DEF_PWM_REG(cfg, 32, __IOM)
DEF_PWM_REG(cnt_read, 32, __IOM)
DEF_PWM_REG(int_ctrl, 32, __IOM)
REG_RSVD_U32 DEF_PWM_REG(cnt_value, 32, __IOM)
Definition i_reg_pwm.h:130
__PWM_REG_T PWM[6]
Definition i_reg_pwm.h:133
__TMR_REG_T TMR[3]
Definition i_reg_pwm.h:131