18#ifndef __I_REG_SPI_H__ 
   19#define __I_REG_SPI_H__ 
   35#ifndef __AIC8800_SPI_USE_BIT_FIELD 
   36#   define __AIC8800_SPI_USE_BIT_FIELD              DISABLED 
   39#define SPI0_BASE_ADDRESS                           (0X40105000ul) 
   41#define REG_SPI0                                    ((REG_SPI_T *)SPI0_BASE_ADDRESS) 
   60#if __AIC8800_SPI_USE_BIT_FIELD == ENABLED 
   61#   define DEF_SPI_REG(__NAME, __TOTAL_SIZE, ...)                               \ 
   63        reg##__TOTAL_SIZE##_t VALUE;                                            \ 
   69#   define DEF_SPI_REG(__NAME, __TOTAL_SIZE, ...)                               \ 
   70        __VA_ARGS__ reg##__TOTAL_SIZE##_t __NAME 
   74#define SPI_DR_DIV_MASK         ((reg32_t)(0xFFFF << SPI_DR_DIV)) 
volatile uint32_t reg32_t
Definition i_io_systick.h:120
#define REG_RSVD_U32
Definition i_io_systick.h:138
#define REG_RSVD_U32N(__N)
Definition i_io_systick.h:142
#define DEF_SPI_REG(__NAME, __TOTAL_SIZE,...)
Definition i_reg_spi.h:61
#define __IM
Definition i_reg_spi.h:45
#define __IOM
Definition i_reg_spi.h:55
Definition i_reg_spi.h:78
DEF_SPI_REG(ICLR, 32, __IOM)
DEF_SPI_REG(IER, 32, __IOM)
reg32_t CR[6]
Definition i_reg_spi.h:84
DEF_SPI_REG(IMSR, 32, __IM)
__IM reg32_t BASE_ADDR
Definition i_reg_spi.h:80
DEF_SPI_REG(IRSR, 32, __IM)
DEF_SPI_REG(DR, 32, __IOM)
REG_RSVD_U32 DEF_SPI_REG(SR, 32, __IOM)