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partition_CMSDK_ARMv8MML.h
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1/**************************************************************************/
7/* Copyright (c) 2015 - 2016 ARM LIMITED
8
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
19 specific prior written permission.
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
33
34
35#ifndef PARTITION_CMSDK_ARMv8MML_H
36#define PARTITION_CMSDK_ARMv8MML_H
37
38/*
39//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
40*/
41
42/*
43// <e>Initialize Security Attribution Unit (SAU) CTRL register
44*/
45#define SAU_INIT_CTRL 1
46
47/*
48// <q> Enable SAU
49// <i> Value for SAU->CTRL register bit ENABLE
50*/
51#define SAU_INIT_CTRL_ENABLE 1
52
53/*
54// <o> When SAU is disabled
55// <0=> All Memory is Secure
56// <1=> All Memory is Non-Secure
57// <i> Value for SAU->CTRL register bit ALLNS
58// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
59*/
60#define SAU_INIT_CTRL_ALLNS 0
61
62/*
63// </e>
64*/
65
66/*
67// <h>Initialize Security Attribution Unit (SAU) Address Regions
68// <i>SAU configuration specifies regions to be one of:
69// <i> - Secure and Non-Secure Callable
70// <i> - Non-Secure
71// <i>Note: All memory regions not configured by SAU are Secure
72*/
73#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
74
75/*
76// <e>Initialize SAU Region 0
77// <i> Setup SAU Region 0 memory attributes
78*/
79#define SAU_INIT_REGION0 1
80
81/*
82// <o>Start Address <0-0xFFFFFFE0>
83*/
84#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
85
86/*
87// <o>End Address <0x1F-0xFFFFFFFF>
88*/
89#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
90
91/*
92// <o>Region is
93// <0=>Non-Secure
94// <1=>Secure, Non-Secure Callable
95*/
96#define SAU_INIT_NSC0 1
97/*
98// </e>
99*/
100
101/*
102// <e>Initialize SAU Region 1
103// <i> Setup SAU Region 1 memory attributes
104*/
105#define SAU_INIT_REGION1 1
106
107/*
108// <o>Start Address <0-0xFFFFFFE0>
109*/
110#define SAU_INIT_START1 0x00200000
111
112/*
113// <o>End Address <0x1F-0xFFFFFFFF>
114*/
115#define SAU_INIT_END1 0x003FFFFF
116
117/*
118// <o>Region is
119// <0=>Non-Secure
120// <1=>Secure, Non-Secure Callable
121*/
122#define SAU_INIT_NSC1 0
123/*
124// </e>
125*/
126
127/*
128// <e>Initialize SAU Region 2
129// <i> Setup SAU Region 2 memory attributes
130*/
131#define SAU_INIT_REGION2 1
132
133/*
134// <o>Start Address <0-0xFFFFFFE0>
135*/
136#define SAU_INIT_START2 0x20200000
137
138/*
139// <o>End Address <0x1F-0xFFFFFFFF>
140*/
141#define SAU_INIT_END2 0x203FFFFF
142
143/*
144// <o>Region is
145// <0=>Non-Secure
146// <1=>Secure, Non-Secure Callable
147*/
148#define SAU_INIT_NSC2 0
149/*
150// </e>
151*/
152
153/*
154// <e>Initialize SAU Region 3
155// <i> Setup SAU Region 3 memory attributes
156*/
157#define SAU_INIT_REGION3 1
158
159/*
160// <o>Start Address <0-0xFFFFFFE0>
161*/
162#define SAU_INIT_START3 0x40000000
163
164/*
165// <o>End Address <0x1F-0xFFFFFFFF>
166*/
167#define SAU_INIT_END3 0x40040000
168
169/*
170// <o>Region is
171// <0=>Non-Secure
172// <1=>Secure, Non-Secure Callable
173*/
174#define SAU_INIT_NSC3 0
175/*
176// </e>
177*/
178
179/*
180// <e>Initialize SAU Region 4
181// <i> Setup SAU Region 4 memory attributes
182*/
183#define SAU_INIT_REGION4 0
184
185/*
186// <o>Start Address <0-0xFFFFFFE0>
187*/
188#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
189
190/*
191// <o>End Address <0x1F-0xFFFFFFFF>
192*/
193#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
194
195/*
196// <o>Region is
197// <0=>Non-Secure
198// <1=>Secure, Non-Secure Callable
199*/
200#define SAU_INIT_NSC4 0
201/*
202// </e>
203*/
204
205/*
206// <e>Initialize SAU Region 5
207// <i> Setup SAU Region 5 memory attributes
208*/
209#define SAU_INIT_REGION5 0
210
211/*
212// <o>Start Address <0-0xFFFFFFE0>
213*/
214#define SAU_INIT_START5 0x00000000
215
216/*
217// <o>End Address <0x1F-0xFFFFFFFF>
218*/
219#define SAU_INIT_END5 0x00000000
220
221/*
222// <o>Region is
223// <0=>Non-Secure
224// <1=>Secure, Non-Secure Callable
225*/
226#define SAU_INIT_NSC5 0
227/*
228// </e>
229*/
230
231/*
232// <e>Initialize SAU Region 6
233// <i> Setup SAU Region 6 memory attributes
234*/
235#define SAU_INIT_REGION6 0
236
237/*
238// <o>Start Address <0-0xFFFFFFE0>
239*/
240#define SAU_INIT_START6 0x00000000
241
242/*
243// <o>End Address <0x1F-0xFFFFFFFF>
244*/
245#define SAU_INIT_END6 0x00000000
246
247/*
248// <o>Region is
249// <0=>Non-Secure
250// <1=>Secure, Non-Secure Callable
251*/
252#define SAU_INIT_NSC6 0
253/*
254// </e>
255*/
256
257/*
258// <e>Initialize SAU Region 7
259// <i> Setup SAU Region 7 memory attributes
260*/
261#define SAU_INIT_REGION7 0
262
263/*
264// <o>Start Address <0-0xFFFFFFE0>
265*/
266#define SAU_INIT_START7 0x00000000
267
268/*
269// <o>End Address <0x1F-0xFFFFFFFF>
270*/
271#define SAU_INIT_END7 0x00000000
272
273/*
274// <o>Region is
275// <0=>Non-Secure
276// <1=>Secure, Non-Secure Callable
277*/
278#define SAU_INIT_NSC7 0
279/*
280// </e>
281*/
282
283/*
284// </h>
285*/
286
287/*
288// <e>Setup behaviour of Sleep and Exception Handling
289*/
290#define SCB_CSR_AIRCR_INIT 1
291
292/*
293// <o> Deep Sleep can be enabled by
294// <0=>Secure and Non-Secure state
295// <1=>Secure state only
296// <i> Value for SCB->CSR register bit DEEPSLEEPS
297*/
298#define SCB_CSR_DEEPSLEEPS_VAL 1
299
300/*
301// <o>System reset request accessible from
302// <0=> Secure and Non-Secure state
303// <1=> Secure state only
304// <i> Value for SCB->AIRCR register bit SYSRESETREQS
305*/
306#define SCB_AIRCR_SYSRESETREQS_VAL 1
307
308/*
309// <o>Priority of Non-Secure exceptions is
310// <0=> Not altered
311// <1=> Lowered to 0x80-0xFF
312// <i> Value for SCB->AIRCR register bit PRIS
313*/
314#define SCB_AIRCR_PRIS_VAL 1
315
316/*
317// <o>BusFault, HardFault, and NMI target
318// <0=> Secure state
319// <1=> Non-Secure state
320// <i> Value for SCB->AIRCR register bit BFHFNMINS
321*/
322#define SCB_AIRCR_BFHFNMINS_VAL 0
323
324/*
325// </e>
326*/
327
328/*
329// <e>Setup behaviour of Floating Point Unit
330*/
331#define TZ_FPU_NS_USAGE 1
332
333/*
334// <o>Floating Point Unit usage
335// <0=> Secure state only
336// <3=> Secure and Non-Secure state
337// <i> Value for SCB->NSACR register bits CP10, CP11
338*/
339#define SCB_NSACR_CP10_11_VAL 3
340
341/*
342// <o>Treat floating-point registers as Secure
343// <0=> Disabled
344// <1=> Enabled
345// <i> Value for FPU->FPCCR register bit TS
346*/
347#define FPU_FPCCR_TS_VAL 0
348
349/*
350// <o>Clear on return (CLRONRET) accessibility
351// <0=> Secure and Non-Secure state
352// <1=> Secure state only
353// <i> Value for FPU->FPCCR register bit CLRONRETS
354*/
355#define FPU_FPCCR_CLRONRETS_VAL 0
356
357/*
358// <o>Clear floating-point caller saved registers on exception return
359// <0=> Disabled
360// <1=> Enabled
361// <i> Value for FPU->FPCCR register bit CLRONRET
362*/
363#define FPU_FPCCR_CLRONRET_VAL 1
364
365/*
366// </e>
367*/
368
369/*
370// <h>Setup Interrupt Target
371*/
372
373/*
374// <e>Initialize ITNS 0 (Interrupts 0..31)
375*/
376#define NVIC_INIT_ITNS0 1
377
378/*
379// Interrupts 0..31
380// <o.0> UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state
381// <o.1> UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state
382// <o.2> UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state
383// <o.3> UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state
384// <o.4> UART 2 receive interrupt <0=> Secure state <1=> Non-Secure state
385// <o.5> UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state
386// <o.6> GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state
387// <o.7> GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state
388// <o.8> Timer 0 interrupt <0=> Secure state <1=> Non-Secure state
389// <o.9> Timer 1 interrupt <0=> Secure state <1=> Non-Secure state
390// <o.10> Dual Timer interrupt <0=> Secure state <1=> Non-Secure state
391// <o.11> SPI 0, 1 interrupt <0=> Secure state <1=> Non-Secure state
392// <o.12> UART 0, 1, 2, overflow interrupt <0=> Secure state <1=> Non-Secure state
393// <o.13> Ethernet interrupt <0=> Secure state <1=> Non-Secure state
394// <o.14> Audio I2S interrupt <0=> Secure state <1=> Non-Secure state
395// <o.15> Touch Screen interrupt <0=> Secure state <1=> Non-Secure state
396// <o.16> GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state
397// <o.17> GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state
398// <o.18> UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state
399// <o.19> UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state
400// <o.20> UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state
401// <o.21> UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state
402// <o.22> SPI 2 interrupt <0=> Secure state <1=> Non-Secure state
403// <o.23> SPI 3, 4 interrupt <0=> Secure state <1=> Non-Secure state
404// <o.24> GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state
405// <o.25> GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state
406// <o.26> GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state
407// <o.27> GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state
408// <o.28> GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state
409// <o.29> GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state
410// <o.30> GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state
411// <o.31> GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state
412*/
413#define NVIC_INIT_ITNS0_VAL 0x0000122B
414
415/*
416// </e>
417*/
418
419/*
420// <e>Initialize ITNS 1 (Interrupts 32..63)
421*/
422#define NVIC_INIT_ITNS1 1
423
424/*
425// Interrupts 32..63
426// <o.0> GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state
427// <o.1> GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state
428// <o.2> GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state
429// <o.3> GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state
430// <o.4> GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state
431// <o.5> GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state
432// <o.6> GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state
433// <o.7> GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state
434// <o.8> GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state
435// <o.9> GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state
436// <o.10> GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state
437// <o.11> GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state
438// <o.12> GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state
439// <o.13> GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state
440// <o.14> GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state
441// <o.15> GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state
442// <o.16> SPI 0B interrupt <0=> Secure state <1=> Non-Secure state
443// <o.18> Secure Timer 0 interrupt <0=> Secure state <1=> Non-Secure state
444// <o.19> Secure Timer 1 interrupt <0=> Secure state <1=> Non-Secure state
445// <o.20> SPI 1B interrupt <0=> Secure state <1=> Non-Secure state
446// <o.21> SPI 2B interrupt <0=> Secure state <1=> Non-Secure state
447// <o.22> SPI 3B interrupt <0=> Secure state <1=> Non-Secure state
448// <o.23> SPI 4B interrupt <0=> Secure state <1=> Non-Secure state
449*/
450#define NVIC_INIT_ITNS1_VAL 0x00000000
451
452/*
453// </e>
454*/
455
456/*
457// </h>
458*/
459
460
461
462/*
463 max 128 SAU regions.
464 SAU regions are defined in partition.h
465 */
466
467#define SAU_INIT_REGION(n) \
468 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
469 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
470 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
471 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
472
478__STATIC_INLINE void TZ_SAU_Setup (void)
479{
480
481#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
482
483 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
484 SAU_INIT_REGION(0);
485 #endif
486
487 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
488 SAU_INIT_REGION(1);
489 #endif
490
491 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
492 SAU_INIT_REGION(2);
493 #endif
494
495 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
496 SAU_INIT_REGION(3);
497 #endif
498
499 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
500 SAU_INIT_REGION(4);
501 #endif
502
503 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
504 SAU_INIT_REGION(5);
505 #endif
506
507 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
508 SAU_INIT_REGION(6);
509 #endif
510
511 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
512 SAU_INIT_REGION(7);
513 #endif
514
515 /* repeat this for all possible SAU regions */
516
517#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
518
519
520 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
521 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
522 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
523 #endif
524
525 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
526 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
527 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
528
529 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
530 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
531 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
532 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
533 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
534 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
535 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
536
537 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
538 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
539
540 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
541 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
542
543 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
544 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
545 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
546 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
547 #endif
548
549 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
550 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
551 #endif
552
553 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
554 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
555 #endif
556
557 /* repeat this for all possible ITNS elements */
558
559}
560
561#endif /* PARTITION_CMSDK_ARMv8MML_H */
__STATIC_INLINE
#define __STATIC_INLINE
Definition compiler.h:14
TZ_SAU_Setup
__STATIC_INLINE void TZ_SAU_Setup(void)
Setup a SAU Region.
Definition partition_CMSDK_ARMv8MML.h:478
FPU_FPCCR_TS_VAL
#define FPU_FPCCR_TS_VAL
Definition partition_CMSDK_ARMv8MML.h:347
FPU_FPCCR_CLRONRETS_VAL
#define FPU_FPCCR_CLRONRETS_VAL
Definition partition_CMSDK_ARMv8MML.h:355
SAU_INIT_CTRL_ALLNS
#define SAU_INIT_CTRL_ALLNS
Definition partition_CMSDK_ARMv8MML.h:60
SCB_CSR_DEEPSLEEPS_VAL
#define SCB_CSR_DEEPSLEEPS_VAL
Definition partition_CMSDK_ARMv8MML.h:298
SCB_NSACR_CP10_11_VAL
#define SCB_NSACR_CP10_11_VAL
Definition partition_CMSDK_ARMv8MML.h:339
SAU_INIT_CTRL_ENABLE
#define SAU_INIT_CTRL_ENABLE
Definition partition_CMSDK_ARMv8MML.h:51
SAU_INIT_REGION
#define SAU_INIT_REGION(n)
Definition partition_CMSDK_ARMv8MML.h:467
SCB_AIRCR_SYSRESETREQS_VAL
#define SCB_AIRCR_SYSRESETREQS_VAL
Definition partition_CMSDK_ARMv8MML.h:306
FPU_FPCCR_CLRONRET_VAL
#define FPU_FPCCR_CLRONRET_VAL
Definition partition_CMSDK_ARMv8MML.h:363
NVIC_INIT_ITNS1_VAL
#define NVIC_INIT_ITNS1_VAL
Definition partition_CMSDK_ARMv8MML.h:450
SCB_AIRCR_BFHFNMINS_VAL
#define SCB_AIRCR_BFHFNMINS_VAL
Definition partition_CMSDK_ARMv8MML.h:322
SCB_AIRCR_PRIS_VAL
#define SCB_AIRCR_PRIS_VAL
Definition partition_CMSDK_ARMv8MML.h:314
NVIC_INIT_ITNS0_VAL
#define NVIC_INIT_ITNS0_VAL
Definition partition_CMSDK_ARMv8MML.h:413
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