VSF Documented
sthal_qspi.h
Go to the documentation of this file.
1/*****************************************************************************
2 * Copyright(C)2009-2024 by VSF Team *
3 * *
4 * Licensed under the Apache License, Version 2.0 (the "License"); *
5 * you may not use this file except in compliance with the License. *
6 * You may obtain a copy of the License at *
7 * *
8 * http://www.apache.org/licenses/LICENSE-2.0 *
9 * *
10 * Unless required by applicable law or agreed to in writing, software *
11 * distributed under the License is distributed on an "AS IS" BASIS, *
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
13 * See the License for the specific language governing permissions and *
14 * limitations under the License. *
15 * *
16 ****************************************************************************/
17
18#ifndef __ST_HAL_QSPI_H__
19#define __ST_HAL_QSPI_H__
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25#if defined(HAL_QSPI_MODULE_ENABLED) && VSF_HAL_USE_SPI == ENABLED && defined(VSF_SPI_CTRL_QSPI_ENABLE)
26
27/*============================ INCLUDES ======================================*/
28
29#include "sthal_def.h"
30
31/*============================ MACROS ========================================*/
32
33#define HAL_QSPI_ERROR_NONE 0x00000000U
34#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U
35#define HAL_QSPI_ERROR_TRANSFER 0x00000002U
36#define HAL_QSPI_ERROR_DMA 0x00000004U
37#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U
38
39#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
40# define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U
41#endif
42
43#ifdef VSF_SPI_QSPI_SAMPLE_SHIFTING_NONE
44# define QSPI_SAMPLE_SHIFTING_NONE VSF_SPI_QSPI_SAMPLE_SHIFTING_NONE
45#else
46# define QSPI_SAMPLE_SHIFTING_NONE 0
47#endif
48
49#ifdef VSF_SPI_QSPI_SAMPLE_SHIFTING_HALFCYCLE
50# define QSPI_SAMPLE_SHIFTING_HALFCYCLE VSF_SPI_QSPI_SAMPLE_SHIFTING_HALFCYCLE
51#else
52# define QSPI_SAMPLE_SHIFTING_HALFCYCLE 0
53#endif
54
55#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_1_CYCLE
56# define QSPI_CS_HIGH_TIME_1_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_1_CYCLE
57#else
58# define QSPI_CS_HIGH_TIME_1_CYCLE 0
59#endif
60
61#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_2_CYCLE
62# define QSPI_CS_HIGH_TIME_2_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_2_CYCLE
63#else
64# define QSPI_CS_HIGH_TIME_2_CYCLE 0
65#endif
66
67#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_3_CYCLE
68# define QSPI_CS_HIGH_TIME_3_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_3_CYCLE
69#else
70# define QSPI_CS_HIGH_TIME_3_CYCLE 0
71#endif
72
73#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_4_CYCLE
74# define QSPI_CS_HIGH_TIME_4_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_4_CYCLE
75#else
76# define QSPI_CS_HIGH_TIME_4_CYCLE 0
77#endif
78
79#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_5_CYCLE
80# define QSPI_CS_HIGH_TIME_5_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_5_CYCLE
81#else
82# define QSPI_CS_HIGH_TIME_5_CYCLE 0
83#endif
84
85#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_6_CYCLE
86# define QSPI_CS_HIGH_TIME_6_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_6_CYCLE
87#else
88# define QSPI_CS_HIGH_TIME_6_CYCLE 0
89#endif
90
91#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_7_CYCLE
92# define QSPI_CS_HIGH_TIME_7_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_7_CYCLE
93#else
94# define QSPI_CS_HIGH_TIME_7_CYCLE 0
95#endif
96
97#ifdef VSF_SPI_QSPI_CS_HIGH_TIME_8_CYCLE
98# define QSPI_CS_HIGH_TIME_8_CYCLE VSF_SPI_QSPI_CS_HIGH_TIME_8_CYCLE
99#else
100# define QSPI_CS_HIGH_TIME_8_CYCLE 0
101#endif
102
103#define QSPI_CLOCK_MODE_0 VSF_SPI_MODE_0
104#define QSPI_CLOCK_MODE_3 VSF_SPI_MODE_3
105
106#ifdef VSF_SPI_QSPI_DUALFLASH_ENABLE
107# define QSPI_DUALFLASH_ENABLE VSF_SPI_QSPI_DUALFLASH_ENABLE
108#else
109# define QSPI_DUALFLASH_ENABLE 0
110#endif
111
112#ifdef VSF_SPI_QSPI_DUALFLASH_DISABLE
113# define QSPI_DUALFLASH_DISABLE VSF_SPI_QSPI_DUALFLASH_DISABLE
114#else
115# define QSPI_DUALFLASH_DISABLE 0
116#endif
117
118#ifdef VSF_SPI_QSPI_FLASH_ID_1
119# define QSPI_FLASH_ID_1 VSF_SPI_QSPI_FLASH_ID_1
120#else
121# define QSPI_FLASH_ID_1 0
122#endif
123
124#ifdef VSF_SPI_QSPI_FLASH_ID_2
125# define QSPI_FLASH_ID_2 VSF_SPI_QSPI_FLASH_ID_2
126#else
127# define QSPI_FLASH_ID_2 0
128#endif
129
130#ifdef VSF_SPI_CTRL_QSPI_ADDRESS_BITS_8
131# define QSPI_ADDRESS_8_BITS VSF_SPI_CTRL_QSPI_ADDRESS_BITS_8
132#else
133# define QSPI_ADDRESS_8_BITS 0
134#endif
135
136#ifdef VSF_SPI_CTRL_QSPI_ADDRESS_BITS_16
137# define QSPI_ADDRESS_16_BITS VSF_SPI_CTRL_QSPI_ADDRESS_BITS_16
138#else
139# define QSPI_ADDRESS_16_BITS 0
140#endif
141
142#ifdef VSF_SPI_CTRL_QSPI_ADDRESS_BITS_24
143# define QSPI_ADDRESS_24_BITS VSF_SPI_CTRL_QSPI_ADDRESS_BITS_24
144#else
145# define QSPI_ADDRESS_24_BITS 0
146#endif
147
148#ifdef VSF_SPI_CTRL_QSPI_ADDRESS_BITS_32
149# define QSPI_ADDRESS_32_BITS VSF_SPI_CTRL_QSPI_ADDRESS_BITS_32
150#else
151# define QSPI_ADDRESS_32_BITS 0
152#endif
153
154#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_8_BITS
155# define QSPI_ALTERNATE_BYTES_8_BITS VSF_SPI_QSPI_ALTERNATE_BYTES_8_BITS
156#else
157# define QSPI_ALTERNATE_BYTES_8_BITS 0
158#endif
159
160#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_16_BITS
161# define QSPI_ALTERNATE_BYTES_16_BITS VSF_SPI_QSPI_ALTERNATE_BYTES_16_BITS
162#else
163# define QSPI_ALTERNATE_BYTES_16_BITS 0
164#endif
165
166#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_24_BITS
167# define QSPI_ALTERNATE_BYTES_24_BITS VSF_SPI_QSPI_ALTERNATE_BYTES_24_BITS
168#else
169# define QSPI_ALTERNATE_BYTES_24_BITS 0
170#endif
171
172#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_32_BITS
173# define QSPI_ALTERNATE_BYTES_32_BITS VSF_SPI_QSPI_ALTERNATE_BYTES_32_BITS
174#else
175# define QSPI_ALTERNATE_BYTES_32_BITS 0
176#endif
177
178#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_NONE
179# define QSPI_ALTERNATE_BYTES_NONE VSF_SPI_QSPI_ALTERNATE_BYTES_NONE
180#else
181# define QSPI_ALTERNATE_BYTES_NONE 0
182#endif
183
184#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_1_LINE
185# define QSPI_ALTERNATE_BYTES_1_LINE VSF_SPI_QSPI_ALTERNATE_BYTES_1_LINE
186#else
187# define QSPI_ALTERNATE_BYTES_1_LINE 0
188#endif
189
190#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_2_LINES
191# define QSPI_ALTERNATE_BYTES_2_LINES VSF_SPI_QSPI_ALTERNATE_BYTES_2_LINES
192#else
193# define QSPI_ALTERNATE_BYTES_2_LINES 0
194#endif
195
196#ifdef VSF_SPI_QSPI_ALTERNATE_BYTES_4_LINES
197# define QSPI_ALTERNATE_BYTES_4_LINES VSF_SPI_QSPI_ALTERNATE_BYTES_4_LINES
198#else
199# define QSPI_ALTERNATE_BYTES_4_LINES 0
200#endif
201
202#define QSPI_INSTRUCTION_NONE 0
203#define QSPI_INSTRUCTION_1_LINE 1
204#define QSPI_INSTRUCTION_2_LINES 2
205#define QSPI_INSTRUCTION_4_LINES 3
206
207#define QSPI_ADDRESS_NONE 0
208#define QSPI_ADDRESS_1_LINE 1
209#define QSPI_ADDRESS_2_LINES 2
210#define QSPI_ADDRESS_4_LINES 3
211
212#ifdef VSF_SPI_QSPI_DATA_NONE
213# define QSPI_DATA_NONE VSF_SPI_CTRL_QSPI_DATA_PHASE_SINGLE
214#else
215# define QSPI_DATA_NONE 0
216#endif
217
218#ifdef VSF_SPI_CTRL_QSPI_DATA_PHASE_SINGLE
219# define QSPI_DATA_1_LINE VSF_SPI_CTRL_QSPI_DATA_PHASE_SINGLE
220#else
221# define QSPI_DATA_1_LINE 0
222#endif
223
224#ifdef VSF_SPI_CTRL_QSPI_DATA_PHASE_DUAL
225# define QSPI_DATA_2_LINES VSF_SPI_CTRL_QSPI_DATA_PHASE_DUAL
226#else
227# define QSPI_DATA_2_LINES 0
228#endif
229
230#ifdef VSF_SPI_CTRL_QSPI_DATA_PHASE_QUAD
231# define QSPI_DATA_4_LINES VSF_SPI_CTRL_QSPI_DATA_PHASE_QUAD
232#else
233# define QSPI_DATA_4_LINES 0
234#endif
235
236#ifdef VSF_SPI_QSPI_DDR_MODE_DISABLE
237# define QSPI_DDR_MODE_DISABLE VSF_SPI_QSPI_DDR_MODE_DISABLE
238#else
239# define QSPI_DDR_MODE_DISABLE 0
240#endif
241
242#ifdef VSF_SPI_QSPI_DDR_MODE_ENABLE
243# define QSPI_DDR_MODE_ENABLE VSF_SPI_QSPI_DDR_MODE_ENABLE
244#else
245# define QSPI_DDR_MODE_ENABLE 0
246#endif
247
248#ifdef VSF_SPI_QSPI_DDR_HHC_ANALOG_DELAY
249# define QSPI_DDR_HHC_ANALOG_DELAY VSF_SPI_QSPI_DDR_HHC_ANALOG_DELAY
250#else
251# define QSPI_DDR_HHC_ANALOG_DELAY 0
252#endif
253
254#ifdef VSF_SPI_QSPI_DDR_HHC_HALF_CLK_DELAY
255# define QSPI_DDR_HHC_HALF_CLK_DELAY VSF_SPI_QSPI_DDR_HHC_HALF_CLK_DELAY
256#else
257# define QSPI_DDR_HHC_HALF_CLK_DELAY 0
258#endif
259
260#ifdef VSF_SPI_QSPI_SIOO_INST_EVERY_CMD
261# define QSPI_SIOO_INST_EVERY_CMD VSF_SPI_QSPI_SIOO_INST_EVERY_CMD
262#else
263# define QSPI_SIOO_INST_EVERY_CMD 0
264#endif
265
266#ifdef VSF_SPI_QSPI_SIOO_INST_ONLY_FIRST_CMD
267# define QSPI_SIOO_INST_ONLY_FIRST_CMD VSF_SPI_QSPI_SIOO_INST_ONLY_FIRST_CMD
268#else
269# define QSPI_SIOO_INST_ONLY_FIRST_CMD 0
270#endif
271
272#ifdef VSF_SPI_QSPI_MATCH_MODE_AND
273# define QSPI_MATCH_MODE_AND VSF_SPI_QSPI_MATCH_MODE_AND
274#else
275# define QSPI_MATCH_MODE_AND 0x00000000U
276#endif
277
278#ifdef VSF_SPI_QSPI_MATCH_MODE_OR
279# define QSPI_MATCH_MODE_OR VSF_SPI_QSPI_MATCH_MODE_OR
280#else
281# define QSPI_MATCH_MODE_OR 0
282#endif
283
284#ifdef VSF_SPI_QSPI_AUTOMATIC_STOP_DISABLE
285# define QSPI_AUTOMATIC_STOP_DISABLE VSF_SPI_QSPI_AUTOMATIC_STOP_DISABLE
286#else
287# define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U
288#endif
289
290#ifdef VSF_SPI_QSPI_AUTOMATIC_STOP_ENABLE
291# define QSPI_AUTOMATIC_STOP_ENABLE VSF_SPI_QSPI_AUTOMATIC_STOP_ENABLE
292#else
293# define QSPI_AUTOMATIC_STOP_ENABLE 0
294#endif
295
296#ifdef VSF_SPI_QSPI_TIMEOUT_COUNTER_DISABLE
297# define QSPI_TIMEOUT_COUNTER_DISABLE VSF_SPI_QSPI_TIMEOUT_COUNTER_DISABLE
298#else
299# define QSPI_TIMEOUT_COUNTER_DISABLE 0
300#endif
301
302#ifdef VSF_SPI_QSPI_TIMEOUT_COUNTER_ENABLE
303# define QSPI_TIMEOUT_COUNTER_ENABLE VSF_SPI_QSPI_TIMEOUT_COUNTER_ENABLE
304#else
305# define QSPI_TIMEOUT_COUNTER_ENABLE 0
306#endif
307
308#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U
309
310#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
311#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
312#define IS_QSPI_SSHIFT(SSHIFT) \
313 (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
314 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
315#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
316#define IS_QSPI_CS_HIGH_TIME(CSHTIME) \
317 (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
318 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
319 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
320 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
321 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
322 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
323 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
324 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
325#define IS_QSPI_CLOCK_MODE(CLKMODE) \
326 (((CLKMODE) == QSPI_CLOCK_MODE_0) || ((CLKMODE) == QSPI_CLOCK_MODE_3))
327#define IS_QSPI_FLASH_ID(FLASH_ID) \
328 (((FLASH_ID) == QSPI_FLASH_ID_1) || ((FLASH_ID) == QSPI_FLASH_ID_2))
329#define IS_QSPI_DUAL_FLASH_MODE(MODE) \
330 (((MODE) == QSPI_DUALFLASH_ENABLE) || ((MODE) == QSPI_DUALFLASH_DISABLE))
331#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
332#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) \
333 (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
334 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
335 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
336 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
337#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) \
338 (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
339 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
340 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
341 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
342#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
343#define IS_QSPI_INSTRUCTION_MODE(MODE) \
344 (((MODE) == QSPI_INSTRUCTION_NONE) || \
345 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
346 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
347 ((MODE) == QSPI_INSTRUCTION_4_LINES))
348#define IS_QSPI_ADDRESS_MODE(MODE) \
349 (((MODE) == QSPI_ADDRESS_NONE) || ((MODE) == QSPI_ADDRESS_1_LINE) || \
350 ((MODE) == QSPI_ADDRESS_2_LINES) || ((MODE) == QSPI_ADDRESS_4_LINES))
351#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) \
352 (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
353 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
354 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
355 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
356#define IS_QSPI_DATA_MODE(MODE) \
357 (((MODE) == QSPI_DATA_NONE) || ((MODE) == QSPI_DATA_1_LINE) || \
358 ((MODE) == QSPI_DATA_2_LINES) || ((MODE) == QSPI_DATA_4_LINES))
359#define IS_QSPI_DDR_MODE(DDR_MODE) \
360 (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
361 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
362#define IS_QSPI_DDR_HHC(DDR_HHC) \
363 (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
364 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
365#define IS_QSPI_SIOO_MODE(SIOO_MODE) \
366 (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
367 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
368#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFUL)
369#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
370#define IS_QSPI_MATCH_MODE(MODE) \
371 (((MODE) == QSPI_MATCH_MODE_AND) || ((MODE) == QSPI_MATCH_MODE_OR))
372#define IS_QSPI_AUTOMATIC_STOP(APMS) \
373 (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
374 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
375#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) \
376 (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
377 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
378#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
379
380/*============================ MACROFIED FUNCTIONS ===========================*/
381/*============================ TYPES =========================================*/
382
383typedef vsf_spi_t QUADSPI_TypeDef;
384
385typedef struct {
386 uint32_t ClockPrescaler;
387 uint32_t FifoThreshold;
388 uint32_t SampleShifting;
389 uint32_t FlashSize;
390 uint32_t ChipSelectHighTime;
391 uint32_t ClockMode;
392 uint32_t FlashID;
393 uint32_t DualFlash;
394} QSPI_InitTypeDef;
395
396typedef enum {
397 HAL_QSPI_STATE_RESET = 0x00U,
398 HAL_QSPI_STATE_READY = 0x01U,
399 HAL_QSPI_STATE_BUSY = 0x02U,
400 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
401 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U,
402 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,
403 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U,
404 HAL_QSPI_STATE_ABORT = 0x08U,
405 HAL_QSPI_STATE_ERROR = 0x04U
406} HAL_QSPI_StateTypeDef;
407
408typedef struct {
409 /* 指令相关 */
410 uint32_t Instruction; /* QSPI 指令码 */
411 uint32_t InstructionMode; /* 指令传输模式 (无/单线/双线/四线) */
412 uint32_t SIOOMode; /* 指令只在首次发送还是每次命令都发送 */
413
414 /* 地址相关 */
415 uint32_t Address; /* QSPI 地址 */
416 uint32_t AddressSize; /* 地址大小 (8/16/24/32位) */
417 uint32_t AddressMode; /* 地址传输模式 (无/单线/双线/四线) */
418
419 /* 交替字节相关 */
420 uint32_t AlternateBytes; /* QSPI 交替字节 */
421 uint32_t AlternateBytesSize; /* 交替字节大小 (8/16/24/32位) */
422 uint32_t AlternateByteMode; /* 交替字节传输模式 (无/单线/双线/四线) */
423
424 /* 数据相关 */
425 uint32_t DataMode; /* 数据传输模式 (无/单线/双线/四线) */
426 uint32_t NbData; /* 要传输的数据字节数 */
427
428 /* 时序控制相关 */
429 uint32_t DummyCycles; /* 空周期数 */
430 uint32_t DdrMode; /* 是否启用 DDR 模式 */
431 uint32_t DdrHoldHalfCycle; /* DDR 模式下的半周期保持配置 */
432} QSPI_CommandTypeDef;
433
434typedef struct {
435 uint32_t Match;
436 uint32_t Mask;
437 uint32_t Interval;
438 uint32_t StatusBytesSize;
439 uint32_t MatchMode;
440 uint32_t AutomaticStop;
441} QSPI_AutoPollingTypeDef;
442
443typedef struct {
444 uint32_t TimeOutPeriod;
445 uint32_t TimeOutActivation;
446} QSPI_MemoryMappedTypeDef;
447
448#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
449typedef enum {
450 HAL_QSPI_ERROR_CB_ID = 0x00U,
451 HAL_QSPI_ABORT_CB_ID = 0x01U,
452 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,
453 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U,
454 HAL_QSPI_RX_CPLT_CB_ID = 0x04U,
455 HAL_QSPI_TX_CPLT_CB_ID = 0x05U,
456 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U,
457 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U,
458 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U,
459 HAL_QSPI_TIMEOUT_CB_ID = 0x09U,
460 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU,
461 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0BU
462} HAL_QSPI_CallbackIDTypeDef;
463typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
464#endif
465
466typedef struct __QSPI_HandleTypeDef {
467 QUADSPI_TypeDef *Instance;
468 QSPI_InitTypeDef Init;
469 uint8_t *pTxBuffPtr;
470 volatile uint32_t TxXferSize;
471 volatile uint32_t TxXferCount;
472 uint8_t *pRxBuffPtr;
473 volatile uint32_t RxXferSize;
474 volatile uint32_t RxXferCount;
475 DMA_HandleTypeDef *hdma;
476 volatile HAL_LockTypeDef Lock;
477 volatile HAL_QSPI_StateTypeDef State;
478 volatile uint32_t ErrorCode;
479 uint32_t Timeout;
480
481 uint32_t NbData;
482 uint32_t DummyCycles; /* Flash ID for dual flash mode */
483#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
484 void (*ErrorCallback)(struct __QSPI_HandleTypeDef *hqspi);
485 void (*AbortCpltCallback)(struct __QSPI_HandleTypeDef *hqspi);
486 void (*FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
487 void (*CmdCpltCallback)(struct __QSPI_HandleTypeDef *hqspi);
488 void (*RxCpltCallback)(struct __QSPI_HandleTypeDef *hqspi);
489 void (*TxCpltCallback)(struct __QSPI_HandleTypeDef *hqspi);
490 void (*RxHalfCpltCallback)(struct __QSPI_HandleTypeDef *hqspi);
491 void (*TxHalfCpltCallback)(struct __QSPI_HandleTypeDef *hqspi);
492 void (*StatusMatchCallback)(struct __QSPI_HandleTypeDef *hqspi);
493 void (*TimeOutCallback)(struct __QSPI_HandleTypeDef *hqspi);
494 void (*MspInitCallback)(struct __QSPI_HandleTypeDef *hqspi);
495 void (*MspDeInitCallback)(struct __QSPI_HandleTypeDef *hqspi);
496#endif
497} QSPI_HandleTypeDef;
498
499/*============================ GLOBAL VARIABLES ==============================*/
500/*============================ PROTOTYPES ====================================*/
501
502HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi);
503HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi);
504void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi);
505void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
506
507#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
508HAL_StatusTypeDef HAL_QSPI_RegisterCallback(
509 QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId,
510 pQSPI_CallbackTypeDef pCallback);
511HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback(
512 QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
513#endif
514
515HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi,
516 QSPI_CommandTypeDef *cmd, uint32_t Timeout);
517HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData,
518 uint32_t Timeout);
519HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData,
520 uint32_t Timeout);
521HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi,
522 QSPI_CommandTypeDef *cmd);
523HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi,
524 uint8_t *pData);
525HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi,
526 uint8_t *pData);
527HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi,
528 uint8_t *pData);
529HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi,
530 uint8_t *pData);
531HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi,
532 QSPI_CommandTypeDef *cmd,
533 QSPI_AutoPollingTypeDef *cfg,
534 uint32_t Timeout);
535HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi,
536 QSPI_CommandTypeDef *cmd,
537 QSPI_AutoPollingTypeDef *cfg);
538HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi,
539 QSPI_CommandTypeDef *cmd,
540 QSPI_MemoryMappedTypeDef *cfg);
541void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi);
542void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi);
543void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
544void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi);
545void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi);
546void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi);
547void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi);
548void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi);
549void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi);
550void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi);
551HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi);
552uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi);
553HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi);
554HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi);
555void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
556HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi,
557 uint32_t Threshold);
558uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
559HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi,
560 uint32_t FlashID);
561
562#endif /* defined(HAL_QSPI_MODULE_ENABLED) && VSF_HAL_USE_SPI == ENABLED && defined(VSF_SPI_CTRL_QSPI_ENABLE) */
563
564#ifdef __cplusplus
565}
566#endif
567
568#endif /* __ST_HAL_QSPI_H__ */
Init
vsf_err_t(* Init)(vsf_adc_cfg_t *pCfg)
Definition adc_interface.h:38
uint32_t
unsigned uint32_t
Definition stdint.h:9
uint8_t
unsigned char uint8_t
Definition stdint.h:5
sthal_def.h
HAL_StatusTypeDef
HAL_StatusTypeDef
Definition sthal_def.h:61
HAL_LockTypeDef
HAL_LockTypeDef
Definition sthal_def.h:68
vsf_spi_t
SPI instance structure, used for SPI Multi Class support, not needed in non Multi Class mode.
Definition vsf_template_spi.h:990
Generated from commit: vsfteam/vsf@ece1bff