#include "./vsf_wifi_mt76.h"
#include "../../vsf_wifi_priv.h"

Data Structures
struct	mt76_rate_power_t

struct	mt76_tx_power_info_t

struct	mt76_reg_pair_t

struct	mt76_channel_cfg_t

Macros
#define	VSF_WIFI_MT76_CFG_FORCE_SW_CCMP_TX ENABLED

#define	MT76_VEND_TYPE_CFG ((uint32_t)1 << 30)

#define	MT76_ASIC_VERSION 0x0000

#define	MT76_USB_U3DMA_CFG (MT76_VEND_TYPE_CFG \| 0x9018)

#define	MT76_USB_DMA_CFG_RX_DROP_OR_PAD (1U << 18)

#define	MT76_USB_DMA_CFG_RX_BULK_AGG_EN (1U << 21)

#define	MT76_USB_DMA_CFG_RX_BULK_EN (1U << 22)

#define	MT76_USB_DMA_CFG_TX_BULK_EN (1U << 23)

#define	MT76_WPDMA_GLO_CFG 0x0208

#define	MT76_MAC_SYS_CTRL 0x1004

#define	MT76_MAC_SYS_CTRL_RESET_CSR (1U << 0)

#define	MT76_MAC_SYS_CTRL_RESET_BBP (1U << 1)

#define	MT76_MAC_SYS_CTRL_ENABLE_TX (1U << 2)

#define	MT76_MAC_SYS_CTRL_ENABLE_RX (1U << 3)

#define	MT76_RX_FILTR_CFG 0x1400

#define	MT76_FCE_DMA_ADDR 0x0230

#define	MT76_FCE_DMA_LEN 0x0234

#define	MT76_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09A8

#define	MT76_TX_CPU_FROM_FCE_BASE_PTR 0x09A0

#define	MT76_TX_CPU_FROM_FCE_MAX_COUNT 0x09A4

#define	MT76_FCE_PSE_CTRL 0x0800

#define	MT76_FCE_PDMA_GLOBAL_CONF 0x09C4

#define	MT76_FCE_SKIP_FS 0x0A6C

#define	MT76_MCU_COM_REG0 0x0730

#define	MT76_MCU_CLOCK_CTL 0x0708

#define	MT76_MCU_RESET_CTL 0x070C

#define	MT76_MCU_SEMAPHORE_03 0x07BC

#define	MT76_REV_E3 0x22

#define	MT76_CHIP_ID_7612 0x7612

#define	MT76_CHIP_ID_7632 0x7632

#define	MT76_CHIP_ID_7662 0x7662

#define	MT76_CHIP_ID_7602 0x7602

#define	MT76_PATCH_HDR_SIZE 30

#define	MT76_FW_HDR_SIZE 32

#define	MT76_ROM_PATCH_OFFSET 0x00090000

#define	MT76_ILM_OFFSET 0x00080000

#define	MT76_DLM_OFFSET 0x00110000

#define	MT76_DLM_OFFSET_E3_EXTRA 0x00000800

#define	MT76_USB_DMA_CFG_VAL 0x00C00020

#define	MT76_WLAN_FUN_CTRL 0x0080

#define	MT76_WLAN_FUN_CTRL_WLAN_EN (1U << 0)

#define	MT76_WLAN_FUN_CTRL_WLAN_CLK_EN (1U << 1)

#define	MT76_WLAN_FUN_CTRL_WLAN_RESET_RF (1U << 2)

#define	MT76_WLAN_FUN_CTRL_FRC_WL_ANT_SEL (1U << 5)

#define	MT76_WLAN_MTC_CTRL (0x40000000 \| 0x148)

#define	MT76_WLAN_MTC_CTRL_MTCMOS_PWR_UP (1U << 0)

#define	MT76_WLAN_MTC_CTRL_PWR_ACK (1U << 12)

#define	MT76_WLAN_MTC_CTRL_PWR_ACK_S (1U << 13)

#define	MT76_WLAN_MTC_CTRL_STATE_UP (1U << 28)

#define	MT76_MAC_CSR0 0x1000

#define	MT76_WPDMA_GLO_CFG_TX_DMA_EN (1U << 0)

#define	MT76_WPDMA_GLO_CFG_TX_DMA_BUSY (1U << 1)

#define	MT76_WPDMA_GLO_CFG_RX_DMA_EN (1U << 2)

#define	MT76_WPDMA_GLO_CFG_RX_DMA_BUSY (1U << 3)

#define	MT76_US_CYC_CFG 0x02a4

#define	MT76_US_CYC_CNT 0x1e

#define	MT76_PBF_SYS_CTRL 0x0400

#define	MT76_PBF_CFG 0x0404

#define	MT76_PBF_TX_MAX_PCNT 0x0408

#define	MT76_PBF_RX_MAX_PCNT 0x040c

#define	MT76_BCN_OFFSET_BASE 0x041c

#define	MT76_BCN_OFFSET(_n)

#define	MT76_MAC_ADDR_DW0 0x1008

#define	MT76_MAC_ADDR_DW1 0x100c

#define	MT76_MAC_ADDR_DW1_U2ME_MASK 0x00ff0000

#define	MT76_MAC_BSSID_DW0 0x1010

#define	MT76_MAC_BSSID_DW1 0x1014

#define	MT76_MAC_BSSID_DW1_MBSS_MODE (3U << 16)

#define	MT76_MAC_BSSID_DW1_MBSS_LOCAL_BIT (1U << 21)

#define	MT76_MAC_BSSID_DW1_MBEACON_N_SHIFT 18

#define	MT76_MAX_LEN_CFG 0x1018

#define	MT76_AMPDU_MAX_LEN_20M1S 0x1030

#define	MT76_AMPDU_MAX_LEN_20M2S 0x1034

#define	MT76_BCN_BYPASS_MASK 0x108c

#define	MT76_XIFS_TIME_CFG 0x1100

#define	MT76_BKOFF_SLOT_CFG 0x1104

#define	MT76_BEACON_TIME_CFG 0x1114

#define	MT76_BEACON_TIME_CFG_INTVAL_MASK 0xFFFFu

#define	MT76_BEACON_TIME_CFG_TIMER_EN (1U << 16)

#define	MT76_BEACON_TIME_CFG_SYNC_MODE (3U << 17)

#define	MT76_BEACON_TIME_CFG_SYNC_MODE_STA (1U << 17)

#define	MT76_BEACON_TIME_CFG_TBTT_EN (1U << 19)

#define	MT76_TBTT_SYNC_CFG 0x1118

#define	MT76_MAC_STATUS 0x1200

#define	MT76_MAC_STATUS_TX (1U << 0)

#define	MT76_MAC_STATUS_RX (1U << 1)

#define	MT76_PWR_PIN_CFG 0x1204

#define	MT76_AUX_CLK_CFG 0x120c

#define	MT76_DACCLK_EN_DLY_CFG 0x1264

#define	MT76_TX_SW_CFG0 0x1330

#define	MT76_TX_SW_CFG1 0x1334

#define	MT76_TX_SW_CFG2 0x1338

#define	MT76_TXOP_CTRL_CFG 0x1340

#define	MT76_TXOP_ED_CCA_EN (1U << 20)

#define	MT76_TX_RTS_CFG 0x1344

#define	MT76_TX_RTS_CFG_RETRY_LIMIT 0x000000FF

#define	MT76_TX_TIMEOUT_CFG 0x1348

#define	MT76_FCE_L2_STUFF 0x080c

#define	MT76_FCE_L2_STUFF_WR_MPDU_LEN_EN (1U << 4)

#define	MT76_RF_BYPASS_0 0x0504

#define	MT76_RF_SETTING_0 0x050c

#define	MT76_TX_RETRY_CFG 0x134c

#define	MT76_PIFS_TX_CFG 0x1388

#define	MT76_TX_LINK_CFG 0x1350

#define	MT76_HEADER_TRANS_CTRL_REG 0x0260

#define	MT76_TSO_CTRL 0x0250

#define	MT76_TX_ALC_VGA3 0x0778

#define	MT76_VHT_HT_FBK_CFG1 0x1358

#define	MT76_CCK_PROT_CFG 0x1364

#define	MT76_OFDM_PROT_CFG 0x1368

#define	MT76_MM20_PROT_CFG 0x136c

#define	MT76_MM40_PROT_CFG 0x1370

#define	MT76_GF20_PROT_CFG 0x1374

#define	MT76_GF40_PROT_CFG 0x1378

#define	MT76_EXP_ACK_TIME 0x1380

#define	MT76_TX_BAND_CFG 0x132c

#define	MT76_TX_BAND_CFG_UPPER_40M (1U << 0)

#define	MT76_TX_BAND_CFG_5G (1U << 1)

#define	MT76_TX_BAND_CFG_2G (1U << 2)

#define	MT76_EXT_CCA_CFG 0x141c

#define	MT76_EXT_CCA_CFG_CCA0_M 0x00000003

#define	MT76_EXT_CCA_CFG_CCA1_M 0x0000000c

#define	MT76_EXT_CCA_CFG_CCA2_M 0x00000030

#define	MT76_EXT_CCA_CFG_CCA3_M 0x000000c0

#define	MT76_EXT_CCA_CFG_CCA_MASK_M 0x00000f00

#define	MT76_BBP_CORE_BASE 0x2000

#define	MT76_BBP_AGC_BASE 0x2300

#define	MT76_BBP_TXO_BASE 0x2600

#define	MT76_BBP_TXBE_BASE 0x2700

#define	MT76_BBP_RXO_BASE 0x2900

#define	MT76_BBP(_type, _n)

#define	MT76_BBP_CORE_R1_BW_M (3U << 3) /* bits 4:3 */

#define	MT76_BBP_CORE_R1_BW_20 (0U << 3)

#define	MT76_BBP_CORE_R1_BW_40 (2U << 3)

#define	MT76_BBP_CORE_R1_BW_80 (3U << 3)

#define	MT76_BBP_AGC_R0_BW_M (7U << 12) /* bits 14:12 */

#define	MT76_BBP_AGC_R0_BW_20 (1U << 12)

#define	MT76_BBP_AGC_R0_BW_40 (3U << 12)

#define	MT76_BBP_AGC_R0_BW_80 (7U << 12)

#define	MT76_BBP_AGC_R0_CTRL_CHAN_M (3U << 8) /* bits 9:8 */

#define	MT76_BBP_TXBE_R0_CTRL_CHAN_M (3U << 0) /* bits 1:0 */

#define	MT_TX_STAT_FIFO 0x1718

#define	MT_TX_STAT_FIFO_VALID (1U << 0)

#define	MT_TX_STAT_FIFO_SUCCESS (1U << 5)

#define	MT_TX_STAT_FIFO_AGGR (1U << 6)

#define	MT_TX_STAT_FIFO_ACKREQ (1U << 7)

#define	MT_TX_STAT_FIFO_WCID_M 0x0000FF00

#define	MT_TX_STAT_FIFO_WCID_S 8

#define	MT_TX_STAT_FIFO_RATE_M 0xFFFF0000

#define	MT_TX_STAT_FIFO_RATE_S 16

#define	MT_TX_STAT_FIFO_EXT 0x1798

#define	MT_TX_STAT_FIFO_EXT_RETRY_M 0x000000FF

#define	MT_TX_STAT_FIFO_EXT_RETRY_S 0

#define	MT_TX_STAT_FIFO_EXT_PKTID_M 0x0000FF00

#define	MT_TX_STAT_FIFO_EXT_PKTID_S 8

#define	MT76_PACKET_ID_HAS_RATE 0x80

#define	MT76_PKTID_RATE_M 0x1F

#define	MT76_HT_FBK_TO_LEGACY 0x1384

#define	MT76_TX_PROT_CFG6 0x13e0

#define	MT76_TX_PROT_CFG7 0x13e4

#define	MT76_TX_PROT_CFG8 0x13e8

#define	MT76_TX_PWR_CFG_0 0x1314

#define	MT76_TX_PWR_CFG_1 0x1318

#define	MT76_TX_PWR_CFG_2 0x131c

#define	MT76_TX_PWR_CFG_3 0x1320

#define	MT76_TX_PWR_CFG_4 0x1324

#define	MT76_TX_PWR_CFG_7 0x13d4

#define	MT76_TX_PWR_CFG_8 0x13d8

#define	MT76_TX_PWR_CFG_9 0x13dc

#define	MT76_BB_PA_MODE_CFG0 0x1214

#define	MT76_BB_PA_MODE_CFG1 0x1218

#define	MT76_RF_PA_MODE_CFG0 0x121c

#define	MT76_RF_PA_MODE_CFG1 0x1220

#define	MT76_RF_PA_MODE_ADJ0 0x1228

#define	MT76_RF_PA_MODE_ADJ1 0x122c

#define	MT76_TX_SW_CFG0 0x1330

#define	MT76_TX_SW_CFG1 0x1334

#define	MT76_TX0_RF_GAIN_CORR 0x13a0

#define	MT76_TX1_RF_GAIN_CORR 0x13a4

#define	MT76_TX_ALC_CFG_0 0x13b0

#define	MT76_TX_ALC_CFG_0_CH_INIT_0_M 0x0000003f

#define	MT76_TX_ALC_CFG_0_CH_INIT_0_S 0

#define	MT76_TX_ALC_CFG_0_CH_INIT_1_M 0x00003f00

#define	MT76_TX_ALC_CFG_0_CH_INIT_1_S 8

#define	MT76_TX_ALC_CFG_0_LIMIT_0_M 0x003f0000

#define	MT76_TX_ALC_CFG_0_LIMIT_0_S 16

#define	MT76_TX_ALC_CFG_0_LIMIT_1_M 0x3f000000

#define	MT76_TX_ALC_CFG_0_LIMIT_1_S 24

#define	MT76_TX_ALC_CFG_2 0x13a8

#define	MT76_TX_ALC_CFG_3 0x13ac

#define	MT76_XIFS_TIME_CFG 0x1100

#define	MT76_XIFS_TIME_CFG_OFDM_SIFS_M 0x0000ff00

#define	MT76_XIFS_TIME_CFG_OFDM_SIFS_S 8

#define	MT76_LEGACY_BASIC_RATE 0x1408

#define	MT76_HT_BASIC_RATE 0x140c

#define	MT76_HT_CTRL_CFG 0x1410

#define	MT76_TX_SW_CFG3 0x1478

#define	MT76_PN_PAD_MODE 0x150c

#define	MT76_TXOP_HLDR_ET 0x1608

#define	MT76_TXOP_HLDR_TX40M_BLK_EN (1U << 1)

#define	MT76_PROT_AUTO_TX_CFG 0x1648

#define	MT76_EFUSE_CTRL 0x0024

#define	MT76_PAUSE_ENABLE_CONTROL1 0x0a38

#define	MT76_FCE_WLAN_FLOW_CONTROL1 0x0824

#define	MT76_WPDMA_DELAY_INT_CFG 0x0210

#define	MT76_WCID_ATTR_BASE 0xa800

#define	MT76_WCID_ATTR(_n)

#define	MT76_WCID_ATTR_PAIRWISE (1U << 0)

#define	MT76_WCID_ATTR_PKEY_MODE (0x7U << 1)

#define	MT76_WCID_ATTR_PKEY_MODE_SHIFT 1

#define	MT76_WCID_ATTR_BSS_IDX (0U << 4)

#define	MT76_WCID_ATTR_BSS_IDX_EXT (1U << 11)

#define	MT76_WCID_ADDR_BASE 0x1800

#define	MT76_WCID_ADDR(_n)

#define	MT76_WCID_DROP_BASE 0x106c

#define	MT76_WCID_DROP(_n)

#define	MT76_WCID_DROP_MASK(_n)

#define	MT76_WCID_TX_INFO_BASE 0x1c00

#define	MT76_WCID_TX_INFO(_n)

#define	MT76_WCID_KEY_BASE 0x8000

#define	MT76_WCID_KEY(_n)

#define	MT76_WCID_IV_BASE 0xa000

#define	MT76_WCID_IV(_n)

#define	MT_VIF_WCID(_n)

#define	MT76_SKEY_MODE_MASK 0xFU

#define	MT76_SKEY_MODE_SHIFT(_bss, _idx)

#define	MT_WCID_TX_INFO_RATE 0x0000FFFFU

#define	MT_WCID_TX_INFO_RATE_S 0

#define	MT_WCID_TX_INFO_NSS_SHIFT 16

#define	MT_WCID_TX_INFO_NSS_MASK 0x00030000U

#define	MT_WCID_TX_INFO_TXPWR_ADJ_SHIFT 18

#define	MT_WCID_TX_INFO_TXPWR_ADJ_MASK 0x03FC0000U

#define	MT_WCID_TX_INFO_SET 0x80000000U

#define	MT76_SKEY_BASE_0 0xac00

#define	MT76_SKEY_BASE_1 0xb400

#define	MT76_SKEY(_bss, _idx)

#define	MT76_SKEY_MODE_BASE_0 0xb000

#define	MT76_SKEY_MODE_BASE_1 0xb3f0

#define	MT76_SKEY_MODE(_bss)

#define	MT76_BBP_CORE_BASE 0x2000

#define	MT76_BBP_IBI_BASE 0x2100

#define	MT76_BBP_AGC_BASE 0x2300

#define	MT76_BBP_TXO_BASE 0x2600

#define	MT76_BBP_TXBE_BASE 0x2700

#define	MT76_BBP_RXO_BASE 0x2900

#define	MT76_BBP(_type, _n)

#define	MT76_BBP_TXO_4_TX_CMM_BW (1U << 25)

#define	MT76_BBP_RXO_13_RX_CMM_PD_EN (1U << 8)

#define	MT76_BBP_RXO_13_LDPC_RX_EN (1U << 10)

#define	MT76_XO_CTRL5 0x0114

#define	MT76_XO_CTRL5_C2_VAL_MASK 0x7f00

#define	MT76_XO_CTRL5_C2_VAL_SHIFT 8

#define	MT76_XO_CTRL6 0x0118

#define	MT76_XO_CTRL6_C2_CTRL_MASK 0x7f00

#define	MT76_XO_CTRL6_C2_CTRL_SHIFT 8

#define	MT76_XO_CTRL7 0x011c

#define	MT76_COEXCFG0 0x0040

#define	MT76_COEXCFG0_COEX_EN (1U << 0)

#define	MT76_TX_ALC_CFG_4 0x077c

#define	MT76_TX_ALC_CFG_4_MPDU_2ND_TC (1U << 31)

#define	MT76_AUTO_RSP_CFG 0x110c

#define	MT76_WMM_AIFSN 0x0214

#define	MT76_WMM_CWMIN 0x0218

#define	MT76_WMM_CWMAX 0x021c

#define	MT76_WMM_TXOP_BASE 0x0220

#define	MT76_WMM_TXOP(_n)

#define	MT76_EDCA_CFG_BASE 0x1300

#define	MT76_EDCA_CFG_AC(_n)

#define	MT76_TXOP_THRES_CFG 0x13ec

#define	MT76_MCU_MSG_CMD_LOAD_CR 2

#define	MT76_RF_BBP_CR 2

#define	MT76_MCU_MSG_TYPE_CMD ((uint32_t)1 << 30)

#define	MT76_MCU_MSG_CMD_TYPE_SHIFT 20

#define	MT76_MCU_MSG_CMD_SEQ_SHIFT 16

#define	MT76_MCU_MSG_PORT_SHIFT 27

#define	MT76_MCU_MSG_LEN_MASK 0xFFFF

#define	MT76_TXD_INFO_LEN_MASK 0xFFFF

#define	MT76_TXD_INFO_DPORT_SHIFT 27

#define	MT76_TXD_INFO_TYPE_CMD ((uint32_t)1 << 30)

#define	MT76_CPU_TX_PORT 2

#define	MT76_WLAN_PORT 0

#define	MT76_VEND_DEV_MODE 0x01

#define	MT76_FW_PATCH_CHUNK_PAYLOAD (2048 - 8)

#define	MT76_FW_FW_CHUNK_PAYLOAD (MT76_TX_URB_SIZE - 8)

#define	MT76_CMD_FUN_SET_OP 1

#define	MT76_CMD_POWER_SAVING_OP 20

#define	MT76_FUN_Q_SELECT 1

#define	MT76_PWR_RADIO_ON 0x31

#define	MT76_PWR_RADIO_OFF 0x30

#define	MT_EE_READ 0

#define	MT76_EE_MAC_ADDR 0x004

#define	MT76_EE_NIC_CONF_0 0x034

#define	MT76_EE_NIC_CONF_1 0x036

#define	MT76_EE_XTAL_TRIM_1 0x03a

#define	MT76_EE_XTAL_TRIM_2 0x09e

#define	MT76_EE_NIC_CONF_2 0x042

#define	MT76_EE_LNA_GAIN 0x044

#define	MT76_EE_RSSI_OFFSET_2G_0 0x046

#define	MT76_EE_RSSI_OFFSET_2G_1 0x048

#define	MT76_EE_LNA_GAIN_5GHZ_1 0x049

#define	MT76_EE_RSSI_OFFSET_5G_0 0x04a

#define	MT76_EE_RSSI_OFFSET_5G_1 0x04c

#define	MT76_EE_LNA_GAIN_5GHZ_2 0x04d

#define	MT76_EE_TX_POWER_DELTA_BW40 0x050

#define	MT76_EE_TX_POWER_DELTA_BW80 0x052

#define	MT76_EE_TX_POWER_EXT_PA_5G 0x054

#define	MT76_EE_TX_POWER_0_START_2G 0x056

#define	MT76_EE_TX_POWER_1_START_2G 0x05c

#define	MT76_EE_TX_POWER_0_START_5G 0x062

#define	MT76_EE_TX_POWER_1_START_5G 0x080

#define	MT76_EE_TX_POWER_CCK 0x0a0

#define	MT76_EE_TX_POWER_OFDM_2G_6M 0x0a2

#define	MT76_EE_TX_POWER_OFDM_2G_24M 0x0a4

#define	MT76_EE_TX_POWER_OFDM_5G_6M 0x0b2

#define	MT76_EE_TX_POWER_OFDM_5G_24M 0x0b4

#define	MT76_EE_TX_POWER_HT_MCS0 0x0a6

#define	MT76_EE_TX_POWER_HT_MCS4 0x0a8

#define	MT76_EE_TX_POWER_HT_MCS8 0x0aa

#define	MT76_EE_TX_POWER_HT_MCS12 0x0ac

#define	MT76_EE_TX_POWER_VHT_MCS8 0x0be

#define	MT76_EE_2G_TARGET_POWER 0x0d0

#define	MT76_EE_5G_TARGET_POWER 0x0d2

#define	MT76_EE_RF_2G_TSSI_OFF_TXPOWER 0x0f6

#define	MT76_EE_RF_2G_RX_HIGH_GAIN 0x0f8

#define	MT76_EE_RF_5G_GRP0_1_RX_HIGH_GAIN 0x0fa

#define	MT76_EE_RF_5G_GRP2_3_RX_HIGH_GAIN 0x0fc

#define	MT76_EE_RF_5G_GRP4_5_RX_HIGH_GAIN 0x0fe

#define	MT76_TX_POWER_GROUP_SIZE_5G 5

#define	MT76_TX_POWER_GROUPS_5G 6

#define	MT76_EE_NIC_CONF_0_PA_INT_2G (1U << 8)

#define	MT76_EE_NIC_CONF_0_PA_INT_5G (1U << 9)

#define	MT76_EE_NIC_CONF_1_TEMP_TX_ALC (1U << 1)

#define	MT76_EE_NIC_CONF_1_TX_ALC_EN (1U << 13)

#define	MT76_EE_NIC_CONF_1_LNA_EXT_2G (1U << 2)

#define	MT76_EE_NIC_CONF_1_LNA_EXT_5G (1U << 3)

#define	MT76_EE_TX_POWER_EXT_PA_5G_EN (1U << 15)

#define	MT76_MAX_TX_POWER_OPS 32

#define	MT76_CMD_INIT_GAIN_OP 3

#define	MT76_CMD_SWITCH_CHANNEL_OP 30

#define	MT76_CMD_CALIBRATION_OP 31

#define	MT76_MCU_CAL_R 1

#define	MT76_MCU_CAL_RXDCOC 2

#define	MT76_MCU_CAL_RC 3

#define	MT_RX_FILTR_CFG 0x1400

#define	MT_RX_FILTR_CFG_CRC_ERR (1U << 0)

#define	MT_RX_FILTR_CFG_PHY_ERR (1U << 1)

#define	MT_RX_FILTR_CFG_PROMISC (1U << 2)

#define	MT_RX_FILTR_CFG_OTHER_BSS (1U << 3)

#define	MT_RX_FILTR_CFG_VER_ERR (1U << 4)

#define	MT_RX_FILTR_CFG_MCAST (1U << 5)

#define	MT_RX_FILTR_CFG_BCAST (1U << 6)

#define	MT_RX_FILTR_CFG_DUP (1U << 7)

#define	MT_RX_FILTR_CFG_CFACK (1U << 8)

#define	MT_RX_FILTR_CFG_CFEND (1U << 9)

#define	MT_RX_FILTR_CFG_ACK (1U << 10)

#define	MT_RX_FILTR_CFG_CTS (1U << 11)

#define	MT_RX_FILTR_CFG_RTS (1U << 12)

#define	MT_RX_FILTR_CFG_PSPOLL (1U << 13)

#define	MT_RX_FILTR_CFG_BA (1U << 14)

#define	MT_RX_FILTR_CFG_BAR (1U << 15)

#define	MT_RX_FILTR_CFG_CTRL_RSV (1U << 16)

#define	MT_RX_FILTR_CFG_DEFAULT 0x00015f97

#define	MT_TXD_INFO_LEN_MASK 0x0000FFFF

#define	MT_TXD_INFO_NEXT_VLD (1U << 16)

#define	MT_TXD_INFO_TX_BURST (1U << 17)

#define	MT_TXD_INFO_80211 (1U << 19)

#define	MT_TXD_INFO_TSO (1U << 20)

#define	MT_TXD_INFO_CSO (1U << 21)

#define	MT_TXD_INFO_WIV (1U << 24)

#define	MT_TXD_INFO_QSEL_MASK (3U << 25)

#define	MT_TXD_INFO_QSEL_SHIFT 25

#define	MT_TXD_INFO_DPORT_MASK (7U << 27)

#define	MT_TXD_INFO_DPORT_SHIFT 27

#define	MT_TXD_INFO_TYPE_MASK (3U << 30)

#define	MT_QSEL_MGMT 0

#define	MT_QSEL_EDCA 2

#define	MT_WLAN_PORT 0

#define	MT_TXWI_FLAGS_FRAG (1U << 0)

#define	MT_TXWI_FLAGS_MMPS (1U << 1)

#define	MT_TXWI_FLAGS_CFACK (1U << 2)

#define	MT_TXWI_FLAGS_TS (1U << 3)

#define	MT_TXWI_FLAGS_AMPDU (1U << 4)

#define	MT_TXWI_FLAGS_MPDU_DENSITY_MASK (7U << 5)

#define	MT_TXWI_FLAGS_TXOP_MASK (3U << 8)

#define	MT_TXWI_FLAGS_NDPS (1U << 10)

#define	MT_TXWI_FLAGS_RTSBWSIG (1U << 11)

#define	MT_TXWI_FLAGS_NDP_BW_MASK (3U << 12)

#define	MT_TXWI_FLAGS_SOUND (1U << 14)

#define	MT_TXWI_FLAGS_TX_RATE_LUT (1U << 15)

#define	MT_TXWI_ACK_CTL_REQ (1U << 0)

#define	MT_TXWI_ACK_CTL_NSEQ (1U << 1)

#define	MT_TXWI_ACK_CTL_BA_WINDOW_MASK (0x3FU << 2)

#define	MT_RXWI_RATE_INDEX_MASK 0x003F

#define	MT_RXWI_RATE_LDPC (1U << 6)

#define	MT_RXWI_RATE_BW_MASK (3U << 7)

#define	MT_RXWI_RATE_SGI (1U << 9)

#define	MT_RXWI_RATE_STBC (1U << 10)

#define	MT_RXWI_RATE_PHY_MASK (7U << 13)

#define	MT_PHY_TYPE_CCK 0

#define	MT_PHY_TYPE_OFDM 1

#define	MT_PHY_TYPE_HT 2

#define	MT_PHY_TYPE_VHT 4

#define	MT_DMA_HDR_LEN 4

#define	MT_RX_RXWI_LEN 32

#define	MT_FCE_INFO_LEN 4

#define	MT_RXINFO_BA (1U << 0)

#define	MT_RXINFO_DATA (1U << 1)

#define	MT_RXINFO_NULL (1U << 2)

#define	MT_RXINFO_FRAG (1U << 3)

#define	MT_RXINFO_UNICAST (1U << 4)

#define	MT_RXINFO_MULTICAST (1U << 5)

#define	MT_RXINFO_BROADCAST (1U << 6)

#define	MT_RXINFO_MYBSS (1U << 7)

#define	MT_RXINFO_CRCERR (1U << 8)

#define	MT_RXINFO_ICVERR (1U << 9)

#define	MT_RXINFO_MICERR (1U << 10)

#define	MT_RXINFO_AMSDU (1U << 11)

#define	MT_RXINFO_HTC (1U << 12)

#define	MT_RXINFO_RSSI (1U << 13)

#define	MT_RXINFO_L2PAD (1U << 14)

#define	MT_RXINFO_AMPDU (1U << 15)

#define	MT_RXINFO_DECRYPT (1U << 16)

#define	MT_RXINFO_PN_LEN (7U << 19)

#define	MT_RXINFO_PROBE_RESP (1U << 24)

#define	MT_RXINFO_BEACON (1U << 25)

#define	MT_RXWI_CTL_WCID_MASK 0x00FF

#define	MT_RXWI_CTL_MPDU_LEN_MASK (0x3FFFU << 16)

#define	MT_RXWI_CTL_MPDU_LEN_SHIFT 16

#define	MT_RXWI_CTL_EOF (1U << 31)

#define	MT_RXWI_SIZE 32

#define	__mt76_put_le32(_p, _v)

#define	__mt76_get_le32(_p)

#define	__mt76_get_le16(_p)

#define	__mt76_put_le16(_p, _v)

#define	__mt76_round_up(_x, _n)

#define	__mt76_min(_a, _b)

#define	__mt76_rev(_priv)

#define	MT76_PROT_CFG_RATE(_v)

#define	MT76_PROT_CFG_NAV(_v)

#define	MT76_PROT_CFG_CTRL(_v)

#define	MT76_PROT_CFG_TXOP_ALLOW(_v)

#define	MT76_PROT_CFG_RTS_THRESH (1U << 23)

#define	MT76_DEFAULT_PROT_CFG_CCK

#define	MT76_DEFAULT_PROT_CFG_OFDM

#define	MT76_DEFAULT_PROT_CFG_20

#define	MT76_DEFAULT_PROT_CFG_40

#define	__mt76_cfg_read(__wifi, ...)

#define	__mt76_cfg_write(__wifi, ...)

#define	__mt76_fce_write(__wifi, ...)

#define	__mt76_dev_cmd(__wifi, ...)

#define	__mt76_dev_class_cmd(__wifi, ...)

#define	__mt76_mcu_cmd(__wifi, ...)

#define	__mt76_tx_frame(__wifi, ...)

#define	__mt76_rx_submit(__wifi, ...)

#define	MT76_RATE_UP_THRESHOLD 3

#define	MT76_RATE_TABLE_MIN 0 /* CCK 1 Mbps */

#define	MT76_RATE_TABLE_MAX (dimof(__mt76_rate_table) - 1)

#define	MT76_RATE_TABLE_INIT 0 /* CCK 1 Mbps */

#define	MT76_RATE_TABLE_INIT_5G 12 /* HT MCS0 (Linux mt76x02 starts here) */

#define	MT76_TX_QUEUE_MGMT 1

Typedefs
typedef struct mt76_rate_power_t	mt76_rate_power_t

typedef struct mt76_tx_power_info_t	mt76_tx_power_info_t

typedef struct mt76_reg_pair_t	mt76_reg_pair_t

typedef struct mt76_channel_cfg_t	mt76_channel_cfg_t

Enumerations
enum	mt76x02_cipher_type { MT76X02_CIPHER_NONE , MT76X02_CIPHER_WEP40 , MT76X02_CIPHER_WEP104 , MT76X02_CIPHER_TKIP , MT76X02_CIPHER_AES_CCMP , MT76X02_CIPHER_CKIP40 , MT76X02_CIPHER_CKIP104 , MT76X02_CIPHER_CKIP128 , MT76X02_CIPHER_WAPI }

enum	mt76_state_t { MT76_STATE_IDLE = 0 , MT76_STATE_INIT_READ_ASIC , MT76_STATE_INIT_MCU_Q_SELECT , MT76_STATE_INIT_MCU_RADIO_ON , MT76_STATE_INIT_EEPROM_LOAD , MT76_STATE_INIT_MAC_ADDR , MT76_STATE_INIT_USB_DMA , MT76_STATE_INIT_MAC_RESET , MT76_STATE_INIT_WCID_RESET , MT76_STATE_INIT_KEY_RESET , MT76_STATE_INIT_BEACON , MT76_STATE_INIT_MISC , MT76_STATE_INIT_LOAD_CR , MT76_STATE_INIT_PHY , MT76_STATE_INIT_MAC_STOP , MT76_STATE_INIT_READY }

enum	mt76_fw_state_t { MT76_FW_STATE_RESET_WLAN = 0 , MT76_FW_STATE_RESET_WLAN_RF , MT76_FW_STATE_RESET_WLAN_EN , MT76_FW_STATE_POWER_ON_MTCMOS , MT76_FW_STATE_POWER_ON_MTCMOS_POLL , MT76_FW_STATE_POWER_ON_MTCMOS_CLEAR1 , MT76_FW_STATE_POWER_ON_MTCMOS_CLEAR2 , MT76_FW_STATE_POWER_ON_MTCMOS_SET2 , MT76_FW_STATE_POWER_ON_MTCMOS_CLEAR3 , MT76_FW_STATE_POWER_ON_AD_DA , MT76_FW_STATE_POWER_ON_AD_DA_WRITE , MT76_FW_STATE_POWER_ON_WLAN_EN , MT76_FW_STATE_POWER_ON_WLAN_EN_WRITE , MT76_FW_STATE_POWER_ON_BBP_RST , MT76_FW_STATE_POWER_ON_BBP_RST_WRITE , MT76_FW_STATE_POWER_ON_RF , MT76_FW_STATE_WAIT_MAC , MT76_FW_STATE_READ_ASIC_REV , MT76_FW_STATE_CHECK_PATCH , MT76_FW_STATE_ACQUIRE_SEM , MT76_FW_STATE_ENABLE_USB_DMA , MT76_FW_STATE_VENDOR_RESET_DELAY , MT76_FW_STATE_ENABLE_USB_DMA_CFG , MT76_FW_STATE_FCE_PSE , MT76_FW_STATE_FCE_BASE , MT76_FW_STATE_FCE_MAX , MT76_FW_STATE_FCE_PDMA , MT76_FW_STATE_FCE_SKIP , MT76_FW_STATE_UPLOAD , MT76_FW_STATE_ENABLE_PATCH , MT76_FW_STATE_RESET_WMT , MT76_FW_STATE_WAIT_WMT , MT76_FW_STATE_POLL_PATCH , MT76_FW_STATE_RELEASE_SEM , MT76_FW_STATE_PARSE_FW_HEADER , MT76_FW_STATE_LOAD_IVB , MT76_FW_STATE_POLL_FW_READY , MT76_FW_STATE_SET_COMREG , MT76_FW_STATE_REENABLE_FCE , MT76_FW_STATE_DONE }

enum	mt76_fw_stage_t { MT76_FW_STAGE_PATCH = 0 , MT76_FW_STAGE_ILM , MT76_FW_STAGE_DLM }

enum	mt76_fw_send_state_t { MT76_FW_SEND_IDLE = 0 , MT76_FW_SEND_CHUNK , MT76_FW_SEND_FCE_LEN , MT76_FW_SEND_BULK , MT76_FW_SEND_IDX_READ , MT76_FW_SEND_IDX_WRITE }

Functions
vsf_err_t	__mt76_firmware_load (vsf_wifi_t *wifi, vsf_wifi_done_t done)

vsf_err_t	__mt76_init (vsf_wifi_t *wifi, vsf_wifi_done_t done)

void	__mt76_fini (vsf_wifi_t *wifi)

vsf_err_t	__mt76_eeprom_load (vsf_wifi_t *wifi, vsf_wifi_done_t done)

const uint8_t *	__mt76_eeprom_get_mac (vsf_wifi_t *wifi)

vsf_err_t	__mt76_set_channel (vsf_wifi_t *wifi, uint8_t channel, vsf_wifi_done_t done)

vsf_err_t	__mt76_set_rx_filter (vsf_wifi_t *wifi, uint32_t mask, vsf_wifi_done_t done)

vsf_err_t	__mt76_set_mac_addr (vsf_wifi_t *wifi, const uint8_t mac[6], vsf_wifi_done_t done)

vsf_err_t	__mt76_set_bssid (vsf_wifi_t *wifi, const uint8_t bssid[6], vsf_wifi_done_t done)

vsf_err_t	__mt76_set_auth_mode (vsf_wifi_t wifi, const vsf_wifi_auth_cfg_t cfg, vsf_wifi_done_t done)

vsf_err_t	__mt76_connect (vsf_wifi_t wifi, const uint8_t bssid[6], const uint8_t ssid, uint8_t ssid_len, uint8_t channel, vsf_wifi_done_t done)

vsf_err_t	__mt76_disconnect (vsf_wifi_t *wifi, vsf_wifi_done_t done)

vsf_err_t	__mt76_get_link_info (vsf_wifi_t wifi, vsf_wifi_link_info_t info)

void	__mt76_parse_rx (vsf_wifi_t wifi, uint8_t frame, uint16_t len)

vsf_err_t	__mt76_tx (vsf_wifi_t wifi, const uint8_t frame, uint16_t len)

vsf_err_t	__mt76_eeprom_load_start (vsf_wifi_t *wifi, vsf_wifi_done_t done)

void	__mt76_eeprom_parse_hw_cap (vsf_wifi_t *wifi)

Variables
const vsf_wifi_chip_drv_t	vsf_wifi_mt76_drv

Macro Definition Documentation

◆ VSF_WIFI_MT76_CFG_FORCE_SW_CCMP_TX

#define VSF_WIFI_MT76_CFG_FORCE_SW_CCMP_TX ENABLED

◆ MT76_VEND_TYPE_CFG

#define MT76_VEND_TYPE_CFG ((uint32_t)1 << 30)

◆ MT76_ASIC_VERSION

#define MT76_ASIC_VERSION 0x0000

◆ MT76_USB_U3DMA_CFG

#define MT76_USB_U3DMA_CFG (MT76_VEND_TYPE_CFG | 0x9018)

◆ MT76_USB_DMA_CFG_RX_DROP_OR_PAD

#define MT76_USB_DMA_CFG_RX_DROP_OR_PAD (1U << 18)

◆ MT76_USB_DMA_CFG_RX_BULK_AGG_EN

#define MT76_USB_DMA_CFG_RX_BULK_AGG_EN (1U << 21)

◆ MT76_USB_DMA_CFG_RX_BULK_EN

#define MT76_USB_DMA_CFG_RX_BULK_EN (1U << 22)

◆ MT76_USB_DMA_CFG_TX_BULK_EN

#define MT76_USB_DMA_CFG_TX_BULK_EN (1U << 23)

◆ MT76_WPDMA_GLO_CFG

#define MT76_WPDMA_GLO_CFG 0x0208

◆ MT76_MAC_SYS_CTRL

#define MT76_MAC_SYS_CTRL 0x1004

◆ MT76_MAC_SYS_CTRL_RESET_CSR

#define MT76_MAC_SYS_CTRL_RESET_CSR (1U << 0)

◆ MT76_MAC_SYS_CTRL_RESET_BBP

#define MT76_MAC_SYS_CTRL_RESET_BBP (1U << 1)

◆ MT76_MAC_SYS_CTRL_ENABLE_TX

#define MT76_MAC_SYS_CTRL_ENABLE_TX (1U << 2)

◆ MT76_MAC_SYS_CTRL_ENABLE_RX

#define MT76_MAC_SYS_CTRL_ENABLE_RX (1U << 3)

◆ MT76_RX_FILTR_CFG

#define MT76_RX_FILTR_CFG 0x1400

◆ MT76_FCE_DMA_ADDR

#define MT76_FCE_DMA_ADDR 0x0230

◆ MT76_FCE_DMA_LEN

#define MT76_FCE_DMA_LEN 0x0234

◆ MT76_TX_CPU_FROM_FCE_CPU_DESC_IDX

#define MT76_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09A8

◆ MT76_TX_CPU_FROM_FCE_BASE_PTR

#define MT76_TX_CPU_FROM_FCE_BASE_PTR 0x09A0

◆ MT76_TX_CPU_FROM_FCE_MAX_COUNT

#define MT76_TX_CPU_FROM_FCE_MAX_COUNT 0x09A4

◆ MT76_FCE_PSE_CTRL

#define MT76_FCE_PSE_CTRL 0x0800

◆ MT76_FCE_PDMA_GLOBAL_CONF

#define MT76_FCE_PDMA_GLOBAL_CONF 0x09C4

◆ MT76_FCE_SKIP_FS

#define MT76_FCE_SKIP_FS 0x0A6C

◆ MT76_MCU_COM_REG0

#define MT76_MCU_COM_REG0 0x0730

◆ MT76_MCU_CLOCK_CTL

#define MT76_MCU_CLOCK_CTL 0x0708

◆ MT76_MCU_RESET_CTL

#define MT76_MCU_RESET_CTL 0x070C

◆ MT76_MCU_SEMAPHORE_03

#define MT76_MCU_SEMAPHORE_03 0x07BC

◆ MT76_REV_E3

#define MT76_REV_E3 0x22

◆ MT76_CHIP_ID_7612

#define MT76_CHIP_ID_7612 0x7612

◆ MT76_CHIP_ID_7632

#define MT76_CHIP_ID_7632 0x7632

◆ MT76_CHIP_ID_7662

#define MT76_CHIP_ID_7662 0x7662

◆ MT76_CHIP_ID_7602

#define MT76_CHIP_ID_7602 0x7602

◆ MT76_PATCH_HDR_SIZE

#define MT76_PATCH_HDR_SIZE 30

◆ MT76_FW_HDR_SIZE

#define MT76_FW_HDR_SIZE 32

◆ MT76_ROM_PATCH_OFFSET

#define MT76_ROM_PATCH_OFFSET 0x00090000

◆ MT76_ILM_OFFSET

#define MT76_ILM_OFFSET 0x00080000

◆ MT76_DLM_OFFSET

#define MT76_DLM_OFFSET 0x00110000

◆ MT76_DLM_OFFSET_E3_EXTRA

#define MT76_DLM_OFFSET_E3_EXTRA 0x00000800

◆ MT76_USB_DMA_CFG_VAL

#define MT76_USB_DMA_CFG_VAL 0x00C00020

◆ MT76_WLAN_FUN_CTRL

#define MT76_WLAN_FUN_CTRL 0x0080

◆ MT76_WLAN_FUN_CTRL_WLAN_EN

#define MT76_WLAN_FUN_CTRL_WLAN_EN (1U << 0)

◆ MT76_WLAN_FUN_CTRL_WLAN_CLK_EN

#define MT76_WLAN_FUN_CTRL_WLAN_CLK_EN (1U << 1)

◆ MT76_WLAN_FUN_CTRL_WLAN_RESET_RF

#define MT76_WLAN_FUN_CTRL_WLAN_RESET_RF (1U << 2)

◆ MT76_WLAN_FUN_CTRL_FRC_WL_ANT_SEL

#define MT76_WLAN_FUN_CTRL_FRC_WL_ANT_SEL (1U << 5)

◆ MT76_WLAN_MTC_CTRL

#define MT76_WLAN_MTC_CTRL (0x40000000 | 0x148)

◆ MT76_WLAN_MTC_CTRL_MTCMOS_PWR_UP

#define MT76_WLAN_MTC_CTRL_MTCMOS_PWR_UP (1U << 0)

◆ MT76_WLAN_MTC_CTRL_PWR_ACK

#define MT76_WLAN_MTC_CTRL_PWR_ACK (1U << 12)

◆ MT76_WLAN_MTC_CTRL_PWR_ACK_S

#define MT76_WLAN_MTC_CTRL_PWR_ACK_S (1U << 13)

◆ MT76_WLAN_MTC_CTRL_STATE_UP

#define MT76_WLAN_MTC_CTRL_STATE_UP (1U << 28)

◆ MT76_MAC_CSR0

#define MT76_MAC_CSR0 0x1000

◆ MT76_WPDMA_GLO_CFG_TX_DMA_EN

#define MT76_WPDMA_GLO_CFG_TX_DMA_EN (1U << 0)

◆ MT76_WPDMA_GLO_CFG_TX_DMA_BUSY

#define MT76_WPDMA_GLO_CFG_TX_DMA_BUSY (1U << 1)

◆ MT76_WPDMA_GLO_CFG_RX_DMA_EN

#define MT76_WPDMA_GLO_CFG_RX_DMA_EN (1U << 2)

◆ MT76_WPDMA_GLO_CFG_RX_DMA_BUSY

#define MT76_WPDMA_GLO_CFG_RX_DMA_BUSY (1U << 3)

◆ MT76_US_CYC_CFG

#define MT76_US_CYC_CFG 0x02a4

◆ MT76_US_CYC_CNT

#define MT76_US_CYC_CNT 0x1e

◆ MT76_PBF_SYS_CTRL

#define MT76_PBF_SYS_CTRL 0x0400

◆ MT76_PBF_CFG

#define MT76_PBF_CFG 0x0404

◆ MT76_PBF_TX_MAX_PCNT

#define MT76_PBF_TX_MAX_PCNT 0x0408

◆ MT76_PBF_RX_MAX_PCNT

#define MT76_PBF_RX_MAX_PCNT 0x040c

◆ MT76_BCN_OFFSET_BASE

#define MT76_BCN_OFFSET_BASE 0x041c

◆ MT76_BCN_OFFSET

#define MT76_BCN_OFFSET ( _n )

Value:

(MT76_BCN_OFFSET_BASE + ((_n) << 2))

MT76_BCN_OFFSET_BASE

#define MT76_BCN_OFFSET_BASE

Definition vsf_wifi_mt76.c:108

◆ MT76_MAC_ADDR_DW0

#define MT76_MAC_ADDR_DW0 0x1008

◆ MT76_MAC_ADDR_DW1

#define MT76_MAC_ADDR_DW1 0x100c

◆ MT76_MAC_ADDR_DW1_U2ME_MASK

#define MT76_MAC_ADDR_DW1_U2ME_MASK 0x00ff0000

◆ MT76_MAC_BSSID_DW0

#define MT76_MAC_BSSID_DW0 0x1010

◆ MT76_MAC_BSSID_DW1

#define MT76_MAC_BSSID_DW1 0x1014

◆ MT76_MAC_BSSID_DW1_MBSS_MODE

#define MT76_MAC_BSSID_DW1_MBSS_MODE (3U << 16)

◆ MT76_MAC_BSSID_DW1_MBSS_LOCAL_BIT

#define MT76_MAC_BSSID_DW1_MBSS_LOCAL_BIT (1U << 21)

◆ MT76_MAC_BSSID_DW1_MBEACON_N_SHIFT

#define MT76_MAC_BSSID_DW1_MBEACON_N_SHIFT 18

◆ MT76_MAX_LEN_CFG

#define MT76_MAX_LEN_CFG 0x1018

◆ MT76_AMPDU_MAX_LEN_20M1S

#define MT76_AMPDU_MAX_LEN_20M1S 0x1030

◆ MT76_AMPDU_MAX_LEN_20M2S

#define MT76_AMPDU_MAX_LEN_20M2S 0x1034

◆ MT76_BCN_BYPASS_MASK

#define MT76_BCN_BYPASS_MASK 0x108c

◆ MT76_XIFS_TIME_CFG [1/2]

#define MT76_XIFS_TIME_CFG 0x1100

◆ MT76_BKOFF_SLOT_CFG

#define MT76_BKOFF_SLOT_CFG 0x1104

◆ MT76_BEACON_TIME_CFG

#define MT76_BEACON_TIME_CFG 0x1114

◆ MT76_BEACON_TIME_CFG_INTVAL_MASK

#define MT76_BEACON_TIME_CFG_INTVAL_MASK 0xFFFFu

◆ MT76_BEACON_TIME_CFG_TIMER_EN

#define MT76_BEACON_TIME_CFG_TIMER_EN (1U << 16)

◆ MT76_BEACON_TIME_CFG_SYNC_MODE

#define MT76_BEACON_TIME_CFG_SYNC_MODE (3U << 17)

◆ MT76_BEACON_TIME_CFG_SYNC_MODE_STA

#define MT76_BEACON_TIME_CFG_SYNC_MODE_STA (1U << 17)

◆ MT76_BEACON_TIME_CFG_TBTT_EN

#define MT76_BEACON_TIME_CFG_TBTT_EN (1U << 19)

◆ MT76_TBTT_SYNC_CFG

#define MT76_TBTT_SYNC_CFG 0x1118

◆ MT76_MAC_STATUS

#define MT76_MAC_STATUS 0x1200

◆ MT76_MAC_STATUS_TX

#define MT76_MAC_STATUS_TX (1U << 0)

◆ MT76_MAC_STATUS_RX

#define MT76_MAC_STATUS_RX (1U << 1)

◆ MT76_PWR_PIN_CFG

#define MT76_PWR_PIN_CFG 0x1204

◆ MT76_AUX_CLK_CFG

#define MT76_AUX_CLK_CFG 0x120c

◆ MT76_DACCLK_EN_DLY_CFG

#define MT76_DACCLK_EN_DLY_CFG 0x1264

◆ MT76_TX_SW_CFG0 [1/2]

#define MT76_TX_SW_CFG0 0x1330

◆ MT76_TX_SW_CFG1 [1/2]

#define MT76_TX_SW_CFG1 0x1334

◆ MT76_TX_SW_CFG2

#define MT76_TX_SW_CFG2 0x1338

◆ MT76_TXOP_CTRL_CFG

#define MT76_TXOP_CTRL_CFG 0x1340

◆ MT76_TXOP_ED_CCA_EN

#define MT76_TXOP_ED_CCA_EN (1U << 20)

◆ MT76_TX_RTS_CFG

#define MT76_TX_RTS_CFG 0x1344

◆ MT76_TX_RTS_CFG_RETRY_LIMIT

#define MT76_TX_RTS_CFG_RETRY_LIMIT 0x000000FF

◆ MT76_TX_TIMEOUT_CFG

#define MT76_TX_TIMEOUT_CFG 0x1348

◆ MT76_FCE_L2_STUFF

#define MT76_FCE_L2_STUFF 0x080c

◆ MT76_FCE_L2_STUFF_WR_MPDU_LEN_EN

#define MT76_FCE_L2_STUFF_WR_MPDU_LEN_EN (1U << 4)

◆ MT76_RF_BYPASS_0

#define MT76_RF_BYPASS_0 0x0504

◆ MT76_RF_SETTING_0

#define MT76_RF_SETTING_0 0x050c

◆ MT76_TX_RETRY_CFG

#define MT76_TX_RETRY_CFG 0x134c

◆ MT76_PIFS_TX_CFG

#define MT76_PIFS_TX_CFG 0x1388

◆ MT76_TX_LINK_CFG

#define MT76_TX_LINK_CFG 0x1350

◆ MT76_HEADER_TRANS_CTRL_REG

#define MT76_HEADER_TRANS_CTRL_REG 0x0260

◆ MT76_TSO_CTRL

#define MT76_TSO_CTRL 0x0250

◆ MT76_TX_ALC_VGA3

#define MT76_TX_ALC_VGA3 0x0778

◆ MT76_VHT_HT_FBK_CFG1

#define MT76_VHT_HT_FBK_CFG1 0x1358

◆ MT76_CCK_PROT_CFG

#define MT76_CCK_PROT_CFG 0x1364

◆ MT76_OFDM_PROT_CFG

#define MT76_OFDM_PROT_CFG 0x1368

◆ MT76_MM20_PROT_CFG

#define MT76_MM20_PROT_CFG 0x136c

◆ MT76_MM40_PROT_CFG

#define MT76_MM40_PROT_CFG 0x1370

◆ MT76_GF20_PROT_CFG

#define MT76_GF20_PROT_CFG 0x1374

◆ MT76_GF40_PROT_CFG

#define MT76_GF40_PROT_CFG 0x1378

◆ MT76_EXP_ACK_TIME

#define MT76_EXP_ACK_TIME 0x1380

◆ MT76_TX_BAND_CFG

#define MT76_TX_BAND_CFG 0x132c

◆ MT76_TX_BAND_CFG_UPPER_40M

#define MT76_TX_BAND_CFG_UPPER_40M (1U << 0)

◆ MT76_TX_BAND_CFG_5G

#define MT76_TX_BAND_CFG_5G (1U << 1)

◆ MT76_TX_BAND_CFG_2G

#define MT76_TX_BAND_CFG_2G (1U << 2)

◆ MT76_EXT_CCA_CFG

#define MT76_EXT_CCA_CFG 0x141c

◆ MT76_EXT_CCA_CFG_CCA0_M

#define MT76_EXT_CCA_CFG_CCA0_M 0x00000003

◆ MT76_EXT_CCA_CFG_CCA1_M

#define MT76_EXT_CCA_CFG_CCA1_M 0x0000000c

◆ MT76_EXT_CCA_CFG_CCA2_M

#define MT76_EXT_CCA_CFG_CCA2_M 0x00000030

◆ MT76_EXT_CCA_CFG_CCA3_M

#define MT76_EXT_CCA_CFG_CCA3_M 0x000000c0

◆ MT76_EXT_CCA_CFG_CCA_MASK_M

#define MT76_EXT_CCA_CFG_CCA_MASK_M 0x00000f00

◆ MT76_BBP_CORE_BASE [1/2]

#define MT76_BBP_CORE_BASE 0x2000

◆ MT76_BBP_AGC_BASE [1/2]

#define MT76_BBP_AGC_BASE 0x2300

◆ MT76_BBP_TXO_BASE [1/2]

#define MT76_BBP_TXO_BASE 0x2600

◆ MT76_BBP_TXBE_BASE [1/2]

#define MT76_BBP_TXBE_BASE 0x2700

◆ MT76_BBP_RXO_BASE [1/2]

#define MT76_BBP_RXO_BASE 0x2900

◆ MT76_BBP [1/2]

#define MT76_BBP	(		_type,
			_n )

Value:

(MT76_BBP_##_type##_BASE + ((_n) << 2))

◆ MT76_BBP_CORE_R1_BW_M

#define MT76_BBP_CORE_R1_BW_M (3U << 3) /* bits 4:3 */

◆ MT76_BBP_CORE_R1_BW_20

#define MT76_BBP_CORE_R1_BW_20 (0U << 3)

◆ MT76_BBP_CORE_R1_BW_40

#define MT76_BBP_CORE_R1_BW_40 (2U << 3)

◆ MT76_BBP_CORE_R1_BW_80

#define MT76_BBP_CORE_R1_BW_80 (3U << 3)

◆ MT76_BBP_AGC_R0_BW_M

#define MT76_BBP_AGC_R0_BW_M (7U << 12) /* bits 14:12 */

◆ MT76_BBP_AGC_R0_BW_20

#define MT76_BBP_AGC_R0_BW_20 (1U << 12)

◆ MT76_BBP_AGC_R0_BW_40

#define MT76_BBP_AGC_R0_BW_40 (3U << 12)

◆ MT76_BBP_AGC_R0_BW_80

#define MT76_BBP_AGC_R0_BW_80 (7U << 12)

◆ MT76_BBP_AGC_R0_CTRL_CHAN_M

#define MT76_BBP_AGC_R0_CTRL_CHAN_M (3U << 8) /* bits 9:8 */

◆ MT76_BBP_TXBE_R0_CTRL_CHAN_M

#define MT76_BBP_TXBE_R0_CTRL_CHAN_M (3U << 0) /* bits 1:0 */

◆ MT_TX_STAT_FIFO

#define MT_TX_STAT_FIFO 0x1718

◆ MT_TX_STAT_FIFO_VALID

#define MT_TX_STAT_FIFO_VALID (1U << 0)

◆ MT_TX_STAT_FIFO_SUCCESS

#define MT_TX_STAT_FIFO_SUCCESS (1U << 5)

◆ MT_TX_STAT_FIFO_AGGR

#define MT_TX_STAT_FIFO_AGGR (1U << 6)

◆ MT_TX_STAT_FIFO_ACKREQ

#define MT_TX_STAT_FIFO_ACKREQ (1U << 7)

◆ MT_TX_STAT_FIFO_WCID_M

#define MT_TX_STAT_FIFO_WCID_M 0x0000FF00

◆ MT_TX_STAT_FIFO_WCID_S

#define MT_TX_STAT_FIFO_WCID_S 8

◆ MT_TX_STAT_FIFO_RATE_M

#define MT_TX_STAT_FIFO_RATE_M 0xFFFF0000

◆ MT_TX_STAT_FIFO_RATE_S

#define MT_TX_STAT_FIFO_RATE_S 16

◆ MT_TX_STAT_FIFO_EXT

#define MT_TX_STAT_FIFO_EXT 0x1798

◆ MT_TX_STAT_FIFO_EXT_RETRY_M

#define MT_TX_STAT_FIFO_EXT_RETRY_M 0x000000FF

◆ MT_TX_STAT_FIFO_EXT_RETRY_S

#define MT_TX_STAT_FIFO_EXT_RETRY_S 0

◆ MT_TX_STAT_FIFO_EXT_PKTID_M

#define MT_TX_STAT_FIFO_EXT_PKTID_M 0x0000FF00

◆ MT_TX_STAT_FIFO_EXT_PKTID_S

#define MT_TX_STAT_FIFO_EXT_PKTID_S 8

◆ MT76_PACKET_ID_HAS_RATE

#define MT76_PACKET_ID_HAS_RATE 0x80

◆ MT76_PKTID_RATE_M

#define MT76_PKTID_RATE_M 0x1F

◆ MT76_HT_FBK_TO_LEGACY

#define MT76_HT_FBK_TO_LEGACY 0x1384

◆ MT76_TX_PROT_CFG6

#define MT76_TX_PROT_CFG6 0x13e0

◆ MT76_TX_PROT_CFG7

#define MT76_TX_PROT_CFG7 0x13e4

◆ MT76_TX_PROT_CFG8

#define MT76_TX_PROT_CFG8 0x13e8

◆ MT76_TX_PWR_CFG_0

#define MT76_TX_PWR_CFG_0 0x1314

◆ MT76_TX_PWR_CFG_1

#define MT76_TX_PWR_CFG_1 0x1318

◆ MT76_TX_PWR_CFG_2

#define MT76_TX_PWR_CFG_2 0x131c

◆ MT76_TX_PWR_CFG_3

#define MT76_TX_PWR_CFG_3 0x1320

◆ MT76_TX_PWR_CFG_4

#define MT76_TX_PWR_CFG_4 0x1324

◆ MT76_TX_PWR_CFG_7

#define MT76_TX_PWR_CFG_7 0x13d4

◆ MT76_TX_PWR_CFG_8

#define MT76_TX_PWR_CFG_8 0x13d8

◆ MT76_TX_PWR_CFG_9

#define MT76_TX_PWR_CFG_9 0x13dc

◆ MT76_BB_PA_MODE_CFG0

#define MT76_BB_PA_MODE_CFG0 0x1214

◆ MT76_BB_PA_MODE_CFG1

#define MT76_BB_PA_MODE_CFG1 0x1218

◆ MT76_RF_PA_MODE_CFG0

#define MT76_RF_PA_MODE_CFG0 0x121c

◆ MT76_RF_PA_MODE_CFG1

#define MT76_RF_PA_MODE_CFG1 0x1220

◆ MT76_RF_PA_MODE_ADJ0

#define MT76_RF_PA_MODE_ADJ0 0x1228

◆ MT76_RF_PA_MODE_ADJ1

#define MT76_RF_PA_MODE_ADJ1 0x122c

◆ MT76_TX_SW_CFG0 [2/2]

#define MT76_TX_SW_CFG0 0x1330

◆ MT76_TX_SW_CFG1 [2/2]

#define MT76_TX_SW_CFG1 0x1334

◆ MT76_TX0_RF_GAIN_CORR

#define MT76_TX0_RF_GAIN_CORR 0x13a0

◆ MT76_TX1_RF_GAIN_CORR

#define MT76_TX1_RF_GAIN_CORR 0x13a4

◆ MT76_TX_ALC_CFG_0

#define MT76_TX_ALC_CFG_0 0x13b0

◆ MT76_TX_ALC_CFG_0_CH_INIT_0_M

#define MT76_TX_ALC_CFG_0_CH_INIT_0_M 0x0000003f

◆ MT76_TX_ALC_CFG_0_CH_INIT_0_S

#define MT76_TX_ALC_CFG_0_CH_INIT_0_S 0

◆ MT76_TX_ALC_CFG_0_CH_INIT_1_M

#define MT76_TX_ALC_CFG_0_CH_INIT_1_M 0x00003f00

◆ MT76_TX_ALC_CFG_0_CH_INIT_1_S

#define MT76_TX_ALC_CFG_0_CH_INIT_1_S 8

◆ MT76_TX_ALC_CFG_0_LIMIT_0_M

#define MT76_TX_ALC_CFG_0_LIMIT_0_M 0x003f0000

◆ MT76_TX_ALC_CFG_0_LIMIT_0_S

#define MT76_TX_ALC_CFG_0_LIMIT_0_S 16

◆ MT76_TX_ALC_CFG_0_LIMIT_1_M

#define MT76_TX_ALC_CFG_0_LIMIT_1_M 0x3f000000

◆ MT76_TX_ALC_CFG_0_LIMIT_1_S

#define MT76_TX_ALC_CFG_0_LIMIT_1_S 24

◆ MT76_TX_ALC_CFG_2

#define MT76_TX_ALC_CFG_2 0x13a8

◆ MT76_TX_ALC_CFG_3

#define MT76_TX_ALC_CFG_3 0x13ac

◆ MT76_XIFS_TIME_CFG [2/2]

#define MT76_XIFS_TIME_CFG 0x1100

◆ MT76_XIFS_TIME_CFG_OFDM_SIFS_M

#define MT76_XIFS_TIME_CFG_OFDM_SIFS_M 0x0000ff00

◆ MT76_XIFS_TIME_CFG_OFDM_SIFS_S

#define MT76_XIFS_TIME_CFG_OFDM_SIFS_S 8

◆ MT76_LEGACY_BASIC_RATE

#define MT76_LEGACY_BASIC_RATE 0x1408

◆ MT76_HT_BASIC_RATE

#define MT76_HT_BASIC_RATE 0x140c

◆ MT76_HT_CTRL_CFG

#define MT76_HT_CTRL_CFG 0x1410

◆ MT76_TX_SW_CFG3

#define MT76_TX_SW_CFG3 0x1478

◆ MT76_PN_PAD_MODE

#define MT76_PN_PAD_MODE 0x150c

◆ MT76_TXOP_HLDR_ET

#define MT76_TXOP_HLDR_ET 0x1608

◆ MT76_TXOP_HLDR_TX40M_BLK_EN

#define MT76_TXOP_HLDR_TX40M_BLK_EN (1U << 1)

◆ MT76_PROT_AUTO_TX_CFG

#define MT76_PROT_AUTO_TX_CFG 0x1648

◆ MT76_EFUSE_CTRL

#define MT76_EFUSE_CTRL 0x0024

◆ MT76_PAUSE_ENABLE_CONTROL1

#define MT76_PAUSE_ENABLE_CONTROL1 0x0a38

◆ MT76_FCE_WLAN_FLOW_CONTROL1

#define MT76_FCE_WLAN_FLOW_CONTROL1 0x0824

◆ MT76_WPDMA_DELAY_INT_CFG

#define MT76_WPDMA_DELAY_INT_CFG 0x0210

◆ MT76_WCID_ATTR_BASE

#define MT76_WCID_ATTR_BASE 0xa800

◆ MT76_WCID_ATTR

#define MT76_WCID_ATTR ( _n )

Value:

(MT76_WCID_ATTR_BASE + (_n) * 4)

MT76_WCID_ATTR_BASE

#define MT76_WCID_ATTR_BASE

Definition vsf_wifi_mt76.c:272

◆ MT76_WCID_ATTR_PAIRWISE

#define MT76_WCID_ATTR_PAIRWISE (1U << 0)

◆ MT76_WCID_ATTR_PKEY_MODE

#define MT76_WCID_ATTR_PKEY_MODE (0x7U << 1)

◆ MT76_WCID_ATTR_PKEY_MODE_SHIFT

#define MT76_WCID_ATTR_PKEY_MODE_SHIFT 1

◆ MT76_WCID_ATTR_BSS_IDX

#define MT76_WCID_ATTR_BSS_IDX (0U << 4)

◆ MT76_WCID_ATTR_BSS_IDX_EXT

#define MT76_WCID_ATTR_BSS_IDX_EXT (1U << 11)

◆ MT76_WCID_ADDR_BASE

#define MT76_WCID_ADDR_BASE 0x1800

◆ MT76_WCID_ADDR

#define MT76_WCID_ADDR ( _n )

Value:

(MT76_WCID_ADDR_BASE + (_n) * 8)

MT76_WCID_ADDR_BASE

#define MT76_WCID_ADDR_BASE

Definition vsf_wifi_mt76.c:279

◆ MT76_WCID_DROP_BASE

#define MT76_WCID_DROP_BASE 0x106c

◆ MT76_WCID_DROP

#define MT76_WCID_DROP ( _n )

Value:

(MT76_WCID_DROP_BASE + ((_n) >> 5) * 4)

MT76_WCID_DROP_BASE

#define MT76_WCID_DROP_BASE

Definition vsf_wifi_mt76.c:282

◆ MT76_WCID_DROP_MASK

#define MT76_WCID_DROP_MASK ( _n )

Value:

(1U << ((_n) % 32))

◆ MT76_WCID_TX_INFO_BASE

#define MT76_WCID_TX_INFO_BASE 0x1c00

◆ MT76_WCID_TX_INFO

#define MT76_WCID_TX_INFO ( _n )

Value:

(MT76_WCID_TX_INFO_BASE + ((_n) * 8))

MT76_WCID_TX_INFO_BASE

#define MT76_WCID_TX_INFO_BASE

Definition vsf_wifi_mt76.c:286

◆ MT76_WCID_KEY_BASE

#define MT76_WCID_KEY_BASE 0x8000

◆ MT76_WCID_KEY

#define MT76_WCID_KEY ( _n )

Value:

(MT76_WCID_KEY_BASE + (_n) * 32)

MT76_WCID_KEY_BASE

#define MT76_WCID_KEY_BASE

Definition vsf_wifi_mt76.c:289

◆ MT76_WCID_IV_BASE

#define MT76_WCID_IV_BASE 0xa000

◆ MT76_WCID_IV

#define MT76_WCID_IV ( _n )

Value:

(MT76_WCID_IV_BASE + (_n) * 8)

MT76_WCID_IV_BASE

#define MT76_WCID_IV_BASE

Definition vsf_wifi_mt76.c:291

◆ MT_VIF_WCID

#define MT_VIF_WCID ( _n )

Value:

(254 - ((_n) & 7))

◆ MT76_SKEY_MODE_MASK

#define MT76_SKEY_MODE_MASK 0xFU

◆ MT76_SKEY_MODE_SHIFT

#define MT76_SKEY_MODE_SHIFT	(		_bss,
			_idx )

Value:

(4 * ((_idx) + 4 * ((_bss) & 1)))

◆ MT_WCID_TX_INFO_RATE

#define MT_WCID_TX_INFO_RATE 0x0000FFFFU

◆ MT_WCID_TX_INFO_RATE_S

#define MT_WCID_TX_INFO_RATE_S 0

◆ MT_WCID_TX_INFO_NSS_SHIFT

#define MT_WCID_TX_INFO_NSS_SHIFT 16

◆ MT_WCID_TX_INFO_NSS_MASK

#define MT_WCID_TX_INFO_NSS_MASK 0x00030000U

◆ MT_WCID_TX_INFO_TXPWR_ADJ_SHIFT

#define MT_WCID_TX_INFO_TXPWR_ADJ_SHIFT 18

◆ MT_WCID_TX_INFO_TXPWR_ADJ_MASK

#define MT_WCID_TX_INFO_TXPWR_ADJ_MASK 0x03FC0000U

◆ MT_WCID_TX_INFO_SET

#define MT_WCID_TX_INFO_SET 0x80000000U

◆ MT76_SKEY_BASE_0

#define MT76_SKEY_BASE_0 0xac00

◆ MT76_SKEY_BASE_1

#define MT76_SKEY_BASE_1 0xb400

◆ MT76_SKEY

#define MT76_SKEY	(		_bss,
			_idx )

Value:

(((_bss) & 8) ? (MT76_SKEY_BASE_1 + (4 * ((_bss) & 7) + (_idx)) * 32) \

: (MT76_SKEY_BASE_0 + (4 * (_bss) + (_idx)) * 32))

MT76_SKEY_BASE_1

#define MT76_SKEY_BASE_1

Definition vsf_wifi_mt76.c:319

MT76_SKEY_BASE_0

#define MT76_SKEY_BASE_0

Definition vsf_wifi_mt76.c:318

◆ MT76_SKEY_MODE_BASE_0

#define MT76_SKEY_MODE_BASE_0 0xb000

◆ MT76_SKEY_MODE_BASE_1

#define MT76_SKEY_MODE_BASE_1 0xb3f0

◆ MT76_SKEY_MODE

#define MT76_SKEY_MODE ( _bss )

Value:

(((_bss) & 8) ? (MT76_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2)) \

: (MT76_SKEY_MODE_BASE_0 + (((_bss) / 2) << 2)))

MT76_SKEY_MODE_BASE_1

#define MT76_SKEY_MODE_BASE_1

Definition vsf_wifi_mt76.c:324

MT76_SKEY_MODE_BASE_0

#define MT76_SKEY_MODE_BASE_0

Definition vsf_wifi_mt76.c:323

◆ MT76_BBP_CORE_BASE [2/2]

#define MT76_BBP_CORE_BASE 0x2000

◆ MT76_BBP_IBI_BASE

#define MT76_BBP_IBI_BASE 0x2100

◆ MT76_BBP_AGC_BASE [2/2]

#define MT76_BBP_AGC_BASE 0x2300

◆ MT76_BBP_TXO_BASE [2/2]

#define MT76_BBP_TXO_BASE 0x2600

◆ MT76_BBP_TXBE_BASE [2/2]

#define MT76_BBP_TXBE_BASE 0x2700

◆ MT76_BBP_RXO_BASE [2/2]

#define MT76_BBP_RXO_BASE 0x2900

◆ MT76_BBP [2/2]

#define MT76_BBP	(		_type,
			_n )

Value:

(MT76_BBP_##_type##_BASE + ((_n) << 2))

◆ MT76_BBP_TXO_4_TX_CMM_BW

#define MT76_BBP_TXO_4_TX_CMM_BW (1U << 25)

◆ MT76_BBP_RXO_13_RX_CMM_PD_EN

#define MT76_BBP_RXO_13_RX_CMM_PD_EN (1U << 8)

◆ MT76_BBP_RXO_13_LDPC_RX_EN

#define MT76_BBP_RXO_13_LDPC_RX_EN (1U << 10)

◆ MT76_XO_CTRL5

#define MT76_XO_CTRL5 0x0114

◆ MT76_XO_CTRL5_C2_VAL_MASK

#define MT76_XO_CTRL5_C2_VAL_MASK 0x7f00

◆ MT76_XO_CTRL5_C2_VAL_SHIFT

#define MT76_XO_CTRL5_C2_VAL_SHIFT 8

◆ MT76_XO_CTRL6

#define MT76_XO_CTRL6 0x0118

◆ MT76_XO_CTRL6_C2_CTRL_MASK

#define MT76_XO_CTRL6_C2_CTRL_MASK 0x7f00

◆ MT76_XO_CTRL6_C2_CTRL_SHIFT

#define MT76_XO_CTRL6_C2_CTRL_SHIFT 8

◆ MT76_XO_CTRL7

#define MT76_XO_CTRL7 0x011c

◆ MT76_COEXCFG0

#define MT76_COEXCFG0 0x0040

◆ MT76_COEXCFG0_COEX_EN

#define MT76_COEXCFG0_COEX_EN (1U << 0)

◆ MT76_TX_ALC_CFG_4

#define MT76_TX_ALC_CFG_4 0x077c

◆ MT76_TX_ALC_CFG_4_MPDU_2ND_TC

#define MT76_TX_ALC_CFG_4_MPDU_2ND_TC (1U << 31)

◆ MT76_AUTO_RSP_CFG

#define MT76_AUTO_RSP_CFG 0x110c

◆ MT76_WMM_AIFSN

#define MT76_WMM_AIFSN 0x0214

◆ MT76_WMM_CWMIN

#define MT76_WMM_CWMIN 0x0218

◆ MT76_WMM_CWMAX

#define MT76_WMM_CWMAX 0x021c

◆ MT76_WMM_TXOP_BASE

#define MT76_WMM_TXOP_BASE 0x0220

◆ MT76_WMM_TXOP

#define MT76_WMM_TXOP ( _n )

Value:

(MT76_WMM_TXOP_BASE + (((_n) >> 1) << 2))

MT76_WMM_TXOP_BASE

#define MT76_WMM_TXOP_BASE

Definition vsf_wifi_mt76.c:357

◆ MT76_EDCA_CFG_BASE

#define MT76_EDCA_CFG_BASE 0x1300

◆ MT76_EDCA_CFG_AC

#define MT76_EDCA_CFG_AC ( _n )

Value:

(MT76_EDCA_CFG_BASE + ((_n) << 2))

MT76_EDCA_CFG_BASE

#define MT76_EDCA_CFG_BASE

Definition vsf_wifi_mt76.c:359

◆ MT76_TXOP_THRES_CFG

#define MT76_TXOP_THRES_CFG 0x13ec

◆ MT76_MCU_MSG_CMD_LOAD_CR

#define MT76_MCU_MSG_CMD_LOAD_CR 2

◆ MT76_RF_BBP_CR

#define MT76_RF_BBP_CR 2

◆ MT76_MCU_MSG_TYPE_CMD

#define MT76_MCU_MSG_TYPE_CMD ((uint32_t)1 << 30)

◆ MT76_MCU_MSG_CMD_TYPE_SHIFT

#define MT76_MCU_MSG_CMD_TYPE_SHIFT 20

◆ MT76_MCU_MSG_CMD_SEQ_SHIFT

#define MT76_MCU_MSG_CMD_SEQ_SHIFT 16

◆ MT76_MCU_MSG_PORT_SHIFT

#define MT76_MCU_MSG_PORT_SHIFT 27

◆ MT76_MCU_MSG_LEN_MASK

#define MT76_MCU_MSG_LEN_MASK 0xFFFF

◆ MT76_TXD_INFO_LEN_MASK

#define MT76_TXD_INFO_LEN_MASK 0xFFFF

◆ MT76_TXD_INFO_DPORT_SHIFT

#define MT76_TXD_INFO_DPORT_SHIFT 27

◆ MT76_TXD_INFO_TYPE_CMD

#define MT76_TXD_INFO_TYPE_CMD ((uint32_t)1 << 30)

◆ MT76_CPU_TX_PORT

#define MT76_CPU_TX_PORT 2

◆ MT76_WLAN_PORT

#define MT76_WLAN_PORT 0

◆ MT76_VEND_DEV_MODE

#define MT76_VEND_DEV_MODE 0x01

◆ MT76_FW_PATCH_CHUNK_PAYLOAD

#define MT76_FW_PATCH_CHUNK_PAYLOAD (2048 - 8)

◆ MT76_FW_FW_CHUNK_PAYLOAD

#define MT76_FW_FW_CHUNK_PAYLOAD (MT76_TX_URB_SIZE - 8)

◆ MT76_CMD_FUN_SET_OP

#define MT76_CMD_FUN_SET_OP 1

◆ MT76_CMD_POWER_SAVING_OP

#define MT76_CMD_POWER_SAVING_OP 20

◆ MT76_FUN_Q_SELECT

#define MT76_FUN_Q_SELECT 1

◆ MT76_PWR_RADIO_ON

#define MT76_PWR_RADIO_ON 0x31

◆ MT76_PWR_RADIO_OFF

#define MT76_PWR_RADIO_OFF 0x30

◆ MT_EE_READ

#define MT_EE_READ 0

◆ MT76_EE_MAC_ADDR

#define MT76_EE_MAC_ADDR 0x004

◆ MT76_EE_NIC_CONF_0

#define MT76_EE_NIC_CONF_0 0x034

◆ MT76_EE_NIC_CONF_1

#define MT76_EE_NIC_CONF_1 0x036

◆ MT76_EE_XTAL_TRIM_1

#define MT76_EE_XTAL_TRIM_1 0x03a

◆ MT76_EE_XTAL_TRIM_2

#define MT76_EE_XTAL_TRIM_2 0x09e

◆ MT76_EE_NIC_CONF_2

#define MT76_EE_NIC_CONF_2 0x042

◆ MT76_EE_LNA_GAIN

#define MT76_EE_LNA_GAIN 0x044

◆ MT76_EE_RSSI_OFFSET_2G_0

#define MT76_EE_RSSI_OFFSET_2G_0 0x046

◆ MT76_EE_RSSI_OFFSET_2G_1

#define MT76_EE_RSSI_OFFSET_2G_1 0x048

◆ MT76_EE_LNA_GAIN_5GHZ_1

#define MT76_EE_LNA_GAIN_5GHZ_1 0x049

◆ MT76_EE_RSSI_OFFSET_5G_0

#define MT76_EE_RSSI_OFFSET_5G_0 0x04a

◆ MT76_EE_RSSI_OFFSET_5G_1

#define MT76_EE_RSSI_OFFSET_5G_1 0x04c

◆ MT76_EE_LNA_GAIN_5GHZ_2

#define MT76_EE_LNA_GAIN_5GHZ_2 0x04d

◆ MT76_EE_TX_POWER_DELTA_BW40

#define MT76_EE_TX_POWER_DELTA_BW40 0x050

◆ MT76_EE_TX_POWER_DELTA_BW80

#define MT76_EE_TX_POWER_DELTA_BW80 0x052

◆ MT76_EE_TX_POWER_EXT_PA_5G

#define MT76_EE_TX_POWER_EXT_PA_5G 0x054

◆ MT76_EE_TX_POWER_0_START_2G

#define MT76_EE_TX_POWER_0_START_2G 0x056

◆ MT76_EE_TX_POWER_1_START_2G

#define MT76_EE_TX_POWER_1_START_2G 0x05c

◆ MT76_EE_TX_POWER_0_START_5G

#define MT76_EE_TX_POWER_0_START_5G 0x062

◆ MT76_EE_TX_POWER_1_START_5G

#define MT76_EE_TX_POWER_1_START_5G 0x080

◆ MT76_EE_TX_POWER_CCK

#define MT76_EE_TX_POWER_CCK 0x0a0

◆ MT76_EE_TX_POWER_OFDM_2G_6M

#define MT76_EE_TX_POWER_OFDM_2G_6M 0x0a2

◆ MT76_EE_TX_POWER_OFDM_2G_24M

#define MT76_EE_TX_POWER_OFDM_2G_24M 0x0a4

◆ MT76_EE_TX_POWER_OFDM_5G_6M

#define MT76_EE_TX_POWER_OFDM_5G_6M 0x0b2

◆ MT76_EE_TX_POWER_OFDM_5G_24M

#define MT76_EE_TX_POWER_OFDM_5G_24M 0x0b4

◆ MT76_EE_TX_POWER_HT_MCS0

#define MT76_EE_TX_POWER_HT_MCS0 0x0a6

◆ MT76_EE_TX_POWER_HT_MCS4

#define MT76_EE_TX_POWER_HT_MCS4 0x0a8

◆ MT76_EE_TX_POWER_HT_MCS8

#define MT76_EE_TX_POWER_HT_MCS8 0x0aa

◆ MT76_EE_TX_POWER_HT_MCS12

#define MT76_EE_TX_POWER_HT_MCS12 0x0ac

◆ MT76_EE_TX_POWER_VHT_MCS8

#define MT76_EE_TX_POWER_VHT_MCS8 0x0be

◆ MT76_EE_2G_TARGET_POWER

#define MT76_EE_2G_TARGET_POWER 0x0d0

◆ MT76_EE_5G_TARGET_POWER

#define MT76_EE_5G_TARGET_POWER 0x0d2

◆ MT76_EE_RF_2G_TSSI_OFF_TXPOWER

#define MT76_EE_RF_2G_TSSI_OFF_TXPOWER 0x0f6

◆ MT76_EE_RF_2G_RX_HIGH_GAIN

#define MT76_EE_RF_2G_RX_HIGH_GAIN 0x0f8

◆ MT76_EE_RF_5G_GRP0_1_RX_HIGH_GAIN

#define MT76_EE_RF_5G_GRP0_1_RX_HIGH_GAIN 0x0fa

◆ MT76_EE_RF_5G_GRP2_3_RX_HIGH_GAIN

#define MT76_EE_RF_5G_GRP2_3_RX_HIGH_GAIN 0x0fc

◆ MT76_EE_RF_5G_GRP4_5_RX_HIGH_GAIN

#define MT76_EE_RF_5G_GRP4_5_RX_HIGH_GAIN 0x0fe

◆ MT76_TX_POWER_GROUP_SIZE_5G

#define MT76_TX_POWER_GROUP_SIZE_5G 5

◆ MT76_TX_POWER_GROUPS_5G

#define MT76_TX_POWER_GROUPS_5G 6

◆ MT76_EE_NIC_CONF_0_PA_INT_2G

#define MT76_EE_NIC_CONF_0_PA_INT_2G (1U << 8)

◆ MT76_EE_NIC_CONF_0_PA_INT_5G

#define MT76_EE_NIC_CONF_0_PA_INT_5G (1U << 9)

◆ MT76_EE_NIC_CONF_1_TEMP_TX_ALC

#define MT76_EE_NIC_CONF_1_TEMP_TX_ALC (1U << 1)

◆ MT76_EE_NIC_CONF_1_TX_ALC_EN

#define MT76_EE_NIC_CONF_1_TX_ALC_EN (1U << 13)

◆ MT76_EE_NIC_CONF_1_LNA_EXT_2G

#define MT76_EE_NIC_CONF_1_LNA_EXT_2G (1U << 2)

◆ MT76_EE_NIC_CONF_1_LNA_EXT_5G

#define MT76_EE_NIC_CONF_1_LNA_EXT_5G (1U << 3)

◆ MT76_EE_TX_POWER_EXT_PA_5G_EN

#define MT76_EE_TX_POWER_EXT_PA_5G_EN (1U << 15)

◆ MT76_MAX_TX_POWER_OPS

#define MT76_MAX_TX_POWER_OPS 32

◆ MT76_CMD_INIT_GAIN_OP

#define MT76_CMD_INIT_GAIN_OP 3

◆ MT76_CMD_SWITCH_CHANNEL_OP

#define MT76_CMD_SWITCH_CHANNEL_OP 30

◆ MT76_CMD_CALIBRATION_OP

#define MT76_CMD_CALIBRATION_OP 31

◆ MT76_MCU_CAL_R

#define MT76_MCU_CAL_R 1

◆ MT76_MCU_CAL_RXDCOC

#define MT76_MCU_CAL_RXDCOC 2

◆ MT76_MCU_CAL_RC

#define MT76_MCU_CAL_RC 3

◆ MT_RX_FILTR_CFG

#define MT_RX_FILTR_CFG 0x1400

◆ MT_RX_FILTR_CFG_CRC_ERR

#define MT_RX_FILTR_CFG_CRC_ERR (1U << 0)

◆ MT_RX_FILTR_CFG_PHY_ERR

#define MT_RX_FILTR_CFG_PHY_ERR (1U << 1)

◆ MT_RX_FILTR_CFG_PROMISC

#define MT_RX_FILTR_CFG_PROMISC (1U << 2)

◆ MT_RX_FILTR_CFG_OTHER_BSS

#define MT_RX_FILTR_CFG_OTHER_BSS (1U << 3)

◆ MT_RX_FILTR_CFG_VER_ERR

#define MT_RX_FILTR_CFG_VER_ERR (1U << 4)

◆ MT_RX_FILTR_CFG_MCAST

#define MT_RX_FILTR_CFG_MCAST (1U << 5)

◆ MT_RX_FILTR_CFG_BCAST

#define MT_RX_FILTR_CFG_BCAST (1U << 6)

◆ MT_RX_FILTR_CFG_DUP

#define MT_RX_FILTR_CFG_DUP (1U << 7)

◆ MT_RX_FILTR_CFG_CFACK

#define MT_RX_FILTR_CFG_CFACK (1U << 8)

◆ MT_RX_FILTR_CFG_CFEND

#define MT_RX_FILTR_CFG_CFEND (1U << 9)

◆ MT_RX_FILTR_CFG_ACK

#define MT_RX_FILTR_CFG_ACK (1U << 10)

◆ MT_RX_FILTR_CFG_CTS

#define MT_RX_FILTR_CFG_CTS (1U << 11)

◆ MT_RX_FILTR_CFG_RTS

#define MT_RX_FILTR_CFG_RTS (1U << 12)

◆ MT_RX_FILTR_CFG_PSPOLL

#define MT_RX_FILTR_CFG_PSPOLL (1U << 13)

◆ MT_RX_FILTR_CFG_BA

#define MT_RX_FILTR_CFG_BA (1U << 14)

◆ MT_RX_FILTR_CFG_BAR

#define MT_RX_FILTR_CFG_BAR (1U << 15)

◆ MT_RX_FILTR_CFG_CTRL_RSV

#define MT_RX_FILTR_CFG_CTRL_RSV (1U << 16)

◆ MT_RX_FILTR_CFG_DEFAULT

#define MT_RX_FILTR_CFG_DEFAULT 0x00015f97

◆ MT_TXD_INFO_LEN_MASK

#define MT_TXD_INFO_LEN_MASK 0x0000FFFF

◆ MT_TXD_INFO_NEXT_VLD

#define MT_TXD_INFO_NEXT_VLD (1U << 16)

◆ MT_TXD_INFO_TX_BURST

#define MT_TXD_INFO_TX_BURST (1U << 17)

◆ MT_TXD_INFO_80211

#define MT_TXD_INFO_80211 (1U << 19)

◆ MT_TXD_INFO_TSO

#define MT_TXD_INFO_TSO (1U << 20)

◆ MT_TXD_INFO_CSO

#define MT_TXD_INFO_CSO (1U << 21)

◆ MT_TXD_INFO_WIV

#define MT_TXD_INFO_WIV (1U << 24)

◆ MT_TXD_INFO_QSEL_MASK

#define MT_TXD_INFO_QSEL_MASK (3U << 25)

◆ MT_TXD_INFO_QSEL_SHIFT

#define MT_TXD_INFO_QSEL_SHIFT 25

◆ MT_TXD_INFO_DPORT_MASK

#define MT_TXD_INFO_DPORT_MASK (7U << 27)

◆ MT_TXD_INFO_DPORT_SHIFT

#define MT_TXD_INFO_DPORT_SHIFT 27

◆ MT_TXD_INFO_TYPE_MASK

#define MT_TXD_INFO_TYPE_MASK (3U << 30)

◆ MT_QSEL_MGMT

#define MT_QSEL_MGMT 0

◆ MT_QSEL_EDCA

#define MT_QSEL_EDCA 2

◆ MT_WLAN_PORT

#define MT_WLAN_PORT 0

◆ MT_TXWI_FLAGS_FRAG

#define MT_TXWI_FLAGS_FRAG (1U << 0)

◆ MT_TXWI_FLAGS_MMPS

#define MT_TXWI_FLAGS_MMPS (1U << 1)

◆ MT_TXWI_FLAGS_CFACK

#define MT_TXWI_FLAGS_CFACK (1U << 2)

◆ MT_TXWI_FLAGS_TS

#define MT_TXWI_FLAGS_TS (1U << 3)

◆ MT_TXWI_FLAGS_AMPDU

#define MT_TXWI_FLAGS_AMPDU (1U << 4)

◆ MT_TXWI_FLAGS_MPDU_DENSITY_MASK

#define MT_TXWI_FLAGS_MPDU_DENSITY_MASK (7U << 5)

◆ MT_TXWI_FLAGS_TXOP_MASK

#define MT_TXWI_FLAGS_TXOP_MASK (3U << 8)

◆ MT_TXWI_FLAGS_NDPS

#define MT_TXWI_FLAGS_NDPS (1U << 10)

◆ MT_TXWI_FLAGS_RTSBWSIG

#define MT_TXWI_FLAGS_RTSBWSIG (1U << 11)

◆ MT_TXWI_FLAGS_NDP_BW_MASK

#define MT_TXWI_FLAGS_NDP_BW_MASK (3U << 12)

◆ MT_TXWI_FLAGS_SOUND

#define MT_TXWI_FLAGS_SOUND (1U << 14)

◆ MT_TXWI_FLAGS_TX_RATE_LUT

#define MT_TXWI_FLAGS_TX_RATE_LUT (1U << 15)

◆ MT_TXWI_ACK_CTL_REQ

#define MT_TXWI_ACK_CTL_REQ (1U << 0)

◆ MT_TXWI_ACK_CTL_NSEQ

#define MT_TXWI_ACK_CTL_NSEQ (1U << 1)

◆ MT_TXWI_ACK_CTL_BA_WINDOW_MASK

#define MT_TXWI_ACK_CTL_BA_WINDOW_MASK (0x3FU << 2)

◆ MT_RXWI_RATE_INDEX_MASK

#define MT_RXWI_RATE_INDEX_MASK 0x003F

◆ MT_RXWI_RATE_LDPC

#define MT_RXWI_RATE_LDPC (1U << 6)

◆ MT_RXWI_RATE_BW_MASK

#define MT_RXWI_RATE_BW_MASK (3U << 7)

◆ MT_RXWI_RATE_SGI

#define MT_RXWI_RATE_SGI (1U << 9)

◆ MT_RXWI_RATE_STBC

#define MT_RXWI_RATE_STBC (1U << 10)

◆ MT_RXWI_RATE_PHY_MASK

#define MT_RXWI_RATE_PHY_MASK (7U << 13)

◆ MT_PHY_TYPE_CCK

#define MT_PHY_TYPE_CCK 0

◆ MT_PHY_TYPE_OFDM

#define MT_PHY_TYPE_OFDM 1

◆ MT_PHY_TYPE_HT

#define MT_PHY_TYPE_HT 2

◆ MT_PHY_TYPE_VHT

#define MT_PHY_TYPE_VHT 4

◆ MT_DMA_HDR_LEN

#define MT_DMA_HDR_LEN 4

◆ MT_RX_RXWI_LEN

#define MT_RX_RXWI_LEN 32

◆ MT_FCE_INFO_LEN

#define MT_FCE_INFO_LEN 4

◆ MT_RXINFO_BA

#define MT_RXINFO_BA (1U << 0)

◆ MT_RXINFO_DATA

#define MT_RXINFO_DATA (1U << 1)

◆ MT_RXINFO_NULL

#define MT_RXINFO_NULL (1U << 2)

◆ MT_RXINFO_FRAG

#define MT_RXINFO_FRAG (1U << 3)

◆ MT_RXINFO_UNICAST

#define MT_RXINFO_UNICAST (1U << 4)

◆ MT_RXINFO_MULTICAST

#define MT_RXINFO_MULTICAST (1U << 5)

◆ MT_RXINFO_BROADCAST

#define MT_RXINFO_BROADCAST (1U << 6)

◆ MT_RXINFO_MYBSS

#define MT_RXINFO_MYBSS (1U << 7)

◆ MT_RXINFO_CRCERR

#define MT_RXINFO_CRCERR (1U << 8)

◆ MT_RXINFO_ICVERR

#define MT_RXINFO_ICVERR (1U << 9)

◆ MT_RXINFO_MICERR

#define MT_RXINFO_MICERR (1U << 10)

◆ MT_RXINFO_AMSDU

#define MT_RXINFO_AMSDU (1U << 11)

◆ MT_RXINFO_HTC

#define MT_RXINFO_HTC (1U << 12)

◆ MT_RXINFO_RSSI

#define MT_RXINFO_RSSI (1U << 13)

◆ MT_RXINFO_L2PAD

#define MT_RXINFO_L2PAD (1U << 14)

◆ MT_RXINFO_AMPDU

#define MT_RXINFO_AMPDU (1U << 15)

◆ MT_RXINFO_DECRYPT

#define MT_RXINFO_DECRYPT (1U << 16)

◆ MT_RXINFO_PN_LEN

#define MT_RXINFO_PN_LEN (7U << 19)

◆ MT_RXINFO_PROBE_RESP

#define MT_RXINFO_PROBE_RESP (1U << 24)

◆ MT_RXINFO_BEACON

#define MT_RXINFO_BEACON (1U << 25)

◆ MT_RXWI_CTL_WCID_MASK

#define MT_RXWI_CTL_WCID_MASK 0x00FF

◆ MT_RXWI_CTL_MPDU_LEN_MASK

#define MT_RXWI_CTL_MPDU_LEN_MASK (0x3FFFU << 16)

◆ MT_RXWI_CTL_MPDU_LEN_SHIFT

#define MT_RXWI_CTL_MPDU_LEN_SHIFT 16

◆ MT_RXWI_CTL_EOF

#define MT_RXWI_CTL_EOF (1U << 31)

◆ MT_RXWI_SIZE

#define MT_RXWI_SIZE 32

◆ __mt76_put_le32

#define __mt76_put_le32	(		_p,
			_v )

Value:

        do { \
        (_p)[0] = (uint8_t)(_v);                \
        (_p)[1] = (uint8_t)((_v) >> 8);         \
        (_p)[2] = (uint8_t)((_v) >> 16);        \
        (_p)[3] = (uint8_t)((_v) >> 24);        \
    } while (0)

◆ __mt76_get_le32

#define __mt76_get_le32 ( _p )

Value:

    (   (uint32_t)(_p)[0]                   \
      | ((uint32_t)(_p)[1] << 8)            \
      | ((uint32_t)(_p)[2] << 16)           \
      | ((uint32_t)(_p)[3] << 24))

◆ __mt76_get_le16

#define __mt76_get_le16 ( _p )

Value:

( (uint16_t)(_p)[0] \

| ((uint16_t)(_p)[1] << 8))

uint16_t

unsigned short uint16_t

Definition stdint.h:7

◆ __mt76_put_le16

#define __mt76_put_le16	(		_p,
			_v )

Value:

        do { \
        (_p)[0] = (uint8_t)(_v);                \
        (_p)[1] = (uint8_t)((_v) >> 8);         \
    } while (0)

◆ __mt76_round_up

#define __mt76_round_up	(		_x,
			_n )

Value:

(((_x) + ((_n) - 1)) & ~((_n) - 1))

◆ __mt76_min

#define __mt76_min	(		_a,
			_b )

Value:

((_a) < (_b) ? (_a) : (_b))

◆ __mt76_rev

#define __mt76_rev ( _priv )

Value:

((uint16_t)((_priv)->asic_rev & 0xFFFF))

◆ MT76_PROT_CFG_RATE

#define MT76_PROT_CFG_RATE ( _v )

Value:

(((_v) & 0x7fff) << 0)

◆ MT76_PROT_CFG_NAV

#define MT76_PROT_CFG_NAV ( _v )

Value:

(((_v) & 0x1) << 15)

◆ MT76_PROT_CFG_CTRL

#define MT76_PROT_CFG_CTRL ( _v )

Value:

(((_v) & 0x1) << 16)

◆ MT76_PROT_CFG_TXOP_ALLOW

#define MT76_PROT_CFG_TXOP_ALLOW ( _v )

Value:

(((_v) & 0x3f) << 17)

◆ MT76_PROT_CFG_RTS_THRESH

#define MT76_PROT_CFG_RTS_THRESH (1U << 23)

◆ MT76_DEFAULT_PROT_CFG_CCK

#define MT76_DEFAULT_PROT_CFG_CCK

Value:

(MT76_PROT_CFG_RATE(0x3) | MT76_PROT_CFG_NAV(1) | \

MT76_PROT_CFG_TXOP_ALLOW(0x3f) | MT76_PROT_CFG_RTS_THRESH)

MT76_PROT_CFG_NAV

#define MT76_PROT_CFG_NAV(_v)

Definition vsf_wifi_mt76.c:1180

MT76_PROT_CFG_RTS_THRESH

#define MT76_PROT_CFG_RTS_THRESH

Definition vsf_wifi_mt76.c:1183

MT76_PROT_CFG_RATE

#define MT76_PROT_CFG_RATE(_v)

Definition vsf_wifi_mt76.c:1179

◆ MT76_DEFAULT_PROT_CFG_OFDM

#define MT76_DEFAULT_PROT_CFG_OFDM

Value:

(MT76_PROT_CFG_RATE(0x2004) | MT76_PROT_CFG_NAV(1) | \

MT76_PROT_CFG_TXOP_ALLOW(0x3f) | MT76_PROT_CFG_RTS_THRESH)

◆ MT76_DEFAULT_PROT_CFG_20

#define MT76_DEFAULT_PROT_CFG_20

Value:

(MT76_PROT_CFG_RATE(0x2004) | MT76_PROT_CFG_CTRL(1) | \

MT76_PROT_CFG_NAV(1) | MT76_PROT_CFG_TXOP_ALLOW(0x17))

MT76_PROT_CFG_CTRL

#define MT76_PROT_CFG_CTRL(_v)

Definition vsf_wifi_mt76.c:1181

MT76_PROT_CFG_TXOP_ALLOW

#define MT76_PROT_CFG_TXOP_ALLOW(_v)

Definition vsf_wifi_mt76.c:1182

◆ MT76_DEFAULT_PROT_CFG_40

#define MT76_DEFAULT_PROT_CFG_40

Value:

(MT76_PROT_CFG_RATE(0x2084) | MT76_PROT_CFG_CTRL(1) | \

MT76_PROT_CFG_NAV(1) | MT76_PROT_CFG_TXOP_ALLOW(0x3f))

◆ __mt76_cfg_read

#define __mt76_cfg_read	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->base.reg_read(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::base

vsf_wifi_reg_bus_t base

Definition vsf_wifi_mt76.h:91

vsf_wifi_reg_bus_t::reg_read

vsf_err_t(* reg_read)(vsf_wifi_t *wifi, uint32_t reg, uint32_t *out, vsf_wifi_done_t done)

Definition vsf_wifi.h:230

◆ __mt76_cfg_write

#define __mt76_cfg_write	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->base.reg_write(__wifi, __VA_ARGS__)

vsf_wifi_reg_bus_t::reg_write

vsf_err_t(* reg_write)(vsf_wifi_t *wifi, uint32_t reg, uint32_t val, vsf_wifi_done_t done)

Definition vsf_wifi.h:222

◆ __mt76_fce_write

#define __mt76_fce_write	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->fce_write(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::fce_write

vsf_err_t(* fce_write)(vsf_wifi_t *wifi, uint32_t addr, uint32_t val, vsf_wifi_done_t done)

Definition vsf_wifi_mt76.h:96

◆ __mt76_dev_cmd

#define __mt76_dev_cmd	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->dev_cmd(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::dev_cmd

vsf_err_t(* dev_cmd)(vsf_wifi_t *wifi, uint8_t req, uint16_t value, uint16_t index, vsf_wifi_done_t done)

Definition vsf_wifi_mt76.h:101

◆ __mt76_dev_class_cmd

#define __mt76_dev_class_cmd	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->dev_class_cmd(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::dev_class_cmd

vsf_err_t(* dev_class_cmd)(vsf_wifi_t *wifi, uint8_t req, uint16_t value, uint16_t index, const uint8_t *data, uint16_t len, vsf_wifi_done_t done)

Definition vsf_wifi_mt76.h:106

◆ __mt76_mcu_cmd

#define __mt76_mcu_cmd	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->mcu_cmd(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::mcu_cmd

vsf_err_t(* mcu_cmd)(vsf_wifi_t *wifi, const uint8_t *data, uint16_t len, vsf_wifi_done_t done)

Definition vsf_wifi_mt76.h:115

◆ __mt76_tx_frame

#define __mt76_tx_frame	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->tx_frame(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::tx_frame

vsf_err_t(* tx_frame)(vsf_wifi_t *wifi, const uint8_t *data, uint16_t len, uint8_t queue_idx, vsf_wifi_done_t done)

Definition vsf_wifi_mt76.h:120

◆ __mt76_rx_submit

#define __mt76_rx_submit	(		__wifi,
			... )

Value:

__mt76_bus_ops(__wifi)->rx_submit(__wifi, __VA_ARGS__)

vsf_wifi_mt76_bus_ops_t::rx_submit

vsf_err_t(* rx_submit)(vsf_wifi_t *wifi, uint8_t *buf, uint16_t len, uint8_t queue_idx)

Definition vsf_wifi_mt76.h:124

◆ MT76_RATE_UP_THRESHOLD

#define MT76_RATE_UP_THRESHOLD 3

◆ MT76_RATE_TABLE_MIN

#define MT76_RATE_TABLE_MIN 0 /* CCK 1 Mbps */

◆ MT76_RATE_TABLE_MAX

#define MT76_RATE_TABLE_MAX (dimof(__mt76_rate_table) - 1)

◆ MT76_RATE_TABLE_INIT

#define MT76_RATE_TABLE_INIT 0 /* CCK 1 Mbps */

◆ MT76_RATE_TABLE_INIT_5G

#define MT76_RATE_TABLE_INIT_5G 12 /* HT MCS0 (Linux mt76x02 starts here) */

◆ MT76_TX_QUEUE_MGMT

#define MT76_TX_QUEUE_MGMT 1

Typedef Documentation

◆ mt76_rate_power_t

typedef struct mt76_rate_power_t mt76_rate_power_t

◆ mt76_tx_power_info_t

typedef struct mt76_tx_power_info_t mt76_tx_power_info_t

◆ mt76_reg_pair_t

typedef struct mt76_reg_pair_t mt76_reg_pair_t

◆ mt76_channel_cfg_t

typedef struct mt76_channel_cfg_t mt76_channel_cfg_t

Enumeration Type Documentation

◆ mt76x02_cipher_type

enum mt76x02_cipher_type

Enumerator
MT76X02_CIPHER_NONE
MT76X02_CIPHER_WEP40
MT76X02_CIPHER_WEP104
MT76X02_CIPHER_TKIP
MT76X02_CIPHER_AES_CCMP
MT76X02_CIPHER_CKIP40
MT76X02_CIPHER_CKIP104
MT76X02_CIPHER_CKIP128
MT76X02_CIPHER_WAPI

◆ mt76_state_t

enum mt76_state_t

Enumerator
MT76_STATE_IDLE
MT76_STATE_INIT_READ_ASIC
MT76_STATE_INIT_MCU_Q_SELECT
MT76_STATE_INIT_MCU_RADIO_ON
MT76_STATE_INIT_EEPROM_LOAD
MT76_STATE_INIT_MAC_ADDR
MT76_STATE_INIT_USB_DMA
MT76_STATE_INIT_MAC_RESET
MT76_STATE_INIT_WCID_RESET
MT76_STATE_INIT_KEY_RESET
MT76_STATE_INIT_BEACON
MT76_STATE_INIT_MISC
MT76_STATE_INIT_LOAD_CR
MT76_STATE_INIT_PHY
MT76_STATE_INIT_MAC_STOP
MT76_STATE_INIT_READY

◆ mt76_fw_state_t

enum mt76_fw_state_t

Enumerator
MT76_FW_STATE_RESET_WLAN
MT76_FW_STATE_RESET_WLAN_RF
MT76_FW_STATE_RESET_WLAN_EN
MT76_FW_STATE_POWER_ON_MTCMOS
MT76_FW_STATE_POWER_ON_MTCMOS_POLL
MT76_FW_STATE_POWER_ON_MTCMOS_CLEAR1
MT76_FW_STATE_POWER_ON_MTCMOS_CLEAR2
MT76_FW_STATE_POWER_ON_MTCMOS_SET2
MT76_FW_STATE_POWER_ON_MTCMOS_CLEAR3
MT76_FW_STATE_POWER_ON_AD_DA
MT76_FW_STATE_POWER_ON_AD_DA_WRITE
MT76_FW_STATE_POWER_ON_WLAN_EN
MT76_FW_STATE_POWER_ON_WLAN_EN_WRITE
MT76_FW_STATE_POWER_ON_BBP_RST
MT76_FW_STATE_POWER_ON_BBP_RST_WRITE
MT76_FW_STATE_POWER_ON_RF
MT76_FW_STATE_WAIT_MAC
MT76_FW_STATE_READ_ASIC_REV
MT76_FW_STATE_CHECK_PATCH
MT76_FW_STATE_ACQUIRE_SEM
MT76_FW_STATE_ENABLE_USB_DMA
MT76_FW_STATE_VENDOR_RESET_DELAY
MT76_FW_STATE_ENABLE_USB_DMA_CFG
MT76_FW_STATE_FCE_PSE
MT76_FW_STATE_FCE_BASE
MT76_FW_STATE_FCE_MAX
MT76_FW_STATE_FCE_PDMA
MT76_FW_STATE_FCE_SKIP
MT76_FW_STATE_UPLOAD
MT76_FW_STATE_ENABLE_PATCH
MT76_FW_STATE_RESET_WMT
MT76_FW_STATE_WAIT_WMT
MT76_FW_STATE_POLL_PATCH
MT76_FW_STATE_RELEASE_SEM
MT76_FW_STATE_PARSE_FW_HEADER
MT76_FW_STATE_LOAD_IVB
MT76_FW_STATE_POLL_FW_READY
MT76_FW_STATE_SET_COMREG
MT76_FW_STATE_REENABLE_FCE
MT76_FW_STATE_DONE

◆ mt76_fw_stage_t

enum mt76_fw_stage_t

Enumerator
MT76_FW_STAGE_PATCH
MT76_FW_STAGE_ILM
MT76_FW_STAGE_DLM

◆ mt76_fw_send_state_t

enum mt76_fw_send_state_t

Enumerator
MT76_FW_SEND_IDLE
MT76_FW_SEND_CHUNK
MT76_FW_SEND_FCE_LEN
MT76_FW_SEND_BULK
MT76_FW_SEND_IDX_READ
MT76_FW_SEND_IDX_WRITE

Function Documentation

◆ __mt76_firmware_load()

vsf_err_t __mt76_firmware_load	(	vsf_wifi_t *	wifi,
		vsf_wifi_done_t	done )

extern

◆ __mt76_init()

vsf_err_t __mt76_init	(	vsf_wifi_t *	wifi,
		vsf_wifi_done_t	done )

extern

◆ __mt76_fini()

void __mt76_fini ( vsf_wifi_t * wifi )

extern

◆ __mt76_eeprom_load()

vsf_err_t __mt76_eeprom_load	(	vsf_wifi_t *	wifi,
		vsf_wifi_done_t	done )

extern

◆ __mt76_eeprom_get_mac()

const uint8_t * __mt76_eeprom_get_mac ( vsf_wifi_t * wifi )

extern

◆ __mt76_set_channel()

vsf_err_t __mt76_set_channel	(	vsf_wifi_t *	wifi,
		uint8_t	channel,
		vsf_wifi_done_t	done )

extern

◆ __mt76_set_rx_filter()

vsf_err_t __mt76_set_rx_filter	(	vsf_wifi_t *	wifi,
		uint32_t	mask,
		vsf_wifi_done_t	done )

extern

◆ __mt76_set_mac_addr()

vsf_err_t __mt76_set_mac_addr	(	vsf_wifi_t *	wifi,
		const uint8_t	mac[6],
		vsf_wifi_done_t	done )

extern

◆ __mt76_set_bssid()

vsf_err_t __mt76_set_bssid	(	vsf_wifi_t *	wifi,
		const uint8_t	bssid[6],
		vsf_wifi_done_t	done )

extern

◆ __mt76_set_auth_mode()

vsf_err_t __mt76_set_auth_mode	(	vsf_wifi_t *	wifi,
		const vsf_wifi_auth_cfg_t *	cfg,
		vsf_wifi_done_t	done )

extern

◆ __mt76_connect()

vsf_err_t __mt76_connect	(	vsf_wifi_t *	wifi,
		const uint8_t	bssid[6],
		const uint8_t *	ssid,
		uint8_t	ssid_len,
		uint8_t	channel,
		vsf_wifi_done_t	done )

extern

◆ __mt76_disconnect()

vsf_err_t __mt76_disconnect	(	vsf_wifi_t *	wifi,
		vsf_wifi_done_t	done )

extern

◆ __mt76_get_link_info()

vsf_err_t __mt76_get_link_info	(	vsf_wifi_t *	wifi,
		vsf_wifi_link_info_t *	info )

extern

◆ __mt76_parse_rx()

void __mt76_parse_rx	(	vsf_wifi_t *	wifi,
		uint8_t *	frame,
		uint16_t	len )

extern

◆ __mt76_tx()

vsf_err_t __mt76_tx	(	vsf_wifi_t *	wifi,
		const uint8_t *	frame,
		uint16_t	len )

extern

◆ __mt76_eeprom_load_start()

vsf_err_t __mt76_eeprom_load_start	(	vsf_wifi_t *	wifi,
		vsf_wifi_done_t	done )

◆ __mt76_eeprom_parse_hw_cap()

void __mt76_eeprom_parse_hw_cap ( vsf_wifi_t * wifi )

Variable Documentation

◆ vsf_wifi_mt76_drv

const vsf_wifi_chip_drv_t vsf_wifi_mt76_drv

Initial value:

= {
    .name           = "mt7612u",
    .firmware_load  = __mt76_firmware_load,
    .init           = __mt76_init,
    .fini           = __mt76_fini,
    .set_channel    = __mt76_set_channel,
    .set_rx_filter  = __mt76_set_rx_filter,
    .set_mac_addr   = __mt76_set_mac_addr,
    .set_bssid      = __mt76_set_bssid,
    .set_auth_mode  = __mt76_set_auth_mode,
    .connect        = __mt76_connect,
    .disconnect     = __mt76_disconnect,
    .get_link_info  = __mt76_get_link_info,
    .parse_rx       = __mt76_parse_rx,
    .build_tx       = NULL,
    .tx             = __mt76_tx,
 
 
    .crypto_ops     = &__mt76_crypto_ops,
 
}

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ VSF_WIFI_MT76_CFG_FORCE_SW_CCMP_TX

◆ MT76_VEND_TYPE_CFG

◆ MT76_ASIC_VERSION

◆ MT76_USB_U3DMA_CFG

◆ MT76_USB_DMA_CFG_RX_DROP_OR_PAD

◆ MT76_USB_DMA_CFG_RX_BULK_AGG_EN

◆ MT76_USB_DMA_CFG_RX_BULK_EN

◆ MT76_USB_DMA_CFG_TX_BULK_EN

◆ MT76_WPDMA_GLO_CFG

◆ MT76_MAC_SYS_CTRL

◆ MT76_MAC_SYS_CTRL_RESET_CSR

◆ MT76_MAC_SYS_CTRL_RESET_BBP

◆ MT76_MAC_SYS_CTRL_ENABLE_TX

◆ MT76_MAC_SYS_CTRL_ENABLE_RX

◆ MT76_RX_FILTR_CFG

◆ MT76_FCE_DMA_ADDR

◆ MT76_FCE_DMA_LEN

◆ MT76_TX_CPU_FROM_FCE_CPU_DESC_IDX

◆ MT76_TX_CPU_FROM_FCE_BASE_PTR

◆ MT76_TX_CPU_FROM_FCE_MAX_COUNT

◆ MT76_FCE_PSE_CTRL

◆ MT76_FCE_PDMA_GLOBAL_CONF

◆ MT76_FCE_SKIP_FS

◆ MT76_MCU_COM_REG0

◆ MT76_MCU_CLOCK_CTL

◆ MT76_MCU_RESET_CTL

◆ MT76_MCU_SEMAPHORE_03

◆ MT76_REV_E3

◆ MT76_CHIP_ID_7612

◆ MT76_CHIP_ID_7632

◆ MT76_CHIP_ID_7662

◆ MT76_CHIP_ID_7602

◆ MT76_PATCH_HDR_SIZE

◆ MT76_FW_HDR_SIZE

◆ MT76_ROM_PATCH_OFFSET

◆ MT76_ILM_OFFSET

◆ MT76_DLM_OFFSET

◆ MT76_DLM_OFFSET_E3_EXTRA

◆ MT76_USB_DMA_CFG_VAL

◆ MT76_WLAN_FUN_CTRL

◆ MT76_WLAN_FUN_CTRL_WLAN_EN

◆ MT76_WLAN_FUN_CTRL_WLAN_CLK_EN

◆ MT76_WLAN_FUN_CTRL_WLAN_RESET_RF

◆ MT76_WLAN_FUN_CTRL_FRC_WL_ANT_SEL

◆ MT76_WLAN_MTC_CTRL

◆ MT76_WLAN_MTC_CTRL_MTCMOS_PWR_UP

◆ MT76_WLAN_MTC_CTRL_PWR_ACK

◆ MT76_WLAN_MTC_CTRL_PWR_ACK_S

◆ MT76_WLAN_MTC_CTRL_STATE_UP

◆ MT76_MAC_CSR0

◆ MT76_WPDMA_GLO_CFG_TX_DMA_EN

◆ MT76_WPDMA_GLO_CFG_TX_DMA_BUSY

◆ MT76_WPDMA_GLO_CFG_RX_DMA_EN

◆ MT76_WPDMA_GLO_CFG_RX_DMA_BUSY

◆ MT76_US_CYC_CFG

◆ MT76_US_CYC_CNT

◆ MT76_PBF_SYS_CTRL

◆ MT76_PBF_CFG

◆ MT76_PBF_TX_MAX_PCNT

◆ MT76_PBF_RX_MAX_PCNT

◆ MT76_BCN_OFFSET_BASE

◆ MT76_BCN_OFFSET

◆ MT76_MAC_ADDR_DW0

◆ MT76_MAC_ADDR_DW1

◆ MT76_MAC_ADDR_DW1_U2ME_MASK

◆ MT76_MAC_BSSID_DW0

◆ MT76_MAC_BSSID_DW1

◆ MT76_MAC_BSSID_DW1_MBSS_MODE

◆ MT76_MAC_BSSID_DW1_MBSS_LOCAL_BIT

◆ MT76_MAC_BSSID_DW1_MBEACON_N_SHIFT

◆ MT76_MAX_LEN_CFG

◆ MT76_AMPDU_MAX_LEN_20M1S

◆ MT76_AMPDU_MAX_LEN_20M2S