Go to the source code of this file.
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| enum | vsf_spi_mode_t {
VSF_SPI_MASTER = 1 << 2
,
VSF_SPI_SLAVE = 0 << 2
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VSF_SPI_MSB_FIRST = 0 << 7
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VSF_SPI_LSB_FIRST = 1 << 7
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VSF_SPI_CPOL_LOW = 0 << 1
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VSF_SPI_CPOL_HIGH = 1 << 1
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VSF_SPI_CPHA_LOW = 0 << 0
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VSF_SPI_CPHA_HIGH = 1 << 0
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VSF_SPI_MODE_0 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_LOW
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VSF_SPI_MODE_1 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_HIGH
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VSF_SPI_MODE_2 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_LOW
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VSF_SPI_MODE_3 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_HIGH
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VSF_SPI_CS_SOFTWARE_MODE = 1 << 26
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VSF_SPI_CS_HARDWARE_MODE = 1 << 18
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VSF_SPI_MOTOROLA_MODE = (0 << 20)
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VSF_SPI_TI_MODE = (1 << 20)
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VSF_SPI_MOTOROLA_MODE = (0 << 20)
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VSF_SPI_TI_MODE = (1 << 20)
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VSF_SPI_DATASIZE_8 = 0 << 11
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VSF_SPI_DATASIZE_16 = 1 << 11
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VSF_SPI_DATASIZE_16 = 1 << 11
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VSF_SPI_DATASIZE_32 = 1 << 27
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VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX = 0
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VSF_SPI_DATALINE_2_LINE_RX_ONLY = 1 << 10
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VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX = 1 << 15
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VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX = 0
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VSF_SPI_DATALINE_2_LINE_RX_ONLY = 1 << 10
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VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX = 1 << 15
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VSF_SPI_CRC_DISABLED = 0 << 13
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VSF_SPI_CRC_ENABLED = 1 << 13
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__VSF_HW_SPI_CTRL1_MASK
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__VSF_HW_SPI_CTRL2_MASK
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__VSF_HW_SPI_CS_MASK = VSF_SPI_CS_SOFTWARE_MODE
} |
| |
| enum | vsf_spi_irq_mask_t {
VSF_SPI_IRQ_MASK_TX = 1 << 1
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VSF_SPI_IRQ_MASK_RX = 1 << 0
,
VSF_SPI_IRQ_MASK_TX_CPL = 1 << 9
,
VSF_SPI_IRQ_MASK_RX_CPL = 1 << 10
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VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR = 1 << 6
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VSF_SPI_IRQ_MASK_CRC_ERR = 1 << 4
} |
| |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE
| #define VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE ENABLED |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK
| #define VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK ENABLED |
◆ VSF_SPI_MOTOROLA_MODE
| #define VSF_SPI_MOTOROLA_MODE VSF_SPI_MOTOROLA_MODE |
◆ VSF_SPI_TI_MODE
| #define VSF_SPI_TI_MODE VSF_SPI_TI_MODE |
◆ VSF_SPI_MOTOROLA_TI_MASK
◆ VSF_SPI_DATASIZE_16
| #define VSF_SPI_DATASIZE_16 VSF_SPI_DATASIZE_16 |
◆ VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX
| #define VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX |
◆ VSF_SPI_DATALINE_2_LINE_RX_ONLY
| #define VSF_SPI_DATALINE_2_LINE_RX_ONLY VSF_SPI_DATALINE_2_LINE_RX_ONLY |
◆ VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX
| #define VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX |
◆ vsf_spi_mode_t
◆ vsf_spi_irq_mask_t
◆ vsf_spi_mode_t
| Enumerator |
|---|
| VSF_SPI_MASTER | |
| VSF_SPI_SLAVE | |
| VSF_SPI_MSB_FIRST | |
| VSF_SPI_LSB_FIRST | |
| VSF_SPI_CPOL_LOW | |
| VSF_SPI_CPOL_HIGH | |
| VSF_SPI_CPHA_LOW | |
| VSF_SPI_CPHA_HIGH | |
| VSF_SPI_MODE_0 | |
| VSF_SPI_MODE_1 | |
| VSF_SPI_MODE_2 | |
| VSF_SPI_MODE_3 | |
| VSF_SPI_CS_SOFTWARE_MODE | |
| VSF_SPI_CS_HARDWARE_MODE | |
| VSF_SPI_MOTOROLA_MODE | |
| VSF_SPI_TI_MODE | |
| VSF_SPI_MOTOROLA_MODE | |
| VSF_SPI_TI_MODE | |
| VSF_SPI_DATASIZE_8 | |
| VSF_SPI_DATASIZE_16 | |
| VSF_SPI_DATASIZE_16 | |
| VSF_SPI_DATASIZE_32 | |
| VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX | |
| VSF_SPI_DATALINE_2_LINE_RX_ONLY | |
| VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX | |
| VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX | |
| VSF_SPI_DATALINE_2_LINE_RX_ONLY | |
| VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX | |
| VSF_SPI_CRC_DISABLED | |
| VSF_SPI_CRC_ENABLED | |
| __VSF_HW_SPI_CTRL1_MASK | |
| __VSF_HW_SPI_CTRL2_MASK | |
| __VSF_HW_SPI_CS_MASK | |
◆ vsf_spi_irq_mask_t
| Enumerator |
|---|
| VSF_SPI_IRQ_MASK_TX | |
| VSF_SPI_IRQ_MASK_RX | |
| VSF_SPI_IRQ_MASK_TX_CPL | |
| VSF_SPI_IRQ_MASK_RX_CPL | |
| VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR | |
| VSF_SPI_IRQ_MASK_CRC_ERR | |