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CMSDK_ARMv8MML_DP.h
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1/**************************************************************************/
8/* Copyright (c) 2015 - 2016 ARM LIMITED
9
10 All rights reserved.
11 Redistribution and use in source and binary forms, with or without
12 modification, are permitted provided that the following conditions are met:
13 - Redistributions of source code must retain the above copyright
14 notice, this list of conditions and the following disclaimer.
15 - Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18 - Neither the name of ARM nor the names of its contributors may be used
19 to endorse or promote products derived from this software without
20 specific prior written permission.
21 *
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 POSSIBILITY OF SUCH DAMAGE.
33 ---------------------------------------------------------------------------*/
34
35
36#ifndef CMSDK_ARMv8MML_DP_H
37#define CMSDK_ARMv8MML_DP_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43
44/* ------------------------- Interrupt Number Definition ------------------------ */
45
46typedef enum IRQn
47{
48/* -------------------- ARMv8MML Processor Exceptions Numbers ------------------- */
49 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
50 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
51 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
52 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
53 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
54 SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
55 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
56 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
57 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
58 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
59
60/* -------------------- ARMv8MML Specific Interrupt Numbers --------------------- */
61 UART0RX_IRQn = 0, /* UART 0 receive interrupt */
62 UART0TX_IRQn = 1, /* UART 0 transmit interrupt */
63 UART1RX_IRQn = 2, /* UART 1 receive interrupt */
64 UART1TX_IRQn = 3, /* UART 1 transmit interrupt */
65 UART2RX_IRQn = 4, /* UART 2 receive interrupt */
66 UART2TX_IRQn = 5, /* UART 2 transmit interrupt */
67 GPIO0ALL_IRQn = 6, /* GPIO 0 combined interrupt */
68 GPIO1ALL_IRQn = 7, /* GPIO 1 combined interrupt */
69 TIMER0_IRQn = 8, /* Timer 0 interrupt */
70 TIMER1_IRQn = 9, /* Timer 1 interrupt */
71 DUALTIMER_IRQn = 10, /* Dual Timer interrupt */
72 SPI_0_1_IRQn = 11, /* SPI #0, #1 interrupt */
73 UART_0_1_2_OVF_IRQn = 12, /* UART overflow (0, 1 & 2) interrupt */
74 ETHERNET_IRQn = 13, /* Ethernet interrupt */
75 I2S_IRQn = 14, /* Audio I2S interrupt */
76 TOUCHSCREEN_IRQn = 15, /* Touch Screen interrupt */
77 GPIO2_IRQn = 16, /* GPIO 2 combined interrupt */
78 GPIO3_IRQn = 17, /* GPIO 3 combined interrupt */
79 UART3RX_IRQn = 18, /* UART 3 receive interrupt */
80 UART3TX_IRQn = 19, /* UART 3 transmit interrupt */
81 UART4RX_IRQn = 20, /* UART 4 receive interrupt */
82 UART4TX_IRQn = 21, /* UART 4 transmit interrupt */
83 SPI_2_IRQn = 22, /* SPI #2 interrupt */
84 SPI_3_4_IRQn = 23, /* SPI #3, SPI #4 interrupt */
85 GPIO0_0_IRQn = 24, /* GPIO 0 individual interrupt ( 0) */
86 GPIO0_1_IRQn = 25, /* GPIO 0 individual interrupt ( 1) */
87 GPIO0_2_IRQn = 26, /* GPIO 0 individual interrupt ( 2) */
88 GPIO0_3_IRQn = 27, /* GPIO 0 individual interrupt ( 3) */
89 GPIO0_4_IRQn = 28, /* GPIO 0 individual interrupt ( 4) */
90 GPIO0_5_IRQn = 29, /* GPIO 0 individual interrupt ( 5) */
91 GPIO0_6_IRQn = 30, /* GPIO 0 individual interrupt ( 6) */
92 GPIO0_7_IRQn = 31, /* GPIO 0 individual interrupt ( 7) */
93 GPIO1_0_IRQn = 32, /* GPIO 1 individual interrupt ( 0) */
94 GPIO1_1_IRQn = 33, /* GPIO 1 individual interrupt ( 1) */
95 GPIO1_2_IRQn = 34, /* GPIO 1 individual interrupt ( 2) */
96 GPIO1_3_IRQn = 35, /* GPIO 1 individual interrupt ( 3) */
97 GPIO1_4_IRQn = 36, /* GPIO 1 individual interrupt ( 4) */
98 GPIO1_5_IRQn = 37, /* GPIO 1 individual interrupt ( 5) */
99 GPIO1_6_IRQn = 38, /* GPIO 1 individual interrupt ( 6) */
100 GPIO1_7_IRQn = 39, /* GPIO 1 individual interrupt ( 7) */
101 GPIO1_8_IRQn = 40, /* GPIO 1 individual interrupt ( 0) */
102 GPIO1_9_IRQn = 41, /* GPIO 1 individual interrupt ( 9) */
103 GPIO1_10_IRQn = 42, /* GPIO 1 individual interrupt (10) */
104 GPIO1_11_IRQn = 43, /* GPIO 1 individual interrupt (11) */
105 GPIO1_12_IRQn = 44, /* GPIO 1 individual interrupt (12) */
106 GPIO1_13_IRQn = 45, /* GPIO 1 individual interrupt (13) */
107 GPIO1_14_IRQn = 46, /* GPIO 1 individual interrupt (14) */
108 GPIO1_15_IRQn = 47, /* GPIO 1 individual interrupt (15) */
109 SPI_0B_IRQn = 48, /* SPI #0 interrupt */
110 Reserved_IRQn = 49, /* Reserved */
111 SECURETIMER0_IRQn = 50, /* Secure Timer 0 interrupt */
112 SECURETIMER1_IRQn = 51, /* Secure Timer 1 interrupt */
113 SPI_1B_IRQn = 52, /* SPI #1 interrupt */
114 SPI_2B_IRQn = 53, /* SPI #2 interrupt */
115 SPI_3B_IRQn = 54, /* SPI #3 interrupt */
116 SPI_4B_IRQn = 55 /* SPI #4 interrupt */
117} IRQn_Type;
118
119
120/* ================================================================================ */
121/* ================ Processor and Core Peripheral Section ================ */
122/* ================================================================================ */
123
124/* ------- Start of section using anonymous unions and disabling warnings ------- */
125#if defined (__CC_ARM)
126 #pragma push
127 #pragma anon_unions
128#elif defined (__ICCARM__)
129 #pragma language=extended
130#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
131 #pragma clang diagnostic push
132 #pragma clang diagnostic ignored "-Wc11-extensions"
133 #pragma clang diagnostic ignored "-Wreserved-id-macro"
134#elif defined (__GNUC__)
135 /* anonymous unions are enabled by default */
136#elif defined (__TMS470__)
137 /* anonymous unions are enabled by default */
138#elif defined (__TASKING__)
139 #pragma warning 586
140#elif defined (__CSMC__)
141 /* anonymous unions are enabled by default */
142#else
143 #warning Not supported compiler type
144#endif
145
146
147/* -------- Configuration of the Cortex-ARMv8MML Processor and Core Peripherals ------- */
148#define __ARMv8MML_REV 0x0001U /* Core revision r0p1 */
149#define __SAUREGION_PRESENT 1U /* SAU regions present */
150#define __MPU_PRESENT 1U /* MPU present */
151#define __VTOR_PRESENT 1U /* VTOR present */
152#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
153#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
154#define __FPU_PRESENT 1U /* FPU present */
155#define __FPU_DP 1U /* double precision FPU */
156#define __DSP_PRESENT 0U /* no DSP extension present */
157
158#include "core_armv8mml.h" /* Processor and core peripherals */
159#include "system_CMSDK_ARMv8MML.h" /* System Header */
160
161
162/* ================================================================================ */
163/* ================ Device Specific Peripheral Section ================ */
164/* ================================================================================ */
165
166/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
167typedef struct
168{
169 __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
170 __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
171 __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
172 union {
173 __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
174 __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
175 };
176 __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
177
178} CMSDK_UART_TypeDef;
179
180/* CMSDK_UART DATA Register Definitions */
181#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
182#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
183
184/* CMSDK_UART STATE Register Definitions */
185#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
186#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
187
188#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
189#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
190
191#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
192#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
193
194#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
195#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
196
197/* CMSDK_UART CTRL Register Definitions */
198#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
199#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
200
201#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
202#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
203
204#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
205#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
206
207#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
208#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
209
210#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
211#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
212
213#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
214#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
215
216#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
217#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
218
219#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
220#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
221
222#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
223#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
224
225#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
226#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
227
228#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
229#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
230
231/* CMSDK_UART BAUDDIV Register Definitions */
232#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
233#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
234
235
236/*----------------------------- Timer (TIMER) -------------------------------*/
237typedef struct
238{
239 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
240 __IOM uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
241 __IOM uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
242 union {
243 __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
244 __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
245 };
246
247} CMSDK_TIMER_TypeDef;
248
249/* CMSDK_TIMER CTRL Register Definitions */
250#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
251#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
252
253#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
254#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
255
256#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
257#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
258
259#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
260#define CMSDK_TIMER_CTRL_EN_Msk (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */
261
262/* CMSDK_TIMER VAL Register Definitions */
263#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
264#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */
265
266/* CMSDK_TIMER RELOAD Register Definitions */
267#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
268#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */
269
270/* CMSDK_TIMER INTSTATUS Register Definitions */
271#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
272#define CMSDK_TIMER_INTSTATUS_Msk (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
273
274/* CMSDK_TIMER INTCLEAR Register Definitions */
275#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
276#define CMSDK_TIMER_INTCLEAR_Msk (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
277
278
279/*------------- Timer (TIM) --------------------------------------------------*/
280typedef struct
281{
282 __IOM uint32_t T1LOAD; /* Offset: 0x000 (R/W) Timer 1 Load */
283 __IM uint32_t T1VALUE; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
284 __IOM uint32_t T1CTRL; /* Offset: 0x008 (R/W) Timer 1 Control */
285 __OM uint32_t T1INTCLR; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
286 __IM uint32_t T1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
287 __IM uint32_t T1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
288 __IOM uint32_t T1BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */
289 uint32_t RESERVED0;
290 __IOM uint32_t T2LOAD; /* Offset: 0x020 (R/W) Timer 2 Load */
291 __IM uint32_t T2VALUE; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
292 __IOM uint32_t T2CTRL; /* Offset: 0x028 (R/W) Timer 2 Control */
293 __OM uint32_t T2INTCLR; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
294 __IM uint32_t T2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
295 __IM uint32_t T2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
296 __IOM uint32_t T2BGLOAD; /* Offset: 0x038 (R/W) Background Load Register */
297 uint32_t RESERVED1[945];
298 __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
299 __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
300} CMSDK_DUALTIMER_BOTH_TypeDef;
301
302
303typedef struct
304{
305 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Timer Load */
306 __IM uint32_t VALUE; /* Offset: 0x000 (R/W) Timer Counter Current Value */
307 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Timer Control */
308 __OM uint32_t INTCLR; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
309 __IM uint32_t RIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
310 __IM uint32_t MIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
311 __IOM uint32_t BGLOAD; /* Offset: 0x000 (R/W) Background Load Register */
312} CMSDK_DUALTIMER_SINGLE_TypeDef;
313
314/* CMSDK_DUALTIMER_SINGLE LOAD Register Definitions */
315#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
316#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
317
318/* CMSDK_DUALTIMER_SINGLE VALUE Register Definitions */
319#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
320#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
321
322/* CMSDK_DUALTIMER_SINGLE CTRL Register Definitions */
323#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
324#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
325
326#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
327#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
328
329#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
330#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
331
332#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
333#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
334
335#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
336#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
337
338#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
339#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
340
341/* CMSDK_DUALTIMER_SINGLE INTCLR Register Definitions */
342#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
343#define CMSDK_DUALTIMER_INTCLR_Msk (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
344
345/* CMSDK_DUALTIMER_SINGLE RIS Register Definitions */
346#define CMSDK_DUALTIMER_RIS_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
347#define CMSDK_DUALTIMER_RIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
348
349/* CMSDK_DUALTIMER_SINGLE MIS Register Definitions */
350#define CMSDK_DUALTIMER_MIS_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
351#define CMSDK_DUALTIMER_MIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
352
353/* CMSDK_DUALTIMER_SINGLE BGLOAD Register Definitions */
354#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
355#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
356
357
358/*-------------------- General Purpose Input Output (GPIO) -------------------*/
359typedef struct
360{
361 __IOM uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
362 __IOM uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
363 uint32_t RESERVED0[2];
364 __IOM uint32_t OUTENSET; /* Offset: 0x010 (R/W) Output Enable Set Register */
365 __IOM uint32_t OUTENCLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
366 __IOM uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
367 __IOM uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
368 __IOM uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
369 __IOM uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
370 __IOM uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
371 __IOM uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
372 __IOM uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
373 __IOM uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
374 union {
375 __IM uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
376 __OM uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
377 };
378 uint32_t RESERVED1[241];
379 __IOM uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
380 __IOM uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
381} CMSDK_GPIO_TypeDef;
382
383/* CMSDK_GPIO DATA Register Definitions */
384#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
385#define CMSDK_GPIO_DATA_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */
386
387/* CMSDK_GPIO DATAOUT Register Definitions */
388#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
389#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
390
391/* CMSDK_GPIO OUTENSET Register Definitions */
392#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
393#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
394
395/* CMSDK_GPIO OUTENCLR Register Definitions */
396#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
397#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
398
399/* CMSDK_GPIO ALTFUNCSET Register Definitions */
400#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
401#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
402
403/* CMSDK_GPIO ALTFUNCCLR Register Definitions */
404#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
405#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
406
407/* CMSDK_GPIO INTENSET Register Definitions */
408#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
409#define CMSDK_GPIO_INTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
410
411/* CMSDK_GPIO INTENCLR Register Definitions */
412#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
413#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
414
415/* CMSDK_GPIO INTTYPESET Register Definitions */
416#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
417#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
418
419/* CMSDK_GPIO INTTYPECLR Register Definitions */
420#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
421#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
422
423/* CMSDK_GPIO INTPOLSET Register Definitions */
424#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
425#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
426
427/* CMSDK_GPIO INTPOLCLR Register Definitions */
428#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
429#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
430
431/* CMSDK_GPIO INTCLEAR Register Definitions */
432#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
433#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
434
435/* CMSDK_GPIO INTCLEAR Register Definitions */
436#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
437#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
438
439/* CMSDK_GPIO MASKLOWBYTE Register Definitions */
440#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
441#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
442
443/* CMSDK_GPIO MASKHIGHBYTE Register Definitions */
444#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
445#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
446
447
448/*------------- System Control (SYSCON) --------------------------------------*/
449typedef struct
450{
451 __IOM uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
452 __IOM uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
453 __IOM uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
454 __IOM uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
455 __IOM uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
456} CMSDK_SYSCON_TypeDef;
457
458/* CMSDK_SYSCON REMAP Register Definitions */
459#define CMSDK_SYSCON_REMAP_Pos 0
460#define CMSDK_SYSCON_REMAP_Msk (0x1UL /*<< CMSDK_SYSCON_REMAP_Pos*/) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
461
462/* CMSDK_SYSCON PMUCTRL Register Definitions */
463#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
464#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x1UL /*<< CMSDK_SYSCON_PMUCTRL_EN_Pos*/) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
465
466/* CMSDK_SYSCON LOCKUPRST Register Definitions */
467#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
468#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x1UL /*<< CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos*/) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
469
470/* CMSDK_SYSCON EMICTRL Register Definitions */
471#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
472#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
473
474#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
475#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
476
477#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
478#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
479
480#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
481#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x7UL /*<< CMSDK_SYSCON_EMICTRL_RCYC_Pos*/) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
482
483/* CMSDK_SYSCON RSTINFO Register Definitions */
484#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
485#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
486
487#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
488#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
489
490#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
491#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x1UL /*<< CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos*/) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
492
493
494/*------------------- Watchdog ----------------------------------------------*/
495typedef struct
496{
497
498 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
499 __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
500 __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
501 __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
502 __IM uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
503 __IM uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
504 uint32_t RESERVED0[762];
505 __IOM uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
506 uint32_t RESERVED1[191];
507 __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
508 __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
509}CMSDK_WATCHDOG_TypeDef;
510
511/* CMSDK_WATCHDOG LOAD Register Definitions */
512#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
513#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */
514
515/* CMSDK_WATCHDOG VALUE Register Definitions */
516#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
517#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */
518
519/* CMSDK_WATCHDOG CTRL Register Definitions */
520#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
521#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
522
523#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
524#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
525
526/* CMSDK_WATCHDOG INTCLR Register Definitions */
527#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
528#define CMSDK_Watchdog_INTCLR_Msk (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
529
530/* CMSDK_WATCHDOG RAWINTSTAT Register Definitions */
531#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
532#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
533
534/* CMSDK_WATCHDOG MASKINTSTAT Register Definitions */
535#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
536#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
537
538/* CMSDK_WATCHDOG LOCK Register Definitions */
539#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
540#define CMSDK_Watchdog_LOCK_Msk (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */
541
542/* CMSDK_WATCHDOG INTEGTESTEN Register Definitions */
543#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
544#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
545
546/* CMSDK_WATCHDOG INTEGTESTOUTSET Register Definitions */
547#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
548#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
549
550
551
552/* -------------------- End of section using anonymous unions ------------------- */
553#if defined (__CC_ARM)
554 #pragma pop
555#elif defined (__ICCARM__)
556 /* leave anonymous unions enabled */
557#elif (__ARMCC_VERSION >= 6010050)
558 #pragma clang diagnostic pop
559#elif defined (__GNUC__)
560 /* anonymous unions are enabled by default */
561#elif defined (__TMS470__)
562 /* anonymous unions are enabled by default */
563#elif defined (__TASKING__)
564 #pragma warning restore
565#elif defined (__CSMC__)
566 /* anonymous unions are enabled by default */
567#else
568 #warning Not supported compiler type
569#endif
570
571
572
573
574/* ================================================================================ */
575/* ================ Peripheral memory map ================ */
576/* ================================================================================ */
577
578/* Peripheral and SRAM base address */
579#define CMSDK_FLASH_BASE (0x00000000UL)
580#define CMSDK_SRAM_BASE (0x20000000UL)
581#define CMSDK_PERIPH_BASE (0x40000000UL)
582
583#define CMSDK_RAM_BASE (0x20000000UL)
584#define CMSDK_APB_BASE (0x40000000UL)
585#define CMSDK_AHB_BASE (0x40010000UL)
586#define CMSDK_S_APB_BASE (0x50000000UL)
587
588/* APB peripherals */
589#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
590#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
591#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
592#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
593#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
594#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
595#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
596#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
597#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
598
599/* AHB peripherals */
600#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
601#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
602#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
603
604/* Secure APB peripherals */
605#define CMSDK_SECURETIMER0_BASE (CMSDK_S_APB_BASE + 0x0000UL)
606#define CMSDK_SECURETIMER1_BASE (CMSDK_S_APB_BASE + 0x1000UL)
607
608
609/* ================================================================================ */
610/* ================ Peripheral declaration ================ */
611/* ================================================================================ */
612
613#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
614#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
615#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
616#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
617#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
618#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
619#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
620#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
621#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
622#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
623#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
624#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
625#define CMSDK_SECURETIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER0_BASE)
626#define CMSDK_SECURETIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER1_BASE)
627
628
629#ifdef __cplusplus
630}
631#endif
632
633#endif /* CMSDK_ARMv8MML_DP_H */
IRQn_Type
enum IRQn IRQn_Type
SPI_0B_IRQn
@ SPI_0B_IRQn
Definition CMSDK_ARMv8MML_DP.h:109
GPIO2_IRQn
@ GPIO2_IRQn
Definition CMSDK_ARMv8MML_DP.h:77
GPIO1_14_IRQn
@ GPIO1_14_IRQn
Definition CMSDK_ARMv8MML_DP.h:107
PendSV_IRQn
@ PendSV_IRQn
Definition CMSDK_ARMv8MML_DP.h:57
UART4TX_IRQn
@ UART4TX_IRQn
Definition CMSDK_ARMv8MML_DP.h:82
TIMER1_IRQn
@ TIMER1_IRQn
Definition CMSDK_ARMv8MML_DP.h:70
UART2RX_IRQn
@ UART2RX_IRQn
Definition CMSDK_ARMv8MML_DP.h:65
I2S_IRQn
@ I2S_IRQn
Definition CMSDK_ARMv8MML_DP.h:75
UART4RX_IRQn
@ UART4RX_IRQn
Definition CMSDK_ARMv8MML_DP.h:81
SECURETIMER0_IRQn
@ SECURETIMER0_IRQn
Definition CMSDK_ARMv8MML_DP.h:111
UART2TX_IRQn
@ UART2TX_IRQn
Definition CMSDK_ARMv8MML_DP.h:66
TIMER0_IRQn
@ TIMER0_IRQn
Definition CMSDK_ARMv8MML_DP.h:69
UART3TX_IRQn
@ UART3TX_IRQn
Definition CMSDK_ARMv8MML_DP.h:80
GPIO1_6_IRQn
@ GPIO1_6_IRQn
Definition CMSDK_ARMv8MML_DP.h:99
GPIO0_6_IRQn
@ GPIO0_6_IRQn
Definition CMSDK_ARMv8MML_DP.h:91
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition CMSDK_ARMv8MML_DP.h:51
SPI_3B_IRQn
@ SPI_3B_IRQn
Definition CMSDK_ARMv8MML_DP.h:115
SPI_4B_IRQn
@ SPI_4B_IRQn
Definition CMSDK_ARMv8MML_DP.h:116
SVCall_IRQn
@ SVCall_IRQn
Definition CMSDK_ARMv8MML_DP.h:55
GPIO1_10_IRQn
@ GPIO1_10_IRQn
Definition CMSDK_ARMv8MML_DP.h:103
UART0TX_IRQn
@ UART0TX_IRQn
Definition CMSDK_ARMv8MML_DP.h:62
GPIO1_5_IRQn
@ GPIO1_5_IRQn
Definition CMSDK_ARMv8MML_DP.h:98
GPIO0_2_IRQn
@ GPIO0_2_IRQn
Definition CMSDK_ARMv8MML_DP.h:87
GPIO3_IRQn
@ GPIO3_IRQn
Definition CMSDK_ARMv8MML_DP.h:78
SPI_2B_IRQn
@ SPI_2B_IRQn
Definition CMSDK_ARMv8MML_DP.h:114
GPIO1ALL_IRQn
@ GPIO1ALL_IRQn
Definition CMSDK_ARMv8MML_DP.h:68
GPIO1_13_IRQn
@ GPIO1_13_IRQn
Definition CMSDK_ARMv8MML_DP.h:106
UsageFault_IRQn
@ UsageFault_IRQn
Definition CMSDK_ARMv8MML_DP.h:53
UART_0_1_2_OVF_IRQn
@ UART_0_1_2_OVF_IRQn
Definition CMSDK_ARMv8MML_DP.h:73
SysTick_IRQn
@ SysTick_IRQn
Definition CMSDK_ARMv8MML_DP.h:58
GPIO1_1_IRQn
@ GPIO1_1_IRQn
Definition CMSDK_ARMv8MML_DP.h:94
GPIO0_3_IRQn
@ GPIO0_3_IRQn
Definition CMSDK_ARMv8MML_DP.h:88
ETHERNET_IRQn
@ ETHERNET_IRQn
Definition CMSDK_ARMv8MML_DP.h:74
GPIO1_7_IRQn
@ GPIO1_7_IRQn
Definition CMSDK_ARMv8MML_DP.h:100
UART1TX_IRQn
@ UART1TX_IRQn
Definition CMSDK_ARMv8MML_DP.h:64
GPIO1_4_IRQn
@ GPIO1_4_IRQn
Definition CMSDK_ARMv8MML_DP.h:97
BusFault_IRQn
@ BusFault_IRQn
Definition CMSDK_ARMv8MML_DP.h:52
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition CMSDK_ARMv8MML_DP.h:56
GPIO1_11_IRQn
@ GPIO1_11_IRQn
Definition CMSDK_ARMv8MML_DP.h:104
GPIO0ALL_IRQn
@ GPIO0ALL_IRQn
Definition CMSDK_ARMv8MML_DP.h:67
SecureFault_IRQn
@ SecureFault_IRQn
Definition CMSDK_ARMv8MML_DP.h:54
GPIO0_5_IRQn
@ GPIO0_5_IRQn
Definition CMSDK_ARMv8MML_DP.h:90
UART0RX_IRQn
@ UART0RX_IRQn
Definition CMSDK_ARMv8MML_DP.h:61
GPIO1_12_IRQn
@ GPIO1_12_IRQn
Definition CMSDK_ARMv8MML_DP.h:105
HardFault_IRQn
@ HardFault_IRQn
Definition CMSDK_ARMv8MML_DP.h:50
GPIO0_4_IRQn
@ GPIO0_4_IRQn
Definition CMSDK_ARMv8MML_DP.h:89
DUALTIMER_IRQn
@ DUALTIMER_IRQn
Definition CMSDK_ARMv8MML_DP.h:71
GPIO1_0_IRQn
@ GPIO1_0_IRQn
Definition CMSDK_ARMv8MML_DP.h:93
GPIO1_9_IRQn
@ GPIO1_9_IRQn
Definition CMSDK_ARMv8MML_DP.h:102
GPIO0_1_IRQn
@ GPIO0_1_IRQn
Definition CMSDK_ARMv8MML_DP.h:86
GPIO1_3_IRQn
@ GPIO1_3_IRQn
Definition CMSDK_ARMv8MML_DP.h:96
SPI_1B_IRQn
@ SPI_1B_IRQn
Definition CMSDK_ARMv8MML_DP.h:113
TOUCHSCREEN_IRQn
@ TOUCHSCREEN_IRQn
Definition CMSDK_ARMv8MML_DP.h:76
GPIO1_8_IRQn
@ GPIO1_8_IRQn
Definition CMSDK_ARMv8MML_DP.h:101
GPIO1_2_IRQn
@ GPIO1_2_IRQn
Definition CMSDK_ARMv8MML_DP.h:95
SPI_3_4_IRQn
@ SPI_3_4_IRQn
Definition CMSDK_ARMv8MML_DP.h:84
SECURETIMER1_IRQn
@ SECURETIMER1_IRQn
Definition CMSDK_ARMv8MML_DP.h:112
Reserved_IRQn
@ Reserved_IRQn
Definition CMSDK_ARMv8MML_DP.h:110
UART1RX_IRQn
@ UART1RX_IRQn
Definition CMSDK_ARMv8MML_DP.h:63
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition CMSDK_ARMv8MML_DP.h:49
GPIO0_7_IRQn
@ GPIO0_7_IRQn
Definition CMSDK_ARMv8MML_DP.h:92
SPI_2_IRQn
@ SPI_2_IRQn
Definition CMSDK_ARMv8MML_DP.h:83
SPI_0_1_IRQn
@ SPI_0_1_IRQn
Definition CMSDK_ARMv8MML_DP.h:72
GPIO1_15_IRQn
@ GPIO1_15_IRQn
Definition CMSDK_ARMv8MML_DP.h:108
UART3RX_IRQn
@ UART3RX_IRQn
Definition CMSDK_ARMv8MML_DP.h:79
GPIO0_0_IRQn
@ GPIO0_0_IRQn
Definition CMSDK_ARMv8MML_DP.h:85
IRQn
IRQn
Definition f1c100s_reg.h:1131
__OM
#define __OM
Definition i_reg_gpio.h:47
__IM
#define __IM
Definition i_reg_gpio.h:42
__IOM
#define __IOM
Definition i_reg_gpio.h:52
uint32_t
unsigned uint32_t
Definition stdint.h:9
CMSDK_DUALTIMER_BOTH_TypeDef
Definition CMSDK_ARMv8MBL.h:278
CMSDK_DUALTIMER_SINGLE_TypeDef
Definition CMSDK_ARMv8MBL.h:301
CMSDK_GPIO_TypeDef
Definition CMSDK_ARMv8MBL.h:357
CMSDK_SYSCON_TypeDef
Definition CMSDK_ARMv8MBL.h:447
CMSDK_TIMER_TypeDef
Definition CMSDK_ARMv8MBL.h:235
CMSDK_UART_TypeDef
Definition CMSDK_ARMv8MBL.h:165
CMSDK_WATCHDOG_TypeDef
Definition CMSDK_ARMv8MBL.h:493
system_CMSDK_ARMv8MML.h
CMSIS Device System Header File for CMSDK_ARMv8MML Device.
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