#include <stdint.h>

Data Structures
struct	syscon_reg_t

struct	ccu_reg_t

struct	dram_reg_t

struct	pio_port_t

struct	pio_port_int_t

struct	pio_reg_t

struct	uart_reg_t

struct	spi_reg_t

struct	tcon_reg_t

struct	debe_reg_t

struct	tve_reg_t

struct	timer_reg_t

struct	musb_reg_t

struct	tp_reg_t

Macros
#define	SYSCON_BASE ((syscon_reg_t *)0x01c00000)

#define	SYSCON_USB_CTRL 0x004

#define	USB_FIFO_MODE (3UL << 0)

#define	USB_FIFO_MODE_8KB (1UL << 0)

#define	CCU_BASE ((ccu_reg_t *)0x01c20000)

#define	CCU_PLL_CPU_CTRL 0x000

#define	PLL_CPU_CTRL_PLL_ENABLE (1UL << 31)

#define	PLL_CPU_CTRL_LOCK (1UL << 28)

#define	__PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P(__P)

#define	__PLL_CPU_CTRL_PLL_FACTOR_N(__N)

#define	__PLL_CPU_CTRL_PLL_FACTOR_K(__K)

#define	__PLL_CPU_CTRL_PLL_FACTOR_M(__M)

#define	PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P(...)

#define	PLL_CPU_CTRL_PLL_FACTOR_N(...)

#define	PLL_CPU_CTRL_PLL_FACTOR_K(...)

#define	PLL_CPU_CTRL_PLL_FACTOR_M(...)

#define	CCU_PLL_AUDIO_CTRL 0x008

#define	PLL_AUDIO_CTRL_PLL_ENABLE (1UL << 31)

#define	PLL_AUDIO_CTRL_LOCK (1UL << 28)

#define	PLL_AUDIO_CTRL_PLL_SDM_EN (1UL << 24)

#define	__PLL_AUDIO_CTRL_PLL_FACTOR_N(__N)

#define	__PLL_AUDIO_CTRL_PLL_PREDIV_M(__M)

#define	PLL_AUDIO_CTRL_PLL_FACTOR_N(...)

#define	PLL_AUDIO_CTRL_PLL_PREDIV_M(...)

#define	CCU_PLL_VIDEO_CTRL 0x010

#define	PLL_VIDEO_CTRL_PLL_ENABLE (1UL << 31)

#define	PLL_VIDEO_CTRL_PLL_MODE (1UL << 30)

#define	PLL_VIDEO_CTRL_PLL_MODE_AUTO PLL_VIDEO_CTRL_PLL_MODE

#define	PLL_VIDEO_CTRL_PLL_MODE_MANUAL 0

#define	PLL_VIDEO_CTRL_LOCK (1UL << 28)

#define	PLL_VIDEO_CTRL_FRAC_CLK_OUT (1UL << 25)

#define	PLL_VIDEO_CTRL_PLL_MODE_SEL (1UL << 24)

#define	PLL_VIDEO_CTRL_PLL_MODE_INTEGER PLL_VIDEO_CTRL_PLL_MODE_SEL

#define	PLL_VIDEO_CTRL_PLL_MODE_FRACTIONAL 0

#define	PLL_VIDEO_CTRL_PLL_SDM_EN (1UL << 20)

#define	__PLL_VIDEO_CTRL_PLL_FACTOR_N(__N)

#define	__PLL_VIDEO_CTRL_PLL_PREDIV_M(__M)

#define	PLL_VIDEO_CTRL_PLL_FACTOR_N(...)

#define	PLL_VIDEO_CTRL_PLL_PREDIV_M(...)

#define	CCU_PLL_VE_CTRL 0x018

#define	PLL_VE_CTRL_PLL_ENABLE (1UL << 31)

#define	PLL_VE_CTRL_LOCK (1UL << 28)

#define	PLL_VE_CTRL_FRAC_CLK_OUT (1UL << 25)

#define	PLL_VE_CTRL_PLL_MODE_SEL (1UL << 24)

#define	PLL_VE_CTRL_PLL_MODE_FRACTIONAL (0UL << 24)

#define	PLL_VE_CTRL_PLL_MODE_INTEGER (1UL << 24)

#define	__PLL_VE_CTRL_PLL_FACTOR_N(__N)

#define	__PLL_VE_CTRL_PLL_PREDIV_M(__M)

#define	PLL_VE_CTRL_PLL_FACTOR_N(...)

#define	PLL_VE_CTRL_PLL_PREDIV_M(...)

#define	CCU_PLL_DDR_CTRL 0x020

#define	PLL_DDR_CTRL_PLL_ENABLE (1UL << 31)

#define	PLL_DDR_CTRL_LOCK (1UL << 28)

#define	PLL_DDR_CTRL_SDRAM_SIGMA_DELTA_EN (1UL << 24)

#define	PLL_DDR_CTRL_PLL_DDR_CFG_UPDATE (1UL << 20)

#define	__PLL_DDR_CTRL_PLL_FACTOR_N(__N)

#define	__PLL_DDR_CTRL_PLL_FACTOR_K(__K)

#define	__PLL_DDR_CTRL_PLL_FACTOR_M(__M)

#define	PLL_DDR_CTRL_PLL_FACTOR_N(...)

#define	PLL_DDR_CTRL_PLL_FACTOR_K(...)

#define	PLL_DDR_CTRL_PLL_FACTOR_M(...)

#define	CCU_PLL_PERIPH_CTRL 0x028

#define	PLL_PERIPH_CTRL_PLL_ENABLE (1UL << 31)

#define	PLL_PERIPH_CTRL_LOCK (1UL << 28)

#define	PLL_PERIPH_CTRL_PLL_24M_OUT_EN (1UL << 18)

#define	__PLL_PERIPH_CTRL_PLL_FACTOR_N(__N)

#define	__PLL_PERIPH_CTRL_PLL_FACTOR_K(__K)

#define	PLL_PERIPH_CTRL_PLL_FACTOR_N(...)

#define	PLL_PERIPH_CTRL_PLL_FACTOR_K(...)

#define	CCU_CPU_CLK_SRC 0x050

#define	CPU_CLK_SRC_SEL (3UL << 16)

#define	CPU_CLK_SRC_SEL_LOSC (0UL << 16)

#define	CPU_CLK_SRC_SEL_OSC24M (1UL << 16)

#define	CPU_CLK_SRC_SEL_PLL_CPU (2UL << 16)

#define	CCU_AHB_APB_HCLKC_CFG 0x054

#define	__AHB_APB_HCLKC_CFG_HCLKC_DIV(__DIV)

#define	AHB_APB_HCLKC_CFG_HCLKC_DIV(...)

#define	AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL (3UL << 12)

#define	AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_LOSC (0UL << 12)

#define	AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_OSC24M (1UL << 12)

#define	AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_CPUCLK (2UL << 12)

#define	AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_PERIPH (3UL << 12)

#define	__AHB_APB_HCLKC_CFG_APB_CLK_RATIO(__R)

#define	__AHB_APB_HCLKC_CFG_AHB_PRE_DIV(__DIV)

#define	__AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO(__R)

#define	AHB_APB_HCLKC_CFG_APB_CLK_RATIO(...)

#define	AHB_APB_HCLKC_CFG_AHB_PRE_DIV(...)

#define	AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO(...)

#define	CCU_BUS_CLK_GATINT0 0x060

#define	BUS_CLK_GATING0_USB_OTG_GATING (1UL << 24)

#define	BUS_CLK_GATING0_SPI1_GATING (1UL << 21)

#define	BUS_CLK_GATING0_SPI0_GATING (1UL << 20)

#define	BUS_CLK_GATING0_SDRAM_GATING (1UL << 14)

#define	BUS_CLK_GATING0_SD1_GATING (1UL << 9)

#define	BUS_CLK_GATING0_SD0_GATING (1UL << 8)

#define	BUS_CLK_GATING0_DMA_GATING (1UL << 6)

#define	CCU_BUS_CLK_GATE1 0x064

#define	BUS_CLK_GATING1_DEFE_GATING (1UL << 14)

#define	BUS_CLK_GATING1_DEBE_GATING (1UL << 12)

#define	BUS_CLK_GATING1_TVE_GATING (1UL << 10)

#define	BUS_CLK_GATING1_TBD_GATING (1UL << 9)

#define	BUS_CLK_GATING1_CSI_GATING (1UL << 8)

#define	BUS_CLK_GATING1_DEINTERLACE_GATING (1UL << 5)

#define	BUS_CLK_GATING1_LCD_GATING (1UL << 4)

#define	BUS_CLK_GATING1_VE_GATING (1UL << 0)

#define	CCU_BUS_CLK_GATE2 0x068

#define	BUS_CLK_GATING2_UART2_GATING (1UL << 22)

#define	BUS_CLK_GATING2_UART1_GATING (1UL << 21)

#define	BUS_CLK_GATING2_UART0_GATING (1UL << 20)

#define	BUS_CLK_GATING2_TWI2_GATING (1UL << 18)

#define	BUS_CLK_GATING2_TWI1_GATING (1UL << 17)

#define	BUS_CLK_GATING2_TWI0_GATING (1UL << 16)

#define	BUS_CLK_GATING2_RSB_GATING (1UL << 3)

#define	BUS_CLK_GATING2_CIR_GATING (1UL << 2)

#define	BUS_CLK_GATING2_OWA_GATING (1UL << 1)

#define	BUS_CLK_GATING2_AUDIO_CODEC_GATING (1UL << 0)

#define	CCU_SDMMC0_CLK 0x088

#define	SDMMC0_CLK_SCLK_GATING (1UL << 31)

#define	SDMMC0_CLK_CLK_SRC_SEL (3UL << 24)

#define	SDMMC0_CLK_CLK_SRC_SEL_OSC24M (0UL << 24)

#define	SDMMC0_CLK_CLK_SRC_SEL_PLL_PERIPH (1UL << 24)

#define	__SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR(__DLY)

#define	__SDMMC0_CLK_CLK_DIV_RATIO_N(__N)

#define	__SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR(__DLY)

#define	__SDMMC0_CLK_CLK_DIV_RATIO_M(__M)

#define	SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR(...)

#define	SDMMC0_CLK_CLK_DIV_RATIO_N(...)

#define	SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR(...)

#define	SDMMC0_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_SDMMC1_CLK 0x08c

#define	SDMMC1_CLK_SCLK_GATING (1UL << 31)

#define	SDMMC1_CLK_CLK_SRC_SEL (3UL << 24)

#define	SDMMC1_CLK_CLK_SRC_SEL_OSC24M (0UL << 24)

#define	SDMMC1_CLK_CLK_SRC_SEL_PLL_PERIPH (1UL << 24)

#define	__SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR(__DLY)

#define	__SDMMC1_CLK_CLK_DIV_RATIO_N(__N)

#define	__SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR(__DLY)

#define	__SDMMC1_CLK_CLK_DIV_RATIO_M(__M)

#define	SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR(...)

#define	SDMMC1_CLK_CLK_DIV_RATIO_N(...)

#define	SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR(...)

#define	SDMMC1_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_DAUDIO_CLK 0x0b0

#define	DAUDIO_CLK_SCLK_GATING (1UL << 31)

#define	DAUTIO_CLK_CLK_SRC_SEL (3UL << 16)

#define	DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8X (0UL << 16)

#define	DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD2 (1UL << 16)

#define	DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD4 (2UL << 16)

#define	DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD8 (3UL << 16)

#define	CCU_OWA_CLK 0x0b4

#define	OWA_CLK_SCLK_GATING (1UL << 31)

#define	OWA_CLK_CLK_SRC_SEL (3UL << 16)

#define	OWA_CLK_CLK_SRC_SEL_PLL2 (0UL << 16)

#define	OWA_CLK_CLK_SRC_SEL_PLL2D2 (1UL << 16)

#define	OWA_CLK_CLK_SRC_SEL_PLL2D4 (2UL << 16)

#define	OWA_CLK_CLK_SRC_SEL_PLL2D8 (3UL << 16)

#define	CCU_CIR_CLK 0x0b8

#define	CIR_CLK_SCLK_GATING (1UL << 31)

#define	CIR_CLK_CLK_SRC_SEL (3UL << 24)

#define	CIR_CLK_CLK_SRC_SEL_LOSC (0UL << 24)

#define	CIR_CLK_CLK_SRC_SEL_OSC24M (1UL << 24)

#define	__CIR_CLK_CLK_DIV_RATION_N(__N)

#define	__CIR_CLK_CLK_DIV_RATION_M(__M)

#define	CIR_CLK_CLK_DIV_RATION_N(...)

#define	CIR_CLK_CLK_DIV_RATION_M(...)

#define	CCU_USBPHY_CLK 0x0cc

#define	USBPHY_CLK_SCLK_GATING (1UL << 1)

#define	USBPHY_CLK_USBPHY_RST (1UL << 0)

#define	CCU_DRAM_GATING 0x100

#define	DRAM_GATING_BE_DCLK_GATING (1UL << 26)

#define	DRAM_GATING_FE_DCLK_GATING (1UL << 24)

#define	DRAM_GATING_TVD_DCLK_GATING (1UL << 3)

#define	DRAM_GATING_DEINTERLACE_DCLK_GATING (1UL << 2)

#define	DRAM_GATING_CSI_DCLK_GATING (1UL << 1)

#define	DRAM_GATING_VE_DCLK_GATING (1UL << 0)

#define	CCU_BE_CLK 0x104

#define	BE_CLK_SCLK_GATING (1UL << 31)

#define	BE_CLK_CLK_SRC_SEL (3UL << 24)

#define	BE_CLK_CLK_SRC_SEL_PLL_VIDEO (0UL << 24)

#define	BE_CLK_CLK_SRC_SEL_PLL_PERIPH (2UL << 24)

#define	__BE_CLK_CLK_DIV_RATIO_M(__M)

#define	BE_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_FE_CLK 0x10c

#define	FE_CLK_SCLK_GATING (1UL << 31)

#define	FE_CLK_CLK_SRC_SEL (3UL << 24)

#define	FE_CLK_CLK_SRC_SEL_PLL_VIDEO (0UL << 24)

#define	FE_CLK_CLK_SRC_SEL_PLL_PERIPH (2UL << 24)

#define	__FE_CLK_CLK_DIV_RATIO_M(__M)

#define	FE_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_TCON_CLK 0x118

#define	TCON_CLK_SCLK_GATING (1UL << 31)

#define	TCON_CLK_CLK_SRC_SEL (7UL << 24)

#define	TCON_CLK_CLK_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

#define	TCON_CLK_CLK_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

#define	CCU_DI_CLK 0x11c

#define	DI_CLK_SCLK_GATING (1UL << 31)

#define	DI_CLK_CLK_SRC_SEL (7UL << 24)

#define	DI_CLK_CLK_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

#define	DI_CLK_CLK_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

#define	__DI_CLK_CLK_DIV_RATIO_M(__M)

#define	DI_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_TVE_CLK 0x120

#define	TVE_CLK_SCLK2_GATING (1UL << 31)

#define	TVE_CLK_SCLK2_SRC_SEL (7UL << 24)

#define	TVE_CLK_SCLK2_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

#define	TVE_CLK_SCLK2_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

#define	TVE_CLK_SCLK1_GATING (1UL << 15)

#define	TVE_CLK_SCLK1_SRC_SEL (1UL << 8)

#define	TVE_CLK_SCLK1_SRC_SEL_TVE_SCLK2 (0UL << 8)

#define	TVE_CLK_SCLK1_SRC_SEL_TVE_SCLK2_D2 (1UL << 8)

#define	__TVE_CLK_CLK_DIV_RATIO_M(__M)

#define	TVE_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_TVD_CLK 0x124

#define	TVD_CLK_SCLK_GATING (1UL << 31)

#define	TVD_CLK_CLK_SRC_SEL (7UL << 24)

#define	TVD_CLK_CLK_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

#define	TVD_CLK_CLK_SRC_SEL_OSC24M (1UL << 24)

#define	TVD_CLK_CLK_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

#define	__TVD_CLK_CLK_DIV_RATIO_M(__M)

#define	TVD_CLK_CLK_DIV_RATIO_M(...)

#define	CCU_CSI_CLK 0x134

#define	CSI_CLK_CSI_MCLK_GATING (1UL << 15)

#define	CSI_CLK_MCLK_SRC_SEL (7UL << 8)

#define	CSI_CLK_MCLK_SRC_SEL_PLL_VIDEO_1X (0UL << 8)

#define	CSI_CLK_MCLK_SRC_SEL_OSC24M (5UL << 8)

#define	__CSI_CLK_CLSI_MCLK_DIV_M(__M)

#define	CSI_CLK_CLSI_MCLK_DIV_M(...)

#define	CCU_VE_CLK 0x13c

#define	VE_CLK_SCLK_GATING (1UL << 31)

#define	CCU_AUDIO_CODEC_CLK 0x140

#define	AUDIO_CODEC_CLK_SCLK_GATING (1UL << 31)

#define	CCU_AVS_CLK 0x144

#define	AVS_CLK_SCLK_GATING (1UL << 31)

#define	CCU_PLL_STABLE_TIME0 0x200

#define	__PLL_STABLE_TIME0_PLL_LOCK_TIME(__T)

#define	PLL_STABLE_TIME0_PLL_LOCK_TIME(...)

#define	CCU_PLL_STABLE_TIME1 0x204

#define	__PLL_STABLE_TIME1_PLL_LOCK_TIME(__T)

#define	PLL_STABLE_TIME1_PLL_LOCK_TIME(...)

#define	CCU_PLL_CPU_BIAS 0x220

#define	CCU_PLL_AUDIO_BIAS 0x224

#define	CCU_PLL_VIDEO_BIAS 0x228

#define	CCU_PLL_VE_BIAS 0x22c

#define	CCU_PLL_DDR0_BIAS 0x230

#define	CCU_PLL_PERIPH_BIAS 0x234

#define	CCU_PLL_CPU_TUN 0x250

#define	CCU_PLL_DDR_TUN 0x260

#define	CCU_PLL_AUDIO_PAT_CTRL 0x284

#define	CCU_PLL_VIDEO_PAT_CTRL 0x288

#define	CCU_PLL_DDR_PAT_CTRL 0x290

#define	CCU_BUS_SOFT_RST0 0x2c0

#define	BUS_SOFT_RST0_USBOTG_RST (1UL << 24)

#define	BUS_SOFT_RST0_SPI1_RST (1UL << 21)

#define	BUS_SOFT_RST0_SPI0_RST (1UL << 20)

#define	BUS_SOFT_RST0_SDRAM_RST (1UL << 14)

#define	BUS_SOFT_RST0_SD1_RST (1UL << 9)

#define	BUS_SOFT_RST0_SD0_RST (1UL << 8)

#define	BUS_SOFT_RST0_DMA_RST (1UL << 6)

#define	CCU_BUS_SOFT_RST1 0x2c4

#define	BUS_SOFT_RST1_DEFE_RST (1UL << 14)

#define	BUS_SOFT_RST1_DEBE_RST (1UL << 12)

#define	BUS_SOFT_RST1_TVE_RST (1UL << 10)

#define	BUS_SOFT_RST1_RVD_RST (1UL << 9)

#define	BUS_SOFT_RST1_CSI_RST (1UL << 8)

#define	BUS_SOFT_RST1_DEINTERLACE_RST (1UL << 5)

#define	BUS_SOFT_RST1_LCD_RST (1UL << 4)

#define	BUS_SOFT_RST1_VE_RST (1UL << 0)

#define	CCU_BUS_SOFT_RST2 0x2d0

#define	BUS_SOFT_RST2_UART2_RST (1UL << 22)

#define	BUS_SOFT_RST2_UART1_RST (1UL << 21)

#define	BUS_SOFT_RST2_UART0_RST (1UL << 20)

#define	BUS_SOFT_RST2_TWI2_RST (1UL << 18)

#define	BUS_SOFT_RST2_TWI1_RST (1UL << 17)

#define	BUS_SOFT_RST2_TWI0_RST (1UL << 16)

#define	BUS_SOFT_RST2_DAUDIO_RST (1UL << 12)

#define	BUS_SOFT_RST2_RSB_RST (1UL << 3)

#define	BUS_SOFT_RST2_CIR_RST (1UL << 2)

#define	BUS_SOFT_RST2_OWA_RST (1UL << 1)

#define	BUS_SOFT_RST2_AUDIO_CODEC_RST (1UL << 0)

#define	DRAM_BASE ((dram_reg_t *)0x01c01000)

#define	DRAM_SCONR 0x000

#define	DRAM_STMG0R 0x004

#define	DRAM_STMG1R 0x008

#define	DRAM_SCTLR 0x00c

#define	DRAM_SREFR 0x010

#define	DRAM_SEXTMR 0x014

#define	DRAM_DDLYR 0x024

#define	DRAM_DADRR 0x028

#define	DRAM_DVALR 0x02c

#define	DRAM_DRPTR0 0x030

#define	DRAM_DRPTR1 0x034

#define	DRAM_DRPTR2 0x038

#define	DRAM_DRPTR3 0x03c

#define	DRAM_SEFR 0x040

#define	DRAM_MAE 0x044

#define	DRAM_ASPR 0x048

#define	DRAM_SDLY0 0x04C

#define	DRAM_SDLY1 0x050

#define	DRAM_SDLY2 0x054

#define	DRAM_MCR0 0x100

#define	DRAM_MCR1 0x104

#define	DRAM_MCR2 0x108

#define	DRAM_MCR3 0x10c

#define	DRAM_MCR4 0x110

#define	DRAM_MCR5 0x114

#define	DRAM_MCR6 0x118

#define	DRAM_MCR7 0x11c

#define	DRAM_MCR8 0x120

#define	DRAM_MCR9 0x124

#define	DRAM_MCR10 0x128

#define	DRAM_MCR11 0x12c

#define	DRAM_BWCR 0x140

#define	PIO_BASE ((pio_reg_t *)0x01c20800)

#define	UART0_BASE ((uart_reg_t *)0x01c25000)

#define	UART1_BASE ((uart_reg_t *)0x01c25400)

#define	UART2_BASE ((uart_reg_t *)0x01c25800)

#define	UART_RBR 0x000

#define	UART_THR 0x000

#define	UART_DLL 0x000

#define	UART_DLH 0x004

#define	UART_IER 0x004

#define	IER_PTIME (1UL << 7)

#define	IER_EDSSI (1UL << 3)

#define	IER_ELSI (1UL << 2)

#define	IER_ETBEI (1UL << 1)

#define	IER_ERBFI (1UL << 0)

#define	UART_IIR 0x008

#define	UART_FCR 0x008

#define	FCR_RT (3UL << 6)

#define	FCR_RT_1 (0UL << 6)

#define	FCR_RT_QUARTER (1UL << 6)

#define	FCR_RT_HALF (2UL << 6)

#define	FCR_RT_2_LESS (3UL << 6)

#define	FCR_TFT (3UL << 4)

#define	FCR_TFT_EMPTY (0UL << 4)

#define	FCR_TFT_2 (1UL << 4)

#define	FCR_TFT_QUARTER (2UL << 4)

#define	FCR_TFT_HALF (3UL << 4)

#define	FCR_DMAM (1UL << 3)

#define	FCR_XFIFOR (1UL << 2)

#define	FCR_RFIFOR (1UL << 1)

#define	FCR_FIFOE (1UL << 0)

#define	UART_LCR 0x00c

#define	LCR_DLAB (1UL << 7)

#define	LCR_BC (1UL << 6)

#define	LCR_EPS (3UL << 4)

#define	LCR_EPS_ODD (0UL << 4)

#define	LCR_EPS_EVEN (1UL << 4)

#define	LCR_PEN (1UL << 3)

#define	LCR_STOP (1UL << 2)

#define	LCR_STOP_1 (0UL << 2)

#define	LCR_STOP_2 (1UL << 2)

#define	LCR_DLS (3UL << 0)

#define	LCR_DLS_5 (0UL << 0)

#define	LCR_DLS_6 (1UL << 0)

#define	LCR_DLS_7 (2UL << 0)

#define	LCR_DLS_8 (3UL << 0)

#define	UART_MCR 0x010

#define	MCR_SIRE (1UL << 6)

#define	MCR_AFCE (1UL << 5)

#define	MCR_LOOP (1UL << 4)

#define	MCR_RTS (1UL << 1)

#define	MCR_DTR (1UL << 0)

#define	UART_LSR 0x014

#define	UART_MSR 0x018

#define	UART_SCH 0x01c

#define	UART_USR 0x07c

#define	USR_RFF (1UL << 4)

#define	USR_RFNE (1UL << 3)

#define	USR_TFE (1UL << 2)

#define	USR_TFNF (1UL << 1)

#define	USR_BUSY (1UL << 0)

#define	UART_TFL 0x080

#define	UART_RFL 0x084

#define	UART_HALT 0x0a4

#define	SPI0_BASE ((spi_reg_t *)0x01c05000)

#define	SPI1_BASE ((spi_reg_t *)0x01c06000)

#define	SPI_GCR 0x004

#define	GCR_EN (1UL << 0)

#define	GCR_MODE (1UL << 1)

#define	GCR_MODE_MASTE (1UL << 1)

#define	GCR_MODE_SLAVE (0UL << 1)

#define	GCR_TP_EN (1UL << 7)

#define	GCR_SRST (1UL << 31)

#define	SPI_TCR 0x008

#define	__TCR_CPHA(__CPHA)

#define	__TCR_CPOL(__CPOL)

#define	__TCR_SPOL(__SPOL)

#define	TCR_CPHA(...)

#define	TCR_CPOL(...)

#define	TCR_SPOL(...)

#define	TCR_SSCTL (1UL << 3)

#define	__TCR_SS_SEL(__SEL)

#define	TCR_SS_SEL(...)

#define	TCR_SS_OWNER (1UL << 6)

#define	TCR_SS_OWNER_SPI (0UL << 6)

#define	TCR_SS_OWNER_SOFTWARE (1UL << 6)

#define	__TCR_SS_LEVEL(__LVL)

#define	TCR_SS_LEVEL(...)

#define	TCR_DHB (1UL << 8)

#define	TCR_DDB (1UL << 9)

#define	TCR_RPSM (1UL << 10)

#define	TCR_RPSM_NORMAL (0UL << 10)

#define	TCR_RPSM_RAPID (1UL << 10)

#define	TCR_SDC (1UL << 11)

#define	TCR_FBS (1UL << 12)

#define	TCR_FBS_MSB_FIRST (0UL << 12)

#define	TCR_FBS_LSB_FIRST (1UL << 12)

#define	TCR_SDM (1UL << 13)

#define	TCR_XCH (1UL << 31)

#define	SPI_IER 0x010

#define	SPI_ISR 0x014

#define	SPI_FCR 0x018

#define	FCR_RX_TRIG_LEVEL(__LVL)

#define	FCR_RF_DRQ_EN (1UL << 8)

#define	FCR_RX_DMA_MODE (1UL << 9)

#define	FCR_RX_DMA_MODE_NORMAL (0UL << 9)

#define	FCR_RX_DMA_MODE_DEDICATE (1UL << 9)

#define	FCR_RX_FIFO_ACCESS_SIZE (3UL << 10)

#define	FCR_RX_FIFO_ACCESS_SIZE_BYTE (0UL << 10)

#define	FCR_RX_FIFO_ACCESS_SIZE_WORD (1UL << 10)

#define	FCR_RX_FIFO_ACCESS_SIZE_BY_BUS (3UL << 10)

#define	FCR_RF_TEST (1UL << 14)

#define	FCR_RF_RST (1UL << 15)

#define	FCR_TX_TRIG_LEVEL(__LVL)

#define	FCR_TX_FIFO_ACCESS_SIZE (3UL << 26)

#define	FCR_TX_FIFO_ACCESS_SIZE_BYTE (0UL << 26)

#define	FCR_TX_FIFO_ACCESS_SIZE_WORD (1UL << 26)

#define	FCR_TX_FIFO_ACCESS_SIZE_BY_BUS (3UL << 26)

#define	FCR_TF_TEST (1UL << 30)

#define	FCR_TF_RST (1UL << 31)

#define	SPI_FSR 0x01c

#define	SPI_WCR 0x020

#define	SPI_CCR 0x024

#define	CCR_CDR2(__N)

#define	CCR_CDR1(_N)

#define	CCR_DRS (1UL << 12)

#define	CCR_DRS_CDR1 (0UL << 12)

#define	CCR_DRS_CDR2 (1UL << 12)

#define	SPI_MBC 0x030

#define	SPI_MTC 0x034

#define	SPI_BCC 0x038

#define	SPI_TXD 0x200

#define	SPI_RXD 0x300

#define	TCON_BASE ((tcon_reg_t *)0x01C0C000)

#define	TCON_CTRL 0x000

#define	TCON_CTRL_MODULE_EN (1UL << 31)

#define	TCON_CTRL_IO_MAP_SEL (1UL << 0)

#define	TCON_CTRL_IO_MAP_SEL_TCON0 (0UL << 0)

#define	TCON_CTRL_IO_MAP_SEL_TCON1 (1UL << 0)

#define	TCON_INT_REG0 0x004

#define	TCON_INT_REG1 0x008

#define	TCON_FRM_CTRL 0x010

#define	TCON_FRM_CTRL_TCON0_FRM_EN (1UL << 31)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_R (1UL << 6)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_R6 (0UL << 6)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_R5 (1UL << 6)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_G (1UL << 5)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_G6 (0UL << 5)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_G5 (1UL << 5)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_B (1UL << 4)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_B6 (0UL << 4)

#define	TCON_FRM_CTRL_TCON0_FRM_MODE_B5 (1UL << 4)

#define	TCON_FRM_SEED0_R 0x014

#define	TCON_FRM_SEED0_G 0x018

#define	TCON_FRM_SEED0_B 0x01c

#define	TCON_FRM_SEED1_R 0x020

#define	TCON_FRM_SEED1_G 0x024

#define	TCON_FRM_SEED1_B 0x028

#define	TCON_FRM_TBL0 0x02c

#define	TCON_FRM_TBL1 0x030

#define	TCON_FRM_TBL2 0x034

#define	TCON_FRM_TBL3 0x038

#define	TCON0_CTRL 0x040

#define	TCON0_CTRL_EN (1UL << 31)

#define	TCON0_CTRL_IF (3UL << 24)

#define	TCON0_CTRL_IF_HV (0UL << 24)

#define	TCON0_CTRL_IF_8080 (1UL << 24)

#define	TCON0_CTRL_RBG_GBR (1UL << 23)

#define	__TCON0_CTRL_STA_DLY(__DLY)

#define	TCON0_CTRL_STA_DLY(...)

#define	TCON0_CLK_CTRL 0x044

#define	TCON0_CLK_CTRL_LCKL_EN (0xFUL << 28)

#define	__TCON0_CLK_CTRL_DCLKDIV(__DIV)

#define	TCON0_CLK_CTRL_DCLKDIV(...)

#define	TCON0_BASIC_TIMING0 0x048

#define	TCON0_BASIC_TIMING1 0x04c

#define	TCON0_BASIC_TIMING2 0x050

#define	TCON0_BASIC_TIMING3 0x054

#define	TCON0_HV_TIMING 0x058

#define	TCON0_CPU_IF 0x060

#define	TCON0_CPU_WR 0x064

#define	TCON0_CPU_RD 0x068

#define	TCON0_CPU_RD_NX 0x06c

#define	TCON0_IO_CTRL0 0x088

#define	TCON0_IO_CTRL0_DCLK_SEL (3UL << 28)

#define	TCON0_IO_CTRL0_DCLK_SEL_DCLK0 (0UL << 28)

#define	TCON0_IO_CTRL0_DCLK_SEL_DCLK1 (1UL << 28)

#define	TCON0_IO_CTRL0_DCLK_SEL_DCLK2 (2UL << 28)

#define	TCON0_IO_CTRL0_IO3_INV (1UL << 27)

#define	TCON0_IO_CTRL0_IO2_INV (1UL << 26)

#define	TCON0_IO_CTRL0_IO1_INV (1UL << 25)

#define	TCON0_IO_CTRL0_IO0_INV (1UL << 24)

#define	TCON0_IO_CTRL1 0x08c

#define	TCON1_CTRL 0x090

#define	TCON1_CTRL_EN (1UL << 31)

#define	TCON1_BASIC0 0x094

#define	TCON1_BASIC1 0x098

#define	TCON1_BASIC2 0x09c

#define	TCON1_BASIC3 0x0a0

#define	TCON1_BASIC4 0x0a4

#define	TCON1_BASIC5 0x0a8

#define	TCON1_IO_CTRL0 0x0f0

#define	TCON1_IO_CTRL1 0x0f4

#define	TCON_DEBUG_INFO 0x0fc

#define	DEBE_BASE ((debe_reg_t *)0x01E60000)

#define	DEBE_MODE_CTRL 0x800

#define	DEBE_MODE_CTRL_LAYER_EN(__LAYER)

#define	DEBE_MODE_CTRL_CHANNEL_START (1UL << 1)

#define	DEBE_MODE_CTRL_DEBE_EN (1UL << 0)

#define	DEBE_BACKCOLOR 0x804

#define	DEBE_DISP_SIZE 0x808

#define	DEBE_DISP_SIZE_WIDTH(__W)

#define	DEBE_DISP_SIZE_HEIGHT(__H)

#define	DEBE_LAY0_SIZE 0x810

#define	DEBE_LAY1_SIZE 0x814

#define	DEBE_LAY2_SIZE 0x818

#define	DEBE_LAY3_SIZE 0x81c

#define	DEBE_LAY_SIZE_WIDTH(__W)

#define	DEBE_LAY_SIZE_HEIGHT(__H)

#define	DEBE_LAY0_CODNT 0x820

#define	DEBE_LAY1_CODNT 0x824

#define	DEBE_LAY2_CODNT 0x828

#define	DEBE_LAY3_CODNT 0x82c

#define	DEBE_LAY_CODNT_X(__X)

#define	DEBE_LAY_CODNT_Y(__Y)

#define	DEBE_LAY0_LINEWIDTH 0x840

#define	DEBE_LAY1_LINEWIDTH 0x844

#define	DEBE_LAY2_LINEWIDTH 0x848

#define	DEBE_LAY3_LINEWIDTH 0x84c

#define	DEBE_LAY_LINEWIDTH_BIT(__W)

#define	DEBE_LAY_LINEWIDTH_BYTE(__W)

#define	DEBE_LAY_LINEWIDTH_HWORD(__W)

#define	DEBE_LAY_LINEWIDTH_WORD(__W)

#define	DEBE_LAY0_FB_ADDR0 0x850

#define	DEBE_LAY1_FB_ADDR0 0x854

#define	DEBE_LAY2_FB_ADDR0 0x858

#define	DEBE_LAY3_FB_ADDR0 0x85c

#define	DEBE_LAY0_FB_ADDR1 0x860

#define	DEBE_LAY1_FB_ADDR1 0x864

#define	DEBE_LAY2_FB_ADDR1 0x868

#define	DEBE_LAY3_FB_ADDR1 0x86c

#define	DEBE_REGBUFF_CTRL 0x870

#define	DEBE_REGBUFF_CTRL_DIABLE_AUTO_RELOAD (1UL << 1)

#define	DEBE_REGBUFF_CTRL_RELOAD (1UL << 0)

#define	DEBE_CK_MAX 0x880

#define	DEBE_CK_MIN 0x884

#define	DEBE_CK_CFG 0x888

#define	DEBE_LAY0_ATT_CTRL0 0x890

#define	DEBE_LAY1_ATT_CTRL0 0x894

#define	DEBE_LAY2_ATT_CTRL0 0x898

#define	DEBE_LAY3_ATT_CTRL0 0x89c

#define	DEBE_LAY0_ATT_CTRL1 0x8a0

#define	DEBE_LAY1_ATT_CTRL1 0x8a4

#define	DEBE_LAY2_ATT_CTRL1 0x8a8

#define	DEBE_LAY3_ATT_CTRL1 0x8ac

#define	DEBE_HWC_CTRL 0x8d8

#define	DEBE_HWCFB_CTRL 0x8e0

#define	DEBE_WB_CTRL 0x8f0

#define	DEBE_WB_ADDR 0x8f4

#define	DEBE_WB_LW 0x8f8

#define	DEBE_IYUV_CH_CTRL 0x920

#define	DEBE_CH0_YUV_FB_ADDR 0x930

#define	DEBE_CH1_YUV_FB_ADDR 0x934

#define	DEBE_CH2_YUV_FB_ADDR 0x938

#define	DEBE_CH0_YUV_BLW 0x940

#define	DEBE_CH1_YUV_BLW 0x944

#define	DEBE_CH2_YUV_BLW 0x948

#define	DEBE_COEF00 0x950

#define	DEBE_COEF01 0x954

#define	DEBE_COEF02 0x958

#define	DEBE_COEF03 0x95c

#define	DEBE_COEF10 0x960

#define	DEBE_COEF11 0x964

#define	DEBE_COEF12 0x968

#define	DEBE_COEF13 0x96c

#define	DEBE_COEF20 0x970

#define	DEBE_COEF21 0x974

#define	DEBE_COEF22 0x978

#define	DEBE_COEF23 0x97c

#define	TVE_BASE ((tve_reg_t *)0x01c0a000)

#define	TVE_ENABLE 0x000

#define	__TVE_ENABLE_DAC_MAP(__DAC, __OUT)

#define	TVE_ENABLE_DAC_MAP(__DAC, ...)

#define	TVE_ENABLE_EN (1UL << 0)

#define	TVE_CFG0 0x004

#define	TVE_CFG0_YC_EN (1UL << 17)

#define	TVE_CFG0_CVBS_EN (1UL << 16)

#define	TVE_CFG0_TVMODE_SELECT(...)

#define	TVE_DAC1 0x008

#define	TVE_DAC1_CLOCK_INVERT (1UL << 24)

#define	TVE_DAC1_DAC_EN(__DAC)

#define	TVE_NOTCH 0x00c

#define	TVE_CHROMA_FREQUENCY 0x010

#define	TVE_PORCH 0x014

#define	TVE_LINE 0x01c

#define	TVE_LEVEL 0x020

#define	TVE_DAC2 0x024

#define	TVE_DETECT_STATUS 0x038

#define	TVE_CBCR_LEVEL 0x10c

#define	TVE_BURST_WIDTH 0x114

#define	TVE_CBCR_GAIN 0x118

#define	TVE_SYNC_VBI 0x11c

#define	TVE_ACTIVE_LINE 0x124

#define	TVE_CHROMA 0x128

#define	TVE_ENCODER 0x12c

#define	TVE_RESYNC 0x130

#define	TVE_SLAVE 0x134

#define	TIMER_BASE ((timer_reg_t *)0x01c20c00)

#define	TMR_IRQ_EN 0x000

#define	TMR_IRQ_STA 0x004

#define	TMR0_CTRL 0x010

#define	TMR0_INTV_VALUE 0x014

#define	TMR0_CUR_VALUE 0x018

#define	TMR1_CTRL 0x020

#define	TMR1_INTV_VALUE 0x024

#define	TMR1_CUR_VALUE 0x028

#define	TMR2_CTRL 0x030

#define	TMR2_INTV_VALUE 0x034

#define	TMR2_CUR_VALUE 0x038

#define	TMR_CTRL_MODE (1UL << 7)

#define	TMR_CTRL_MODE_CONTINUOUS (0UL << 7)

#define	TMR_CTRL_MODE_SINGLE (1UL << 7)

#define	TMR_CTRL_CLK_SRC (3UL << 2)

#define	TMR_CTRL_CLK_SRC_LOSC (0UL << 2)

#define	TMR_CTRL_CLK_SRC_OSC24M (1UL << 2)

#define	TMR_CTRL_RELOAD (1UL << 1)

#define	TMR_CTRL_EN (1UL << 0)

#define	AVS_CNT_CTL 0x080

#define	AVS_CNT0 0x084

#define	AVS_CNT1 0x088

#define	AVS_CNT_DIV 0x08c

#define	WDOG_IRQ_EN 0x0a0

#define	WDOG_IRQ_STA 0x0a4

#define	WDOG_CTRL 0x0b0

#define	WDOG_CFG 0x0b4

#define	WDOG_MODE 0x0b8

#define	MUSB_BASE ((musb_reg_t *)0x01c13000)

#define	MUSB_FAddr 0x0098

#define	MUSB_Power 0x0040

#define	MUSBD_Power_ISOUpdate (1UL << 7)

#define	MUSBD_Power_SoftConn (1UL << 6)

#define	MUSBD_Power_HSEnab (1UL << 5)

#define	MUSB_Power_HSMode (1UL << 4)

#define	MUSB_Power_Reset (1UL << 3)

#define	MUSB_Power_Resume (1UL << 2)

#define	MUSB_Power_SuspendMode (1UL << 1)

#define	MUSB_Power_EnableSuspendM (1UL << 0)

#define	MUSB_IntrTx 0x0044

#define	MUSB_IntrRx 0x0046

#define	MUSB_IntrTxE 0x0048

#define	MUSB_IntrRxE 0x004a

#define	MUSB_IntrUSB 0x004c

#define	MUSBD_IntrUSB_VBusError (1UL << 7)

#define	MUSB_IntrUSB_SessReq (1UL << 6)

#define	MUSB_IntrUSB_Discon (1UL << 5)

#define	MUSBH_IntrUSB_Conn (1UL << 4)

#define	MUSB_IntrUSB_SOF (1UL << 3)

#define	MUSBD_IntrUSB_Reset (1UL << 2)

#define	MUSBH_IntrUSB_Babble (1UL << 2)

#define	MUSB_IntrUSB_Resume (1UL << 1)

#define	MUSBD_IntrUSB_Suspend (1UL << 0)

#define	MUSB_IntrUSBE 0x0050

#define	MUSBD_IntrUSBE_VBusError (1UL << 7)

#define	MUSB_IntrUSBE_SessReq (1UL << 6)

#define	MUSB_IntrUSBE_Discon (1UL << 5)

#define	MUSBH_IntrUSBE_Conn (1UL << 4)

#define	MUSB_IntrUSBE_SOF (1UL << 3)

#define	MUSBD_IntrUSBE_Reset (1UL << 2)

#define	MUSBH_IntrUSBE_Babble (1UL << 2)

#define	MUSB_IntrUSBE_Resume (1UL << 1)

#define	MUSBD_IntrUSBE_Suspend (1UL << 0)

#define	MUSB_Frame 0x0054

#define	MUSB_Index 0x0042

#define	MUSB_Testmode 0x007c

#define	MUSB_TxMaxP 0x0080

#define	MUSB_CSR0 0x0082

#define	MUSBD_CSR0_FlushFIFO (1UL << 8)

#define	MUSBD_CSR0_ServicedSetupEnd (1UL << 7)

#define	MUSBD_CSR0_ServicedRxPktRdy (1UL << 6)

#define	MUSBD_CSR0_SendStall (1UL << 5)

#define	MUSBD_CSR0_SetupEnd (1UL << 4)

#define	MUSBD_CSR0_DataEnd (1UL << 3)

#define	MUSBD_CSR0_SentStall (1UL << 2)

#define	MUSBD_CSR0_TxPktRdy (1UL << 1)

#define	MUSBD_CSR0_RxPktRdy (1UL << 0)

#define	MUSBH_CSR0_DisPing (1UL << 11)

#define	MUSBH_CSR0_DataToggleWrEnable (1UL << 10)

#define	MUSBH_CSR0_DataToggle (1UL << 9)

#define	MUSBH_CSR0_FlushFIFO (1UL << 8)

#define	MUSBH_CSR0_NAKTimeout (1UL << 7)

#define	MUSBH_CSR0_StatusPkt (1UL << 6)

#define	MUSBH_CSR0_ReqPkt (1UL << 5)

#define	MUSBH_CSR0_Error (1UL << 4)

#define	MUSBH_CSR0_SetupPkt (1UL << 3)

#define	MUSBH_CSR0_RxStall (1UL << 2)

#define	MUSBH_CSR0_TxPktRdy (1UL << 1)

#define	MUSBH_CSR0_RxPktRdy (1UL << 0)

#define	MUSB_TxCSR 0x0082

#define	MUSBD_TxCSRL_IncompTx (1UL << 7)

#define	MUSBD_TxCSRL_ClrDataTog (1UL << 6)

#define	MUSBD_TxCSRL_SentStall (1UL << 5)

#define	MUSBD_TxCSRL_SendStall (1UL << 4)

#define	MUSBD_TxCSRL_FlushFIFO (1UL << 3)

#define	MUSBD_TxCSRL_UnderRun (1UL << 2)

#define	MUSBD_TxCSRL_FIFONotEmpty (1UL << 1)

#define	MUSBD_TxCSRL_TxPktRdy (1UL << 0)

#define	MUSBD_TxCSRH_NAKTimeout (1UL << 7)

#define	MUSBD_TxCSRH_AutoSet (1UL << 7)

#define	MUSBD_TxCSRH_ISO (1UL << 6)

#define	MUSBD_TxCSRH_Mode (1UL << 5)

#define	MUSBD_TxCSRH_Mode_Tx (1UL << 5)

#define	MUSBD_TxCSRH_Mode_Rx (0UL << 5)

#define	MUSBD_TxCSRH_DMAReqEnab (1UL << 4)

#define	MUSBD_TxCSRH_FrcDataTog (1UL << 3)

#define	MUSBD_TxCSRH_DMAReqMode (1UL << 2)

#define	MUSBH_TxCSRL_NAKTimeout (1UL << 7)

#define	MUSBH_TxCSRL_IncomTx (1UL << 7)

#define	MUSBH_TxCSRL_ClrDataTog (1UL << 6)

#define	MUSBH_TxCSRL_RxStall (1UL << 5)

#define	MUSBH_TxCSRL_SetupPkt (1UL << 4)

#define	MUSBH_TxCSRL_FlushFIFO (1UL << 3)

#define	MUSBH_TxCSRL_Error (1UL << 2)

#define	MUSBH_TxCSRL_FIFONotEmpty (1UL << 1)

#define	MUSBH_TxCSRL_TxPktRdy (1UL << 0)

#define	MUSBH_TxCSRH_AutoSet (1UL << 7)

#define	MUSBH_TxCSRH_Mode (1UL << 6)

#define	MUSBH_TxCSRH_Mode_Tx (1UL << 5)

#define	MUSBH_TxCSRH_Mode_Rx (0UL << 5)

#define	MUSBH_TxCSRH_DMAReqEnab (1UL << 4)

#define	MUSBH_TxCSRH_FrcDataTog (1UL << 3)

#define	MUSBH_TxCSRH_DMAReqMode (1UL << 2)

#define	MUSBH_TxCSRH_DataToggleWrEnable (1UL << 1)

#define	MUSBH_TxCSRH_DataToggle (1UL << 0)

#define	MUSB_RxMaxP 0x0084

#define	MUSB_RxCSR 0x0086

#define	MUSBD_RxCSRL_ClrDataTog (1UL << 7)

#define	MUSBD_RxCSRL_SentStall (1UL << 6)

#define	MUSBD_RxCSRL_SendStall (1UL << 5)

#define	MUSBD_RxCSRL_FlushFIFO (1UL << 4)

#define	MUSBD_RxCSRL_DataError (1UL << 3)

#define	MUSBD_RxCSRL_OverRun (1UL << 2)

#define	MUSBD_RxCSRL_FIFOFull (1UL << 1)

#define	MUSBD_RxCSRL_RxPktRdy (1UL << 0)

#define	MUSBD_RxCSRH_AutoClear (1UL << 7)

#define	MUSBD_RxCSRH_ISO (1UL << 6)

#define	MUSBD_RxCSRH_DMAReqEnab (1UL << 5)

#define	MUSBD_RxCSRH_DisNyet (1UL << 4)

#define	MUSBD_RxCSRH_PIDError (1UL << 4)

#define	MUSBD_RxCSRH_DMAReqMode (1UL << 3)

#define	MUSBD_RxCSRH_IncompRx (1UL << 0)

#define	MUSBH_RxCSRL_ClrDataTog (1UL << 7)

#define	MUSBH_RxCSRL_RxStall (1UL << 6)

#define	MUSBH_RxCSRL_ReqPkt (1UL << 5)

#define	MUSBH_RxCSRL_FlushFIFO (1UL << 4)

#define	MUSBH_RxCSRL_DataError (1UL << 3)

#define	MUSBH_RxCSRL_NAKTimeout (1UL << 3)

#define	MUSBH_RxCSRL_Error (1UL << 2)

#define	MUSBH_RxCSRL_FIFOFull (1UL << 1)

#define	MUSBH_RxCSRL_RxPktRdy (1UL << 0)

#define	MUSBH_RxCSRH_AutoClear (1UL << 7)

#define	MUSBH_RxCSRH_AutoReq (1UL << 6)

#define	MUSBH_RxCSRH_DMAReqEnab (1UL << 5)

#define	MUSBH_RxCSRH_PIDError (1UL << 4)

#define	MUSBH_RxCSRH_DMAReqMode (1UL << 3)

#define	MUSBH_RxCSRH_DataToggleWrEnable (1UL << 2)

#define	MUSBH_RxCSRH_DataToggle (1UL << 1)

#define	MUSBH_RxCSRH_IncompRx (1UL << 0)

#define	MUSB_Count0 0x0088

#define	MUSB_RxCount 0x0088

#define	MUSB_Type0 0x008c

#define	MUSB_TxType 0x008c

#define	MUSB_NAKLimit0 0x008d

#define	MUSB_TxInterval 0x008d

#define	MUSB_RxType 0x008e

#define	MUSB_RxInterval 0x008f

#define	MUSB_ConfigData 0x001f

#define	MUSB_FIFO0 0x0000

#define	MUSB_FIFO1 0x0004

#define	MUSB_FIFO2 0x0008

#define	MUSB_FIFO3 0x000c

#define	MUSB_FIFO4 0x0010

#define	MUSB_FIFO5 0x0014

#define	MUSB_DevCtl 0x0041

#define	MUSB_DevCtl_FSDev (1UL << 6)

#define	MUSB_DevCtl_LSDev (1UL << 5)

#define	MUSB_DevCtl_HostMode (1UL << 2)

#define	MUSB_DevCtl_Session (1UL << 0)

#define	MUSB_MISC

#define	MUSB_TxFIFOsz 0x0090

#define	MUSB_RxFIFOsz 0x0094

#define	MUSB_TxFIFOadd 0x0092

#define	MUSB_RxFIFOadd 0x0096

#define	MUSB_TxFuncAddr 0x0098

#define	MUSB_TxHubAddr 0x009a

#define	MUSB_TxHubPort 0x009b

#define	MUSB_RxFuncAddr 0x009c

#define	MUSB_RxHubAddr 0x009e

#define	MUSB_RxHubPort 0x009f

#define	MUSB_Vendor0 0x0043

#define	MUSB_Vendor1 0x007d

#define	MUSB_Vendor2 0x007e

#define	MUSB_HWVers

#define	MUSB_EPInfo 0x0078

#define	MUSB_RAMInfo 0x0079

#define	MUSB_LinkInfo 0x007a

#define	MUSB_VPLen 0x007b

#define	MUSB_HS_EOF1 0x007c

#define	MUSB_FS_EOF1 0x007d

#define	MUSB_LS_EOF1 0x007e

#define	MUSB_SOFT_RST

#define	MUSB_ISCR 0x0400

#define	MUSB_ISCR_VBUS_VALID_FROM_DATA (1UL << 30)

#define	MUSB_ISCR_VBUS_VALID_FROM_VBUS (1UL << 29)

#define	MUSB_ISCR_EXT_ID_STATUS (1UL << 28)

#define	MUSB_ISCR_EXT_DM_STATUS (1UL << 27)

#define	MUSB_ISCR_EXT_DP_STATUS (1UL << 26)

#define	MUSB_ISCR_MERGED_VBUS_STATUS (1UL << 25)

#define	MUSB_ISCR_MERGED_ID_STATUS (1UL << 24)

#define	MUSB_ISCR_ID_PULLUP_EN (1UL << 17)

#define	MUSB_ISCR_DPDM_PULLUP_EN (1UL << 16)

#define	MUSB_ISCR_FORCE_ID (3UL << 14)

#define	MUSB_ISCR_FORCE_ID_DEVICE (3UL << 14)

#define	MUSB_ISCR_FORCE_ID_HOST (2UL << 14)

#define	MUSB_ISCR_FORCE_VBUS_VALID (3UL << 12)

#define	MUSB_ISCR_FORCE_VBUS_VALID_HIGH (3UL << 12)

#define	MUSB_ISCR_FORCE_VBUS_VALID_LOW (2UL << 12)

#define	MUSB_ISCR_VBUS_VALID_SRC (1UL << 10)

#define	MUSB_ISCR_HOSC_EN (1UL << 7)

#define	MUSB_ISCR_VBUS_CHANGE_DETECT (1UL << 6)

#define	MUSB_ISCR_ID_CHANGE_DETECT (1UL << 5)

#define	MUSB_ISCR_DPDM_CHANGE_DETECT (1UL << 4)

#define	MUSB_ISCR_IRQ_ENABLE (1UL << 3)

#define	MUSB_ISCR_VBUS_CHANGE_DETECT_EN (1UL << 2)

#define	MUSB_ISCR_ID_CHANGE_DETECT_EN (1UL << 1)

#define	MUSB_ISCR_DPDM_CHANGE_DETECT_EN (1UL << 0)

#define	TP_BASE ((tp_reg_t *)0x01c24800)

#define	TP_CTRL0 0x00

#define	ADC_FIRST_DLY(__DLY)

#define	ADC_FIRST_DLY_MODE(__DLY_MODE)

#define	ADC_CLK_SEL(__CLK_SEL)

#define	ADC_CLK_DIV(__CLK_DIV)

#define	FS_DIV(x)

#define	T_ACQ(x)

#define	TP_CTRL1 0x04

#define	STYLUS_UP_DEBOUN(x)

#define	STYLUS_UP_DEBOUN_EN(x)

#define	TOUCH_PAN_CALI_EN(x)

#define	TP_DUAL_EN(x)

#define	TP_MODE_EN(x)

#define	TP_ADC_SELECT(x)

#define	ADC_CHAN_SELECT(x)

#define	TP_CTRL2 0x08

#define	TP_SENSITIVE_ADJUST(x)

#define	TP_MODE_SELECT(x)

#define	PRE_MEA_EN(x)

#define	PRE_MEA_THRE_CNT(x)

#define	TP_CTRL3 0x0c

#define	FILTER_EN(x)

#define	FILTER_TYPE(x)

#define	TP_INT_FIFOC 0x10

#define	TEMP_IRQ_EN(x)

#define	OVERRUN_IRQ_EN(x)

#define	DATA_IRQ_EN(x)

#define	TP_DATA_XY_CHANGE(x)

#define	FIFO_TRIG(x)

#define	DATA_DRQ_EN(x)

#define	FIFO_FLUSH(x)

#define	TP_UP_IRQ_EN(x)

#define	TP_DOWN_IRQ_EN(x)

#define	TP_INT_FIFOS 0x14

#define	TEMP_DATA_PENDING (1 << 18)

#define	FIFO_OVERRUN_PENDING (1 << 17)

#define	FIFO_DATA_PENDING (1 << 16)

#define	TP_IDLE_FLG (1 << 2)

#define	TP_UP_PENDING (1 << 1)

#define	TP_DOWN_PENDING (1 << 0)

#define	TP_TPR 0x18

#define	TEMP_ENABLE(x)

#define	TEMP_PERIOD(x)

#define	TP_CDAT 0x1c

#define	TP_TEMP_DATA 0x20

#define	TP_DATA 0x24

#define	read_reg8(__base, __reg)

#define	read_reg16(__base, __reg)

#define	read_reg32(__base, __reg)

#define	write_reg8(__base, __reg, __value)

#define	write_reg16(__base, __reg, __value)

#define	write_reg32(__base, __reg, __value)

#define	__REG_TYPE__

#define	__REG_CONNECT(__A, __B)

#define	__REG_RSVD_NAME(__NAME)

#define	____REG_RSVD(__NAME, __BIT)

#define	____REG_RSVD_N(__NAME, __BIT, __N)

#define	__REG_RSVD(__BIT)

#define	__REG_RSVD_N(__BIT, __N)

#define	REG_RSVD_NAME __REG_RSVD_NAME(__LINE__)

#define	REG_RSVD(__BIT)

#define	REG_RSVD_N(__BIT, __N)

#define	REG_RSVD_U8 REG_RSVD(8)

#define	REG_RSVD_U16 REG_RSVD(16)

#define	REG_RSVD_U32 REG_RSVD(32)

#define	REG_RSVD_U8N(__N)

#define	REG_RSVD_U16N(__N)

#define	REG_RSVD_U32N(__N)

#define	REG8_RSVD_N(__N)

#define	REG8_RSVD_B(__BYTE_CNT)

#define	REG8_RSVD_8B REG8_RSVD_B(8)

#define	REG8_RSVD_16B REG8_RSVD_B(16)

#define	REG8_RSVD_32B REG8_RSVD_B(32)

#define	REG8_RSVD_64B REG8_RSVD_B(64)

#define	REG8_RSVD_128B REG8_RSVD_B(128)

#define	REG8_RSVD_256B REG8_RSVD_B(256)

#define	REG8_RSVD_512B REG8_RSVD_B(512)

#define	REG8_RSVD_1K REG8_RSVD_B(1024)

#define	REG8_RSVD_2K REG8_RSVD_B(2048)

#define	REG8_RSVD_4K REG8_RSVD_B(4096)

#define	REG8_RSVD_8K REG8_RSVD_B(8192)

#define	REG8_RSVD_16K REG8_RSVD_B(16 * 1024)

#define	REG8_RSVD_32K REG8_RSVD_B(32 * 1024)

#define	REG8_RSVD_64K REG8_RSVD_B(64 * 1024)

#define	REG8_RSVD_128K REG8_RSVD_B(128 * 1024)

#define	REG8_RSVD_256K REG8_RSVD_B(256 * 1024)

#define	REG8_RSVD_512K REG8_RSVD_B(512 * 1024)

#define	REG8_RSVD_1M REG8_RSVD_B(1024 * 1024)

#define	REG16_RSVD_N(__N)

#define	REG16_RSVD_B(__BYTE_CNT)

#define	REG16_RSVD_8B REG16_RSVD_B(8)

#define	REG16_RSVD_16B REG16_RSVD_B(16)

#define	REG16_RSVD_32B REG16_RSVD_B(32)

#define	REG16_RSVD_64B REG16_RSVD_B(64)

#define	REG16_RSVD_128B REG16_RSVD_B(128)

#define	REG16_RSVD_256B REG16_RSVD_B(256)

#define	REG16_RSVD_512B REG16_RSVD_B(512)

#define	REG16_RSVD_1K REG16_RSVD_B(1024)

#define	REG16_RSVD_2K REG16_RSVD_B(2048)

#define	REG16_RSVD_4K REG16_RSVD_B(4096)

#define	REG16_RSVD_8K REG16_RSVD_B(8192)

#define	REG16_RSVD_16K REG16_RSVD_B(16 * 1024)

#define	REG16_RSVD_32K REG16_RSVD_B(32 * 1024)

#define	REG16_RSVD_64K REG16_RSVD_B(64 * 1024)

#define	REG16_RSVD_128K REG16_RSVD_B(128 * 1024)

#define	REG16_RSVD_256K REG16_RSVD_B(256 * 1024)

#define	REG16_RSVD_512K REG16_RSVD_B(512 * 1024)

#define	REG16_RSVD_1M REG16_RSVD_B(1024 * 1024)

#define	REG32_RSVD_N(__N)

#define	REG32_RSVD_B(__BYTE_CNT)

#define	REG32_RSVD_8B REG32_RSVD_B(8)

#define	REG32_RSVD_16B REG32_RSVD_B(16)

#define	REG32_RSVD_32B REG32_RSVD_B(32)

#define	REG32_RSVD_64B REG32_RSVD_B(64)

#define	REG32_RSVD_128B REG32_RSVD_B(128)

#define	REG32_RSVD_256B REG32_RSVD_B(256)

#define	REG32_RSVD_512B REG32_RSVD_B(512)

#define	REG32_RSVD_1K REG32_RSVD_B(1024)

#define	REG32_RSVD_2K REG32_RSVD_B(2048)

#define	REG32_RSVD_4K REG32_RSVD_B(4096)

#define	REG32_RSVD_8K REG32_RSVD_B(8192)

#define	REG32_RSVD_16K REG32_RSVD_B(16 * 1024)

#define	REG32_RSVD_32K REG32_RSVD_B(32 * 1024)

#define	REG32_RSVD_64K REG32_RSVD_B(64 * 1024)

#define	REG32_RSVD_128K REG32_RSVD_B(128 * 1024)

#define	REG32_RSVD_256K REG32_RSVD_B(256 * 1024)

#define	REG32_RSVD_512K REG32_RSVD_B(512 * 1024)

#define	REG32_RSVD_1M REG32_RSVD_B(1024 * 1024)

Typedefs
typedef enum IRQn	IRQn_Type

typedef struct syscon_reg_t	syscon_reg_t

typedef struct ccu_reg_t	ccu_reg_t

typedef struct dram_reg_t	dram_reg_t

typedef struct pio_port_t	pio_port_t

typedef struct pio_port_int_t	pio_port_int_t

typedef struct pio_reg_t	pio_reg_t

typedef struct uart_reg_t	uart_reg_t

typedef struct spi_reg_t	spi_reg_t

typedef struct tcon_reg_t	tcon_reg_t

typedef struct debe_reg_t	debe_reg_t

typedef struct tve_reg_t	tve_reg_t

typedef struct timer_reg_t	timer_reg_t

typedef struct musb_reg_t	musb_reg_t

typedef struct tp_reg_t	tp_reg_t

Enumerations
enum	IRQn { UART0_IRQn = 1 , UART1_IRQn , UART2_IRQn , OWA_IRQn = 5 , CIR_IRQn , TWI0_IRQn , TWI1_IRQn , TWI2_IRQn , SPI0_IRQn , SPI1_IRQn , Timer0_IRQn = 13 , Timer1_IRQn , Timer2_IRQn , WatchDog_IRQn , RSB_IRQn , DMA_IRQn , TouchPanel_IRQn = 20 , AudioCodec_IRQn , KEYADC_IRQn , SDC0_IRQn , SDC1_IRQn , USBOTG_IRQn = 26 , TVD_IRQn , TVE_IRQn , TCON_IRQn , DEFE_IRQn , DEBE_IRQn , CSI_IRQn , DEInterlacer_IRQn , VE_IRQn , DAUDIO_IRQn , PIOD_IRQn = 38 , PIOE_IRQn , PIOF_IRQn , SWI0_IRQn = 60 , SWI1_IRQn , SWI2_IRQn , SWI3_IRQn }

Macro Definition Documentation

◆ SYSCON_BASE

#define SYSCON_BASE ((syscon_reg_t *)0x01c00000)

Note: i_reg_xxxx.h header files must be standalong and assume following ! conditions: ! a. stdint.h exists ! b. anonymous structures and unions are supported

◆ SYSCON_USB_CTRL

#define SYSCON_USB_CTRL 0x004

◆ USB_FIFO_MODE

#define USB_FIFO_MODE (3UL << 0)

◆ USB_FIFO_MODE_8KB

#define USB_FIFO_MODE_8KB (1UL << 0)

◆ CCU_BASE

#define CCU_BASE ((ccu_reg_t *)0x01c20000)

◆ CCU_PLL_CPU_CTRL

#define CCU_PLL_CPU_CTRL 0x000

◆ PLL_CPU_CTRL_PLL_ENABLE

#define PLL_CPU_CTRL_PLL_ENABLE (1UL << 31)

◆ PLL_CPU_CTRL_LOCK

#define PLL_CPU_CTRL_LOCK (1UL << 28)

◆ __PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P

#define __PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P ( __P )

Value:

(((__P) >> 1) << 16)

◆ __PLL_CPU_CTRL_PLL_FACTOR_N

#define __PLL_CPU_CTRL_PLL_FACTOR_N ( __N )

Value:

(((__N) - 1) << 8)

◆ __PLL_CPU_CTRL_PLL_FACTOR_K

#define __PLL_CPU_CTRL_PLL_FACTOR_K ( __K )

Value:

(((__K) - 1) << 4)

◆ __PLL_CPU_CTRL_PLL_FACTOR_M

#define __PLL_CPU_CTRL_PLL_FACTOR_M ( __M )

Value:

(((__M) - 1) << 0)

◆ PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P

#define PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P ( ... )

Value:

__PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P((6UL, ##__VA_ARGS__))

__PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P

#define __PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P(__P)

Definition f1c100s_reg.h:43

◆ PLL_CPU_CTRL_PLL_FACTOR_N

#define PLL_CPU_CTRL_PLL_FACTOR_N ( ... )

Value:

__PLL_CPU_CTRL_PLL_FACTOR_N((32UL, ##__VA_ARGS__))

__PLL_CPU_CTRL_PLL_FACTOR_N

#define __PLL_CPU_CTRL_PLL_FACTOR_N(__N)

Definition f1c100s_reg.h:44

◆ PLL_CPU_CTRL_PLL_FACTOR_K

#define PLL_CPU_CTRL_PLL_FACTOR_K ( ... )

Value:

__PLL_CPU_CTRL_PLL_FACTOR_K((4UL, ##__VA_ARGS__))

__PLL_CPU_CTRL_PLL_FACTOR_K

#define __PLL_CPU_CTRL_PLL_FACTOR_K(__K)

Definition f1c100s_reg.h:45

◆ PLL_CPU_CTRL_PLL_FACTOR_M

#define PLL_CPU_CTRL_PLL_FACTOR_M ( ... )

Value:

__PLL_CPU_CTRL_PLL_FACTOR_M((4UL, ##__VA_ARGS__))

__PLL_CPU_CTRL_PLL_FACTOR_M

#define __PLL_CPU_CTRL_PLL_FACTOR_M(__M)

Definition f1c100s_reg.h:46

◆ CCU_PLL_AUDIO_CTRL

#define CCU_PLL_AUDIO_CTRL 0x008

◆ PLL_AUDIO_CTRL_PLL_ENABLE

#define PLL_AUDIO_CTRL_PLL_ENABLE (1UL << 31)

◆ PLL_AUDIO_CTRL_LOCK

#define PLL_AUDIO_CTRL_LOCK (1UL << 28)

◆ PLL_AUDIO_CTRL_PLL_SDM_EN

#define PLL_AUDIO_CTRL_PLL_SDM_EN (1UL << 24)

◆ __PLL_AUDIO_CTRL_PLL_FACTOR_N

#define __PLL_AUDIO_CTRL_PLL_FACTOR_N ( __N )

Value:

(((__N) - 1) << 8)

◆ __PLL_AUDIO_CTRL_PLL_PREDIV_M

#define __PLL_AUDIO_CTRL_PLL_PREDIV_M ( __M )

Value:

(((__M) - 1) << 0)

◆ PLL_AUDIO_CTRL_PLL_FACTOR_N

#define PLL_AUDIO_CTRL_PLL_FACTOR_N ( ... )

Value:

__PLL_AUDIO_CTRL_PLL_FACTOR_N((128UL, ##__VA_ARGS__))

__PLL_AUDIO_CTRL_PLL_FACTOR_N

#define __PLL_AUDIO_CTRL_PLL_FACTOR_N(__N)

Definition f1c100s_reg.h:60

◆ PLL_AUDIO_CTRL_PLL_PREDIV_M

#define PLL_AUDIO_CTRL_PLL_PREDIV_M ( ... )

Value:

__PLL_AUDIO_CTRL_PLL_PREDIV_M((32UL, ##__VA_ARGS__))

__PLL_AUDIO_CTRL_PLL_PREDIV_M

#define __PLL_AUDIO_CTRL_PLL_PREDIV_M(__M)

Definition f1c100s_reg.h:61

◆ CCU_PLL_VIDEO_CTRL

#define CCU_PLL_VIDEO_CTRL 0x010

◆ PLL_VIDEO_CTRL_PLL_ENABLE

#define PLL_VIDEO_CTRL_PLL_ENABLE (1UL << 31)

◆ PLL_VIDEO_CTRL_PLL_MODE

#define PLL_VIDEO_CTRL_PLL_MODE (1UL << 30)

◆ PLL_VIDEO_CTRL_PLL_MODE_AUTO

#define PLL_VIDEO_CTRL_PLL_MODE_AUTO PLL_VIDEO_CTRL_PLL_MODE

◆ PLL_VIDEO_CTRL_PLL_MODE_MANUAL

#define PLL_VIDEO_CTRL_PLL_MODE_MANUAL 0

◆ PLL_VIDEO_CTRL_LOCK

#define PLL_VIDEO_CTRL_LOCK (1UL << 28)

◆ PLL_VIDEO_CTRL_FRAC_CLK_OUT

#define PLL_VIDEO_CTRL_FRAC_CLK_OUT (1UL << 25)

◆ PLL_VIDEO_CTRL_PLL_MODE_SEL

#define PLL_VIDEO_CTRL_PLL_MODE_SEL (1UL << 24)

◆ PLL_VIDEO_CTRL_PLL_MODE_INTEGER

#define PLL_VIDEO_CTRL_PLL_MODE_INTEGER PLL_VIDEO_CTRL_PLL_MODE_SEL

◆ PLL_VIDEO_CTRL_PLL_MODE_FRACTIONAL

#define PLL_VIDEO_CTRL_PLL_MODE_FRACTIONAL 0

◆ PLL_VIDEO_CTRL_PLL_SDM_EN

#define PLL_VIDEO_CTRL_PLL_SDM_EN (1UL << 20)

◆ __PLL_VIDEO_CTRL_PLL_FACTOR_N

#define __PLL_VIDEO_CTRL_PLL_FACTOR_N ( __N )

Value:

(((__N) - 1) << 8)

◆ __PLL_VIDEO_CTRL_PLL_PREDIV_M

#define __PLL_VIDEO_CTRL_PLL_PREDIV_M ( __M )

Value:

(((__M) - 1) << 0)

◆ PLL_VIDEO_CTRL_PLL_FACTOR_N

#define PLL_VIDEO_CTRL_PLL_FACTOR_N ( ... )

Value:

__PLL_VIDEO_CTRL_PLL_FACTOR_N((128UL, ##__VA_ARGS__))

__PLL_VIDEO_CTRL_PLL_FACTOR_N

#define __PLL_VIDEO_CTRL_PLL_FACTOR_N(__N)

Definition f1c100s_reg.h:78

◆ PLL_VIDEO_CTRL_PLL_PREDIV_M

#define PLL_VIDEO_CTRL_PLL_PREDIV_M ( ... )

Value:

__PLL_VIDEO_CTRL_PLL_PREDIV_M((16UL, ##__VA_ARGS__))

__PLL_VIDEO_CTRL_PLL_PREDIV_M

#define __PLL_VIDEO_CTRL_PLL_PREDIV_M(__M)

Definition f1c100s_reg.h:79

◆ CCU_PLL_VE_CTRL

#define CCU_PLL_VE_CTRL 0x018

◆ PLL_VE_CTRL_PLL_ENABLE

#define PLL_VE_CTRL_PLL_ENABLE (1UL << 31)

◆ PLL_VE_CTRL_LOCK

#define PLL_VE_CTRL_LOCK (1UL << 28)

◆ PLL_VE_CTRL_FRAC_CLK_OUT

#define PLL_VE_CTRL_FRAC_CLK_OUT (1UL << 25)

◆ PLL_VE_CTRL_PLL_MODE_SEL

#define PLL_VE_CTRL_PLL_MODE_SEL (1UL << 24)

◆ PLL_VE_CTRL_PLL_MODE_FRACTIONAL

#define PLL_VE_CTRL_PLL_MODE_FRACTIONAL (0UL << 24)

◆ PLL_VE_CTRL_PLL_MODE_INTEGER

#define PLL_VE_CTRL_PLL_MODE_INTEGER (1UL << 24)

◆ __PLL_VE_CTRL_PLL_FACTOR_N

#define __PLL_VE_CTRL_PLL_FACTOR_N ( __N )

Value:

(((__N) - 1) << 8)

◆ __PLL_VE_CTRL_PLL_PREDIV_M

#define __PLL_VE_CTRL_PLL_PREDIV_M ( __M )

Value:

(((__M) - 1) << 0)

◆ PLL_VE_CTRL_PLL_FACTOR_N

#define PLL_VE_CTRL_PLL_FACTOR_N ( ... )

Value:

__PLL_VE_CTRL_PLL_FACTOR_N((128UL, ##__VA_ARGS__))

__PLL_VE_CTRL_PLL_FACTOR_N

#define __PLL_VE_CTRL_PLL_FACTOR_N(__N)

Definition f1c100s_reg.h:93

◆ PLL_VE_CTRL_PLL_PREDIV_M

#define PLL_VE_CTRL_PLL_PREDIV_M ( ... )

Value:

__PLL_VE_CTRL_PLL_PREDIV_M((16UL, ##__VA_ARGS__))

__PLL_VE_CTRL_PLL_PREDIV_M

#define __PLL_VE_CTRL_PLL_PREDIV_M(__M)

Definition f1c100s_reg.h:94

◆ CCU_PLL_DDR_CTRL

#define CCU_PLL_DDR_CTRL 0x020

◆ PLL_DDR_CTRL_PLL_ENABLE

#define PLL_DDR_CTRL_PLL_ENABLE (1UL << 31)

◆ PLL_DDR_CTRL_LOCK

#define PLL_DDR_CTRL_LOCK (1UL << 28)

◆ PLL_DDR_CTRL_SDRAM_SIGMA_DELTA_EN

#define PLL_DDR_CTRL_SDRAM_SIGMA_DELTA_EN (1UL << 24)

◆ PLL_DDR_CTRL_PLL_DDR_CFG_UPDATE

#define PLL_DDR_CTRL_PLL_DDR_CFG_UPDATE (1UL << 20)

◆ __PLL_DDR_CTRL_PLL_FACTOR_N

#define __PLL_DDR_CTRL_PLL_FACTOR_N ( __N )

Value:

(((__N) - 1) << 8)

◆ __PLL_DDR_CTRL_PLL_FACTOR_K

#define __PLL_DDR_CTRL_PLL_FACTOR_K ( __K )

Value:

(((__K) - 1) << 4)

◆ __PLL_DDR_CTRL_PLL_FACTOR_M

#define __PLL_DDR_CTRL_PLL_FACTOR_M ( __M )

Value:

(((__M) - 1) << 0)

◆ PLL_DDR_CTRL_PLL_FACTOR_N

#define PLL_DDR_CTRL_PLL_FACTOR_N ( ... )

Value:

__PLL_DDR_CTRL_PLL_FACTOR_N((32UL, ##__VA_ARGS__))

__PLL_DDR_CTRL_PLL_FACTOR_N

#define __PLL_DDR_CTRL_PLL_FACTOR_N(__N)

Definition f1c100s_reg.h:106

◆ PLL_DDR_CTRL_PLL_FACTOR_K

#define PLL_DDR_CTRL_PLL_FACTOR_K ( ... )

Value:

__PLL_DDR_CTRL_PLL_FACTOR_K((4UL, ##__VA_ARGS__))

__PLL_DDR_CTRL_PLL_FACTOR_K

#define __PLL_DDR_CTRL_PLL_FACTOR_K(__K)

Definition f1c100s_reg.h:107

◆ PLL_DDR_CTRL_PLL_FACTOR_M

#define PLL_DDR_CTRL_PLL_FACTOR_M ( ... )

Value:

__PLL_DDR_CTRL_PLL_FACTOR_M((4UL, ##__VA_ARGS__))

__PLL_DDR_CTRL_PLL_FACTOR_M

#define __PLL_DDR_CTRL_PLL_FACTOR_M(__M)

Definition f1c100s_reg.h:108

◆ CCU_PLL_PERIPH_CTRL

#define CCU_PLL_PERIPH_CTRL 0x028

◆ PLL_PERIPH_CTRL_PLL_ENABLE

#define PLL_PERIPH_CTRL_PLL_ENABLE (1UL << 31)

◆ PLL_PERIPH_CTRL_LOCK

#define PLL_PERIPH_CTRL_LOCK (1UL << 28)

◆ PLL_PERIPH_CTRL_PLL_24M_OUT_EN

#define PLL_PERIPH_CTRL_PLL_24M_OUT_EN (1UL << 18)

◆ __PLL_PERIPH_CTRL_PLL_FACTOR_N

#define __PLL_PERIPH_CTRL_PLL_FACTOR_N ( __N )

Value:

(((__N) - 1) << 8)

◆ __PLL_PERIPH_CTRL_PLL_FACTOR_K

#define __PLL_PERIPH_CTRL_PLL_FACTOR_K ( __K )

Value:

(((__K) - 1) << 4)

◆ PLL_PERIPH_CTRL_PLL_FACTOR_N

#define PLL_PERIPH_CTRL_PLL_FACTOR_N ( ... )

Value:

__PLL_PERIPH_CTRL_PLL_FACTOR_N((32UL, ##__VA_ARGS__))

__PLL_PERIPH_CTRL_PLL_FACTOR_N

#define __PLL_PERIPH_CTRL_PLL_FACTOR_N(__N)

Definition f1c100s_reg.h:120

◆ PLL_PERIPH_CTRL_PLL_FACTOR_K

#define PLL_PERIPH_CTRL_PLL_FACTOR_K ( ... )

Value:

__PLL_PERIPH_CTRL_PLL_FACTOR_K((4UL, ##__VA_ARGS__))

__PLL_PERIPH_CTRL_PLL_FACTOR_K

#define __PLL_PERIPH_CTRL_PLL_FACTOR_K(__K)

Definition f1c100s_reg.h:121

◆ CCU_CPU_CLK_SRC

#define CCU_CPU_CLK_SRC 0x050

◆ CPU_CLK_SRC_SEL

#define CPU_CLK_SRC_SEL (3UL << 16)

◆ CPU_CLK_SRC_SEL_LOSC

#define CPU_CLK_SRC_SEL_LOSC (0UL << 16)

◆ CPU_CLK_SRC_SEL_OSC24M

#define CPU_CLK_SRC_SEL_OSC24M (1UL << 16)

◆ CPU_CLK_SRC_SEL_PLL_CPU

#define CPU_CLK_SRC_SEL_PLL_CPU (2UL << 16)

◆ CCU_AHB_APB_HCLKC_CFG

#define CCU_AHB_APB_HCLKC_CFG 0x054

◆ __AHB_APB_HCLKC_CFG_HCLKC_DIV

#define __AHB_APB_HCLKC_CFG_HCLKC_DIV ( __DIV )

Value:

(((__DIV) - 1) << 16)

◆ AHB_APB_HCLKC_CFG_HCLKC_DIV

#define AHB_APB_HCLKC_CFG_HCLKC_DIV ( ... )

Value:

__AHB_APB_HCLKC_CFG_HCLKC_DIV((4UL, ##__VA_ARGS__))

__AHB_APB_HCLKC_CFG_HCLKC_DIV

#define __AHB_APB_HCLKC_CFG_HCLKC_DIV(__DIV)

Definition f1c100s_reg.h:133

◆ AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL

#define AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL (3UL << 12)

◆ AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_LOSC

#define AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_LOSC (0UL << 12)

◆ AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_OSC24M

#define AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_OSC24M (1UL << 12)

◆ AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_CPUCLK

#define AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_CPUCLK (2UL << 12)

◆ AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_PERIPH

#define AHB_APB_HCLKC_CFG_AHB_CLK_SRC_SEL_PERIPH (3UL << 12)

◆ __AHB_APB_HCLKC_CFG_APB_CLK_RATIO

#define __AHB_APB_HCLKC_CFG_APB_CLK_RATIO ( __R )

Value:

((__R) << 8)

◆ __AHB_APB_HCLKC_CFG_AHB_PRE_DIV

#define __AHB_APB_HCLKC_CFG_AHB_PRE_DIV ( __DIV )

Value:

(((__DIV) - 1) << 6)

◆ __AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO

#define __AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO ( __R )

Value:

((__R) << 4)

◆ AHB_APB_HCLKC_CFG_APB_CLK_RATIO

#define AHB_APB_HCLKC_CFG_APB_CLK_RATIO ( ... )

Value:

__AHB_APB_HCLKC_CFG_APB_CLK_RATIO((3UL, ##__VA_ARGS__))

__AHB_APB_HCLKC_CFG_APB_CLK_RATIO

#define __AHB_APB_HCLKC_CFG_APB_CLK_RATIO(__R)

Definition f1c100s_reg.h:141

◆ AHB_APB_HCLKC_CFG_AHB_PRE_DIV

#define AHB_APB_HCLKC_CFG_AHB_PRE_DIV ( ... )

Value:

__AHB_APB_HCLKC_CFG_AHB_PRE_DIV((4UL, ##__VA_ARGS__))

__AHB_APB_HCLKC_CFG_AHB_PRE_DIV

#define __AHB_APB_HCLKC_CFG_AHB_PRE_DIV(__DIV)

Definition f1c100s_reg.h:142

◆ AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO

#define AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO ( ... )

Value:

__AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO((3UL, ##__VA_ARGS__))

__AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO

#define __AHB_APB_HCLKC_CFG_AHB_CLK_DIV_RATIO(__R)

Definition f1c100s_reg.h:143

◆ CCU_BUS_CLK_GATINT0

#define CCU_BUS_CLK_GATINT0 0x060

◆ BUS_CLK_GATING0_USB_OTG_GATING

#define BUS_CLK_GATING0_USB_OTG_GATING (1UL << 24)

◆ BUS_CLK_GATING0_SPI1_GATING

#define BUS_CLK_GATING0_SPI1_GATING (1UL << 21)

◆ BUS_CLK_GATING0_SPI0_GATING

#define BUS_CLK_GATING0_SPI0_GATING (1UL << 20)

◆ BUS_CLK_GATING0_SDRAM_GATING

#define BUS_CLK_GATING0_SDRAM_GATING (1UL << 14)

◆ BUS_CLK_GATING0_SD1_GATING

#define BUS_CLK_GATING0_SD1_GATING (1UL << 9)

◆ BUS_CLK_GATING0_SD0_GATING

#define BUS_CLK_GATING0_SD0_GATING (1UL << 8)

◆ BUS_CLK_GATING0_DMA_GATING

#define BUS_CLK_GATING0_DMA_GATING (1UL << 6)

◆ CCU_BUS_CLK_GATE1

#define CCU_BUS_CLK_GATE1 0x064

◆ BUS_CLK_GATING1_DEFE_GATING

#define BUS_CLK_GATING1_DEFE_GATING (1UL << 14)

◆ BUS_CLK_GATING1_DEBE_GATING

#define BUS_CLK_GATING1_DEBE_GATING (1UL << 12)

◆ BUS_CLK_GATING1_TVE_GATING

#define BUS_CLK_GATING1_TVE_GATING (1UL << 10)

◆ BUS_CLK_GATING1_TBD_GATING

#define BUS_CLK_GATING1_TBD_GATING (1UL << 9)

◆ BUS_CLK_GATING1_CSI_GATING

#define BUS_CLK_GATING1_CSI_GATING (1UL << 8)

◆ BUS_CLK_GATING1_DEINTERLACE_GATING

#define BUS_CLK_GATING1_DEINTERLACE_GATING (1UL << 5)

◆ BUS_CLK_GATING1_LCD_GATING

#define BUS_CLK_GATING1_LCD_GATING (1UL << 4)

◆ BUS_CLK_GATING1_VE_GATING

#define BUS_CLK_GATING1_VE_GATING (1UL << 0)

◆ CCU_BUS_CLK_GATE2

#define CCU_BUS_CLK_GATE2 0x068

◆ BUS_CLK_GATING2_UART2_GATING

#define BUS_CLK_GATING2_UART2_GATING (1UL << 22)

◆ BUS_CLK_GATING2_UART1_GATING

#define BUS_CLK_GATING2_UART1_GATING (1UL << 21)

◆ BUS_CLK_GATING2_UART0_GATING

#define BUS_CLK_GATING2_UART0_GATING (1UL << 20)

◆ BUS_CLK_GATING2_TWI2_GATING

#define BUS_CLK_GATING2_TWI2_GATING (1UL << 18)

◆ BUS_CLK_GATING2_TWI1_GATING

#define BUS_CLK_GATING2_TWI1_GATING (1UL << 17)

◆ BUS_CLK_GATING2_TWI0_GATING

#define BUS_CLK_GATING2_TWI0_GATING (1UL << 16)

◆ BUS_CLK_GATING2_RSB_GATING

#define BUS_CLK_GATING2_RSB_GATING (1UL << 3)

◆ BUS_CLK_GATING2_CIR_GATING

#define BUS_CLK_GATING2_CIR_GATING (1UL << 2)

◆ BUS_CLK_GATING2_OWA_GATING

#define BUS_CLK_GATING2_OWA_GATING (1UL << 1)

◆ BUS_CLK_GATING2_AUDIO_CODEC_GATING

#define BUS_CLK_GATING2_AUDIO_CODEC_GATING (1UL << 0)

◆ CCU_SDMMC0_CLK

#define CCU_SDMMC0_CLK 0x088

◆ SDMMC0_CLK_SCLK_GATING

#define SDMMC0_CLK_SCLK_GATING (1UL << 31)

◆ SDMMC0_CLK_CLK_SRC_SEL

#define SDMMC0_CLK_CLK_SRC_SEL (3UL << 24)

◆ SDMMC0_CLK_CLK_SRC_SEL_OSC24M

#define SDMMC0_CLK_CLK_SRC_SEL_OSC24M (0UL << 24)

◆ SDMMC0_CLK_CLK_SRC_SEL_PLL_PERIPH

#define SDMMC0_CLK_CLK_SRC_SEL_PLL_PERIPH (1UL << 24)

◆ __SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR

#define __SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR ( __DLY )

Value:

((__DLY) << 20)

◆ __SDMMC0_CLK_CLK_DIV_RATIO_N

#define __SDMMC0_CLK_CLK_DIV_RATIO_N ( __N )

Value:

((__N) << 16)

◆ __SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR

#define __SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR ( __DLY )

Value:

((__DLY) << 8)

◆ __SDMMC0_CLK_CLK_DIV_RATIO_M

#define __SDMMC0_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR

#define SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR ( ... )

Value:

__SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR((7UL, ##__VA_ARGS__))

__SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR

#define __SDMMC0_CLK_SAMPLE_CLK_PHASE_CTR(__DLY)

Definition f1c100s_reg.h:183

◆ SDMMC0_CLK_CLK_DIV_RATIO_N

#define SDMMC0_CLK_CLK_DIV_RATIO_N ( ... )

Value:

__SDMMC0_CLK_CLK_DIV_RATIO_N((3UL, ##__VA_ARGS__))

__SDMMC0_CLK_CLK_DIV_RATIO_N

#define __SDMMC0_CLK_CLK_DIV_RATIO_N(__N)

Definition f1c100s_reg.h:184

◆ SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR

#define SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR ( ... )

Value:

__SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR((7UL, ##__VA_ARGS__))

__SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR

#define __SDMMC0_CLK_OUTPUT_CLK_PHASE_CTR(__DLY)

Definition f1c100s_reg.h:185

◆ SDMMC0_CLK_CLK_DIV_RATIO_M

#define SDMMC0_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__SDMMC0_CLK_CLK_DIV_RATIO_M((16UL, ##__VA_ARGS__))

__SDMMC0_CLK_CLK_DIV_RATIO_M

#define __SDMMC0_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:186

◆ CCU_SDMMC1_CLK

#define CCU_SDMMC1_CLK 0x08c

◆ SDMMC1_CLK_SCLK_GATING

#define SDMMC1_CLK_SCLK_GATING (1UL << 31)

◆ SDMMC1_CLK_CLK_SRC_SEL

#define SDMMC1_CLK_CLK_SRC_SEL (3UL << 24)

◆ SDMMC1_CLK_CLK_SRC_SEL_OSC24M

#define SDMMC1_CLK_CLK_SRC_SEL_OSC24M (0UL << 24)

◆ SDMMC1_CLK_CLK_SRC_SEL_PLL_PERIPH

#define SDMMC1_CLK_CLK_SRC_SEL_PLL_PERIPH (1UL << 24)

◆ __SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR

#define __SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR ( __DLY )

Value:

((__DLY) << 20)

◆ __SDMMC1_CLK_CLK_DIV_RATIO_N

#define __SDMMC1_CLK_CLK_DIV_RATIO_N ( __N )

Value:

((__N) << 16)

◆ __SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR

#define __SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR ( __DLY )

Value:

((__DLY) << 8)

◆ __SDMMC1_CLK_CLK_DIV_RATIO_M

#define __SDMMC1_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR

#define SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR ( ... )

Value:

__SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR((7UL, ##__VA_ARGS__))

__SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR

#define __SDMMC1_CLK_SAMPLE_CLK_PHASE_CTR(__DLY)

Definition f1c100s_reg.h:200

◆ SDMMC1_CLK_CLK_DIV_RATIO_N

#define SDMMC1_CLK_CLK_DIV_RATIO_N ( ... )

Value:

__SDMMC1_CLK_CLK_DIV_RATIO_N((3UL, ##__VA_ARGS__))

__SDMMC1_CLK_CLK_DIV_RATIO_N

#define __SDMMC1_CLK_CLK_DIV_RATIO_N(__N)

Definition f1c100s_reg.h:201

◆ SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR

#define SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR ( ... )

Value:

__SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR((7UL, ##__VA_ARGS__))

__SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR

#define __SDMMC1_CLK_OUTPUT_CLK_PHASE_CTR(__DLY)

Definition f1c100s_reg.h:202

◆ SDMMC1_CLK_CLK_DIV_RATIO_M

#define SDMMC1_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__SDMMC1_CLK_CLK_DIV_RATIO_M((16UL, ##__VA_ARGS__))

__SDMMC1_CLK_CLK_DIV_RATIO_M

#define __SDMMC1_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:203

◆ CCU_DAUDIO_CLK

#define CCU_DAUDIO_CLK 0x0b0

◆ DAUDIO_CLK_SCLK_GATING

#define DAUDIO_CLK_SCLK_GATING (1UL << 31)

◆ DAUTIO_CLK_CLK_SRC_SEL

#define DAUTIO_CLK_CLK_SRC_SEL (3UL << 16)

◆ DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8X

#define DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8X (0UL << 16)

◆ DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD2

#define DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD2 (1UL << 16)

◆ DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD4

#define DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD4 (2UL << 16)

◆ DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD8

#define DAUTIO_CLK_CLK_SRC_SEL_PLL_AUDIO_8XD8 (3UL << 16)

◆ CCU_OWA_CLK

#define CCU_OWA_CLK 0x0b4

◆ OWA_CLK_SCLK_GATING

#define OWA_CLK_SCLK_GATING (1UL << 31)

◆ OWA_CLK_CLK_SRC_SEL

#define OWA_CLK_CLK_SRC_SEL (3UL << 16)

◆ OWA_CLK_CLK_SRC_SEL_PLL2

#define OWA_CLK_CLK_SRC_SEL_PLL2 (0UL << 16)

◆ OWA_CLK_CLK_SRC_SEL_PLL2D2

#define OWA_CLK_CLK_SRC_SEL_PLL2D2 (1UL << 16)

◆ OWA_CLK_CLK_SRC_SEL_PLL2D4

#define OWA_CLK_CLK_SRC_SEL_PLL2D4 (2UL << 16)

◆ OWA_CLK_CLK_SRC_SEL_PLL2D8

#define OWA_CLK_CLK_SRC_SEL_PLL2D8 (3UL << 16)

◆ CCU_CIR_CLK

#define CCU_CIR_CLK 0x0b8

◆ CIR_CLK_SCLK_GATING

#define CIR_CLK_SCLK_GATING (1UL << 31)

◆ CIR_CLK_CLK_SRC_SEL

#define CIR_CLK_CLK_SRC_SEL (3UL << 24)

◆ CIR_CLK_CLK_SRC_SEL_LOSC

#define CIR_CLK_CLK_SRC_SEL_LOSC (0UL << 24)

◆ CIR_CLK_CLK_SRC_SEL_OSC24M

#define CIR_CLK_CLK_SRC_SEL_OSC24M (1UL << 24)

◆ __CIR_CLK_CLK_DIV_RATION_N

#define __CIR_CLK_CLK_DIV_RATION_N ( __N )

Value:

((__N) << 16)

◆ __CIR_CLK_CLK_DIV_RATION_M

#define __CIR_CLK_CLK_DIV_RATION_M ( __M )

Value:

(((__M) - 1) << 0)

◆ CIR_CLK_CLK_DIV_RATION_N

#define CIR_CLK_CLK_DIV_RATION_N ( ... )

Value:

__CIR_CLK_CLK_DIV_RATION_N((3UL, ##__VA_ARGS__))

__CIR_CLK_CLK_DIV_RATION_N

#define __CIR_CLK_CLK_DIV_RATION_N(__N)

Definition f1c100s_reg.h:231

◆ CIR_CLK_CLK_DIV_RATION_M

#define CIR_CLK_CLK_DIV_RATION_M ( ... )

Value:

__CIR_CLK_CLK_DIV_RATION_M((16UL, ##__VA_ARGS__))

__CIR_CLK_CLK_DIV_RATION_M

#define __CIR_CLK_CLK_DIV_RATION_M(__M)

Definition f1c100s_reg.h:232

◆ CCU_USBPHY_CLK

#define CCU_USBPHY_CLK 0x0cc

◆ USBPHY_CLK_SCLK_GATING

#define USBPHY_CLK_SCLK_GATING (1UL << 1)

◆ USBPHY_CLK_USBPHY_RST

#define USBPHY_CLK_USBPHY_RST (1UL << 0)

◆ CCU_DRAM_GATING

#define CCU_DRAM_GATING 0x100

◆ DRAM_GATING_BE_DCLK_GATING

#define DRAM_GATING_BE_DCLK_GATING (1UL << 26)

◆ DRAM_GATING_FE_DCLK_GATING

#define DRAM_GATING_FE_DCLK_GATING (1UL << 24)

◆ DRAM_GATING_TVD_DCLK_GATING

#define DRAM_GATING_TVD_DCLK_GATING (1UL << 3)

◆ DRAM_GATING_DEINTERLACE_DCLK_GATING

#define DRAM_GATING_DEINTERLACE_DCLK_GATING (1UL << 2)

◆ DRAM_GATING_CSI_DCLK_GATING

#define DRAM_GATING_CSI_DCLK_GATING (1UL << 1)

◆ DRAM_GATING_VE_DCLK_GATING

#define DRAM_GATING_VE_DCLK_GATING (1UL << 0)

◆ CCU_BE_CLK

#define CCU_BE_CLK 0x104

◆ BE_CLK_SCLK_GATING

#define BE_CLK_SCLK_GATING (1UL << 31)

◆ BE_CLK_CLK_SRC_SEL

#define BE_CLK_CLK_SRC_SEL (3UL << 24)

◆ BE_CLK_CLK_SRC_SEL_PLL_VIDEO

#define BE_CLK_CLK_SRC_SEL_PLL_VIDEO (0UL << 24)

◆ BE_CLK_CLK_SRC_SEL_PLL_PERIPH

#define BE_CLK_CLK_SRC_SEL_PLL_PERIPH (2UL << 24)

◆ __BE_CLK_CLK_DIV_RATIO_M

#define __BE_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ BE_CLK_CLK_DIV_RATIO_M

#define BE_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__BE_CLK_CLK_DIV_RATIO_M((16, ##__VA_ARGS__))

__BE_CLK_CLK_DIV_RATIO_M

#define __BE_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:252

◆ CCU_FE_CLK

#define CCU_FE_CLK 0x10c

◆ FE_CLK_SCLK_GATING

#define FE_CLK_SCLK_GATING (1UL << 31)

◆ FE_CLK_CLK_SRC_SEL

#define FE_CLK_CLK_SRC_SEL (3UL << 24)

◆ FE_CLK_CLK_SRC_SEL_PLL_VIDEO

#define FE_CLK_CLK_SRC_SEL_PLL_VIDEO (0UL << 24)

◆ FE_CLK_CLK_SRC_SEL_PLL_PERIPH

#define FE_CLK_CLK_SRC_SEL_PLL_PERIPH (2UL << 24)

◆ __FE_CLK_CLK_DIV_RATIO_M

#define __FE_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ FE_CLK_CLK_DIV_RATIO_M

#define FE_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__FE_CLK_CLK_DIV_RATIO_M((16, ##__VA_ARGS__))

__FE_CLK_CLK_DIV_RATIO_M

#define __FE_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:260

◆ CCU_TCON_CLK

#define CCU_TCON_CLK 0x118

◆ TCON_CLK_SCLK_GATING

#define TCON_CLK_SCLK_GATING (1UL << 31)

◆ TCON_CLK_CLK_SRC_SEL

#define TCON_CLK_CLK_SRC_SEL (7UL << 24)

◆ TCON_CLK_CLK_SRC_SEL_PLL_VIDEO_1X

#define TCON_CLK_CLK_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

◆ TCON_CLK_CLK_SRC_SEL_PLL_VIDEO_2X

#define TCON_CLK_CLK_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

◆ CCU_DI_CLK

#define CCU_DI_CLK 0x11c

◆ DI_CLK_SCLK_GATING

#define DI_CLK_SCLK_GATING (1UL << 31)

◆ DI_CLK_CLK_SRC_SEL

#define DI_CLK_CLK_SRC_SEL (7UL << 24)

◆ DI_CLK_CLK_SRC_SEL_PLL_VIDEO_1X

#define DI_CLK_CLK_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

◆ DI_CLK_CLK_SRC_SEL_PLL_VIDEO_2X

#define DI_CLK_CLK_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

◆ __DI_CLK_CLK_DIV_RATIO_M

#define __DI_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ DI_CLK_CLK_DIV_RATIO_M

#define DI_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__DI_CLK_CLK_DIV_RATIO_M((16UL, ##__VA_ARGS__))

__DI_CLK_CLK_DIV_RATIO_M

#define __DI_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:273

◆ CCU_TVE_CLK

#define CCU_TVE_CLK 0x120

◆ TVE_CLK_SCLK2_GATING

#define TVE_CLK_SCLK2_GATING (1UL << 31)

◆ TVE_CLK_SCLK2_SRC_SEL

#define TVE_CLK_SCLK2_SRC_SEL (7UL << 24)

◆ TVE_CLK_SCLK2_SRC_SEL_PLL_VIDEO_1X

#define TVE_CLK_SCLK2_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

◆ TVE_CLK_SCLK2_SRC_SEL_PLL_VIDEO_2X

#define TVE_CLK_SCLK2_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

◆ TVE_CLK_SCLK1_GATING

#define TVE_CLK_SCLK1_GATING (1UL << 15)

◆ TVE_CLK_SCLK1_SRC_SEL

#define TVE_CLK_SCLK1_SRC_SEL (1UL << 8)

◆ TVE_CLK_SCLK1_SRC_SEL_TVE_SCLK2

#define TVE_CLK_SCLK1_SRC_SEL_TVE_SCLK2 (0UL << 8)

◆ TVE_CLK_SCLK1_SRC_SEL_TVE_SCLK2_D2

#define TVE_CLK_SCLK1_SRC_SEL_TVE_SCLK2_D2 (1UL << 8)

◆ __TVE_CLK_CLK_DIV_RATIO_M

#define __TVE_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ TVE_CLK_CLK_DIV_RATIO_M

#define TVE_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__TVE_CLK_CLK_DIV_RATIO_M((16UL, ##__VA_ARGS__))

__TVE_CLK_CLK_DIV_RATIO_M

#define __TVE_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:285

◆ CCU_TVD_CLK

#define CCU_TVD_CLK 0x124

◆ TVD_CLK_SCLK_GATING

#define TVD_CLK_SCLK_GATING (1UL << 31)

◆ TVD_CLK_CLK_SRC_SEL

#define TVD_CLK_CLK_SRC_SEL (7UL << 24)

◆ TVD_CLK_CLK_SRC_SEL_PLL_VIDEO_1X

#define TVD_CLK_CLK_SRC_SEL_PLL_VIDEO_1X (0UL << 24)

◆ TVD_CLK_CLK_SRC_SEL_OSC24M

#define TVD_CLK_CLK_SRC_SEL_OSC24M (1UL << 24)

◆ TVD_CLK_CLK_SRC_SEL_PLL_VIDEO_2X

#define TVD_CLK_CLK_SRC_SEL_PLL_VIDEO_2X (2UL << 24)

◆ __TVD_CLK_CLK_DIV_RATIO_M

#define __TVD_CLK_CLK_DIV_RATIO_M ( __M )

Value:

(((__M) - 1) << 0)

◆ TVD_CLK_CLK_DIV_RATIO_M

#define TVD_CLK_CLK_DIV_RATIO_M ( ... )

Value:

__TVD_CLK_CLK_DIV_RATIO_M((16UL, ##__VA_ARGS__))

__TVD_CLK_CLK_DIV_RATIO_M

#define __TVD_CLK_CLK_DIV_RATIO_M(__M)

Definition f1c100s_reg.h:294

◆ CCU_CSI_CLK

#define CCU_CSI_CLK 0x134

◆ CSI_CLK_CSI_MCLK_GATING

#define CSI_CLK_CSI_MCLK_GATING (1UL << 15)

◆ CSI_CLK_MCLK_SRC_SEL

#define CSI_CLK_MCLK_SRC_SEL (7UL << 8)

◆ CSI_CLK_MCLK_SRC_SEL_PLL_VIDEO_1X

#define CSI_CLK_MCLK_SRC_SEL_PLL_VIDEO_1X (0UL << 8)

◆ CSI_CLK_MCLK_SRC_SEL_OSC24M

#define CSI_CLK_MCLK_SRC_SEL_OSC24M (5UL << 8)

◆ __CSI_CLK_CLSI_MCLK_DIV_M

#define __CSI_CLK_CLSI_MCLK_DIV_M ( __M )

Value:

(((__M( - 1) << 0)

◆ CSI_CLK_CLSI_MCLK_DIV_M

#define CSI_CLK_CLSI_MCLK_DIV_M ( ... )

Value:

__CSI_CLK_CLSI_MCLK_DIV_M((16UL, ##__VA_ARGS__))

__CSI_CLK_CLSI_MCLK_DIV_M

#define __CSI_CLK_CLSI_MCLK_DIV_M(__M)

Definition f1c100s_reg.h:302

◆ CCU_VE_CLK

#define CCU_VE_CLK 0x13c

◆ VE_CLK_SCLK_GATING

#define VE_CLK_SCLK_GATING (1UL << 31)

◆ CCU_AUDIO_CODEC_CLK

#define CCU_AUDIO_CODEC_CLK 0x140

◆ AUDIO_CODEC_CLK_SCLK_GATING

#define AUDIO_CODEC_CLK_SCLK_GATING (1UL << 31)

◆ CCU_AVS_CLK

#define CCU_AVS_CLK 0x144

◆ AVS_CLK_SCLK_GATING

#define AVS_CLK_SCLK_GATING (1UL << 31)

◆ CCU_PLL_STABLE_TIME0

#define CCU_PLL_STABLE_TIME0 0x200

◆ __PLL_STABLE_TIME0_PLL_LOCK_TIME

#define __PLL_STABLE_TIME0_PLL_LOCK_TIME ( __T )

Value:

((__T) << 0)

◆ PLL_STABLE_TIME0_PLL_LOCK_TIME

#define PLL_STABLE_TIME0_PLL_LOCK_TIME ( ... )

Value:

__PLL_STABLE_TIME0_PLL_LOCK_TIME((0xFFFFUL, ##__VA_ARGS__))

__PLL_STABLE_TIME0_PLL_LOCK_TIME

#define __PLL_STABLE_TIME0_PLL_LOCK_TIME(__T)

Definition f1c100s_reg.h:312

◆ CCU_PLL_STABLE_TIME1

#define CCU_PLL_STABLE_TIME1 0x204

◆ __PLL_STABLE_TIME1_PLL_LOCK_TIME

#define __PLL_STABLE_TIME1_PLL_LOCK_TIME ( __T )

Value:

((__T) << 0)

◆ PLL_STABLE_TIME1_PLL_LOCK_TIME

#define PLL_STABLE_TIME1_PLL_LOCK_TIME ( ... )

Value:

__PLL_STABLE_TIME1_PLL_LOCK_TIME((0xFFFFUL, ##__VA_ARGS__))

__PLL_STABLE_TIME1_PLL_LOCK_TIME

#define __PLL_STABLE_TIME1_PLL_LOCK_TIME(__T)

Definition f1c100s_reg.h:316

◆ CCU_PLL_CPU_BIAS

#define CCU_PLL_CPU_BIAS 0x220

◆ CCU_PLL_AUDIO_BIAS

#define CCU_PLL_AUDIO_BIAS 0x224

◆ CCU_PLL_VIDEO_BIAS

#define CCU_PLL_VIDEO_BIAS 0x228

◆ CCU_PLL_VE_BIAS

#define CCU_PLL_VE_BIAS 0x22c

◆ CCU_PLL_DDR0_BIAS

#define CCU_PLL_DDR0_BIAS 0x230

◆ CCU_PLL_PERIPH_BIAS

#define CCU_PLL_PERIPH_BIAS 0x234

◆ CCU_PLL_CPU_TUN

#define CCU_PLL_CPU_TUN 0x250

◆ CCU_PLL_DDR_TUN

#define CCU_PLL_DDR_TUN 0x260

◆ CCU_PLL_AUDIO_PAT_CTRL

#define CCU_PLL_AUDIO_PAT_CTRL 0x284

◆ CCU_PLL_VIDEO_PAT_CTRL

#define CCU_PLL_VIDEO_PAT_CTRL 0x288

◆ CCU_PLL_DDR_PAT_CTRL

#define CCU_PLL_DDR_PAT_CTRL 0x290

◆ CCU_BUS_SOFT_RST0

#define CCU_BUS_SOFT_RST0 0x2c0

◆ BUS_SOFT_RST0_USBOTG_RST

#define BUS_SOFT_RST0_USBOTG_RST (1UL << 24)

◆ BUS_SOFT_RST0_SPI1_RST

#define BUS_SOFT_RST0_SPI1_RST (1UL << 21)

◆ BUS_SOFT_RST0_SPI0_RST

#define BUS_SOFT_RST0_SPI0_RST (1UL << 20)

◆ BUS_SOFT_RST0_SDRAM_RST

#define BUS_SOFT_RST0_SDRAM_RST (1UL << 14)

◆ BUS_SOFT_RST0_SD1_RST

#define BUS_SOFT_RST0_SD1_RST (1UL << 9)

◆ BUS_SOFT_RST0_SD0_RST

#define BUS_SOFT_RST0_SD0_RST (1UL << 8)

◆ BUS_SOFT_RST0_DMA_RST

#define BUS_SOFT_RST0_DMA_RST (1UL << 6)

◆ CCU_BUS_SOFT_RST1

#define CCU_BUS_SOFT_RST1 0x2c4

◆ BUS_SOFT_RST1_DEFE_RST

#define BUS_SOFT_RST1_DEFE_RST (1UL << 14)

◆ BUS_SOFT_RST1_DEBE_RST

#define BUS_SOFT_RST1_DEBE_RST (1UL << 12)

◆ BUS_SOFT_RST1_TVE_RST

#define BUS_SOFT_RST1_TVE_RST (1UL << 10)

◆ BUS_SOFT_RST1_RVD_RST

#define BUS_SOFT_RST1_RVD_RST (1UL << 9)

◆ BUS_SOFT_RST1_CSI_RST

#define BUS_SOFT_RST1_CSI_RST (1UL << 8)

◆ BUS_SOFT_RST1_DEINTERLACE_RST

#define BUS_SOFT_RST1_DEINTERLACE_RST (1UL << 5)

◆ BUS_SOFT_RST1_LCD_RST

#define BUS_SOFT_RST1_LCD_RST (1UL << 4)

◆ BUS_SOFT_RST1_VE_RST

#define BUS_SOFT_RST1_VE_RST (1UL << 0)

◆ CCU_BUS_SOFT_RST2

#define CCU_BUS_SOFT_RST2 0x2d0

◆ BUS_SOFT_RST2_UART2_RST

#define BUS_SOFT_RST2_UART2_RST (1UL << 22)

◆ BUS_SOFT_RST2_UART1_RST

#define BUS_SOFT_RST2_UART1_RST (1UL << 21)

◆ BUS_SOFT_RST2_UART0_RST

#define BUS_SOFT_RST2_UART0_RST (1UL << 20)

◆ BUS_SOFT_RST2_TWI2_RST

#define BUS_SOFT_RST2_TWI2_RST (1UL << 18)

◆ BUS_SOFT_RST2_TWI1_RST

#define BUS_SOFT_RST2_TWI1_RST (1UL << 17)

◆ BUS_SOFT_RST2_TWI0_RST

#define BUS_SOFT_RST2_TWI0_RST (1UL << 16)

◆ BUS_SOFT_RST2_DAUDIO_RST

#define BUS_SOFT_RST2_DAUDIO_RST (1UL << 12)

◆ BUS_SOFT_RST2_RSB_RST

#define BUS_SOFT_RST2_RSB_RST (1UL << 3)

◆ BUS_SOFT_RST2_CIR_RST

#define BUS_SOFT_RST2_CIR_RST (1UL << 2)

◆ BUS_SOFT_RST2_OWA_RST

#define BUS_SOFT_RST2_OWA_RST (1UL << 1)

◆ BUS_SOFT_RST2_AUDIO_CODEC_RST

#define BUS_SOFT_RST2_AUDIO_CODEC_RST (1UL << 0)

◆ DRAM_BASE

#define DRAM_BASE ((dram_reg_t *)0x01c01000)

◆ DRAM_SCONR

#define DRAM_SCONR 0x000

◆ DRAM_STMG0R

#define DRAM_STMG0R 0x004

◆ DRAM_STMG1R

#define DRAM_STMG1R 0x008

◆ DRAM_SCTLR

#define DRAM_SCTLR 0x00c

◆ DRAM_SREFR

#define DRAM_SREFR 0x010

◆ DRAM_SEXTMR

#define DRAM_SEXTMR 0x014

◆ DRAM_DDLYR

#define DRAM_DDLYR 0x024

◆ DRAM_DADRR

#define DRAM_DADRR 0x028

◆ DRAM_DVALR

#define DRAM_DVALR 0x02c

◆ DRAM_DRPTR0

#define DRAM_DRPTR0 0x030

◆ DRAM_DRPTR1

#define DRAM_DRPTR1 0x034

◆ DRAM_DRPTR2

#define DRAM_DRPTR2 0x038

◆ DRAM_DRPTR3

#define DRAM_DRPTR3 0x03c

◆ DRAM_SEFR

#define DRAM_SEFR 0x040

◆ DRAM_MAE

#define DRAM_MAE 0x044

◆ DRAM_ASPR

#define DRAM_ASPR 0x048

◆ DRAM_SDLY0

#define DRAM_SDLY0 0x04C

◆ DRAM_SDLY1

#define DRAM_SDLY1 0x050

◆ DRAM_SDLY2

#define DRAM_SDLY2 0x054

◆ DRAM_MCR0

#define DRAM_MCR0 0x100

◆ DRAM_MCR1

#define DRAM_MCR1 0x104

◆ DRAM_MCR2

#define DRAM_MCR2 0x108

◆ DRAM_MCR3

#define DRAM_MCR3 0x10c

◆ DRAM_MCR4

#define DRAM_MCR4 0x110

◆ DRAM_MCR5

#define DRAM_MCR5 0x114

◆ DRAM_MCR6

#define DRAM_MCR6 0x118

◆ DRAM_MCR7

#define DRAM_MCR7 0x11c

◆ DRAM_MCR8

#define DRAM_MCR8 0x120

◆ DRAM_MCR9

#define DRAM_MCR9 0x124

◆ DRAM_MCR10

#define DRAM_MCR10 0x128

◆ DRAM_MCR11

#define DRAM_MCR11 0x12c

◆ DRAM_BWCR

#define DRAM_BWCR 0x140

◆ PIO_BASE

#define PIO_BASE ((pio_reg_t *)0x01c20800)

◆ UART0_BASE

#define UART0_BASE ((uart_reg_t *)0x01c25000)

◆ UART1_BASE

#define UART1_BASE ((uart_reg_t *)0x01c25400)

◆ UART2_BASE

#define UART2_BASE ((uart_reg_t *)0x01c25800)

◆ UART_RBR

#define UART_RBR 0x000

◆ UART_THR

#define UART_THR 0x000

◆ UART_DLL

#define UART_DLL 0x000

◆ UART_DLH

#define UART_DLH 0x004

◆ UART_IER

#define UART_IER 0x004

◆ IER_PTIME

#define IER_PTIME (1UL << 7)

◆ IER_EDSSI

#define IER_EDSSI (1UL << 3)

◆ IER_ELSI

#define IER_ELSI (1UL << 2)

◆ IER_ETBEI

#define IER_ETBEI (1UL << 1)

◆ IER_ERBFI

#define IER_ERBFI (1UL << 0)

◆ UART_IIR

#define UART_IIR 0x008

◆ UART_FCR

#define UART_FCR 0x008

◆ FCR_RT

#define FCR_RT (3UL << 6)

◆ FCR_RT_1

#define FCR_RT_1 (0UL << 6)

◆ FCR_RT_QUARTER

#define FCR_RT_QUARTER (1UL << 6)

◆ FCR_RT_HALF

#define FCR_RT_HALF (2UL << 6)

◆ FCR_RT_2_LESS

#define FCR_RT_2_LESS (3UL << 6)

◆ FCR_TFT

#define FCR_TFT (3UL << 4)

◆ FCR_TFT_EMPTY

#define FCR_TFT_EMPTY (0UL << 4)

◆ FCR_TFT_2

#define FCR_TFT_2 (1UL << 4)

◆ FCR_TFT_QUARTER

#define FCR_TFT_QUARTER (2UL << 4)

◆ FCR_TFT_HALF

#define FCR_TFT_HALF (3UL << 4)

◆ FCR_DMAM

#define FCR_DMAM (1UL << 3)

◆ FCR_XFIFOR

#define FCR_XFIFOR (1UL << 2)

◆ FCR_RFIFOR

#define FCR_RFIFOR (1UL << 1)

◆ FCR_FIFOE

#define FCR_FIFOE (1UL << 0)

◆ UART_LCR

#define UART_LCR 0x00c

◆ LCR_DLAB

#define LCR_DLAB (1UL << 7)

◆ LCR_BC

#define LCR_BC (1UL << 6)

◆ LCR_EPS

#define LCR_EPS (3UL << 4)

◆ LCR_EPS_ODD

#define LCR_EPS_ODD (0UL << 4)

◆ LCR_EPS_EVEN

#define LCR_EPS_EVEN (1UL << 4)

◆ LCR_PEN

#define LCR_PEN (1UL << 3)

◆ LCR_STOP

#define LCR_STOP (1UL << 2)

◆ LCR_STOP_1

#define LCR_STOP_1 (0UL << 2)

◆ LCR_STOP_2

#define LCR_STOP_2 (1UL << 2)

◆ LCR_DLS

#define LCR_DLS (3UL << 0)

◆ LCR_DLS_5

#define LCR_DLS_5 (0UL << 0)

◆ LCR_DLS_6

#define LCR_DLS_6 (1UL << 0)

◆ LCR_DLS_7

#define LCR_DLS_7 (2UL << 0)

◆ LCR_DLS_8

#define LCR_DLS_8 (3UL << 0)

◆ UART_MCR

#define UART_MCR 0x010

◆ MCR_SIRE

#define MCR_SIRE (1UL << 6)

◆ MCR_AFCE

#define MCR_AFCE (1UL << 5)

◆ MCR_LOOP

#define MCR_LOOP (1UL << 4)

◆ MCR_RTS

#define MCR_RTS (1UL << 1)

◆ MCR_DTR

#define MCR_DTR (1UL << 0)

◆ UART_LSR

#define UART_LSR 0x014

◆ UART_MSR

#define UART_MSR 0x018

◆ UART_SCH

#define UART_SCH 0x01c

◆ UART_USR

#define UART_USR 0x07c

◆ USR_RFF

#define USR_RFF (1UL << 4)

◆ USR_RFNE

#define USR_RFNE (1UL << 3)

◆ USR_TFE

#define USR_TFE (1UL << 2)

◆ USR_TFNF

#define USR_TFNF (1UL << 1)

◆ USR_BUSY

#define USR_BUSY (1UL << 0)

◆ UART_TFL

#define UART_TFL 0x080

◆ UART_RFL

#define UART_RFL 0x084

◆ UART_HALT

#define UART_HALT 0x0a4

◆ SPI0_BASE

#define SPI0_BASE ((spi_reg_t *)0x01c05000)

◆ SPI1_BASE

#define SPI1_BASE ((spi_reg_t *)0x01c06000)

◆ SPI_GCR

#define SPI_GCR 0x004

◆ GCR_EN

#define GCR_EN (1UL << 0)

◆ GCR_MODE

#define GCR_MODE (1UL << 1)

◆ GCR_MODE_MASTE

#define GCR_MODE_MASTE (1UL << 1)

◆ GCR_MODE_SLAVE

#define GCR_MODE_SLAVE (0UL << 1)

◆ GCR_TP_EN

#define GCR_TP_EN (1UL << 7)

◆ GCR_SRST

#define GCR_SRST (1UL << 31)

◆ SPI_TCR

#define SPI_TCR 0x008

◆ __TCR_CPHA

#define __TCR_CPHA ( __CPHA )

Value:

((__CPHA) << 0)

◆ __TCR_CPOL

#define __TCR_CPOL ( __CPOL )

Value:

(((__CPOL) ^ 1) << 1)

◆ __TCR_SPOL

#define __TCR_SPOL ( __SPOL )

Value:

(((__SPOL) ^ 1) << 2)

◆ TCR_CPHA

#define TCR_CPHA ( ... )

Value:

__TCR_CPHA((1, ##__VA_ARGS__))

__TCR_CPHA

#define __TCR_CPHA(__CPHA)

Definition f1c100s_reg.h:478

◆ TCR_CPOL

#define TCR_CPOL ( ... )

Value:

__TCR_CPOL((0, ##__VA_ARGS__))

__TCR_CPOL

#define __TCR_CPOL(__CPOL)

Definition f1c100s_reg.h:479

◆ TCR_SPOL

#define TCR_SPOL ( ... )

Value:

__TCR_SPOL((0, ##__VA_ARGS__))

__TCR_SPOL

#define __TCR_SPOL(__SPOL)

Definition f1c100s_reg.h:480

◆ TCR_SSCTL

#define TCR_SSCTL (1UL << 3)

◆ __TCR_SS_SEL

#define __TCR_SS_SEL ( __SEL )

Value:

((__SEL) << 4)

◆ TCR_SS_SEL

#define TCR_SS_SEL ( ... )

Value:

__TCR_SS_SEL((3, ##__VA_ARGS__))

__TCR_SS_SEL

#define __TCR_SS_SEL(__SEL)

Definition f1c100s_reg.h:488

◆ TCR_SS_OWNER

#define TCR_SS_OWNER (1UL << 6)

◆ TCR_SS_OWNER_SPI

#define TCR_SS_OWNER_SPI (0UL << 6)

◆ TCR_SS_OWNER_SOFTWARE

#define TCR_SS_OWNER_SOFTWARE (1UL << 6)

◆ __TCR_SS_LEVEL

#define __TCR_SS_LEVEL ( __LVL )

Value:

((__LVL) << 7)

◆ TCR_SS_LEVEL

#define TCR_SS_LEVEL ( ... )

Value:

__TCR_SS_LEVEL((1, ##__VA_ARGS__))

__TCR_SS_LEVEL

#define __TCR_SS_LEVEL(__LVL)

Definition f1c100s_reg.h:494

◆ TCR_DHB

#define TCR_DHB (1UL << 8)

◆ TCR_DDB

#define TCR_DDB (1UL << 9)

◆ TCR_RPSM

#define TCR_RPSM (1UL << 10)

◆ TCR_RPSM_NORMAL

#define TCR_RPSM_NORMAL (0UL << 10)

◆ TCR_RPSM_RAPID

#define TCR_RPSM_RAPID (1UL << 10)

◆ TCR_SDC

#define TCR_SDC (1UL << 11)

◆ TCR_FBS

#define TCR_FBS (1UL << 12)

◆ TCR_FBS_MSB_FIRST

#define TCR_FBS_MSB_FIRST (0UL << 12)

◆ TCR_FBS_LSB_FIRST

#define TCR_FBS_LSB_FIRST (1UL << 12)

◆ TCR_SDM

#define TCR_SDM (1UL << 13)

◆ TCR_XCH

#define TCR_XCH (1UL << 31)

◆ SPI_IER

#define SPI_IER 0x010

◆ SPI_ISR

#define SPI_ISR 0x014

◆ SPI_FCR

#define SPI_FCR 0x018

◆ FCR_RX_TRIG_LEVEL

#define FCR_RX_TRIG_LEVEL ( __LVL )

Value:

((__LVL) << 0)

◆ FCR_RF_DRQ_EN

#define FCR_RF_DRQ_EN (1UL << 8)

◆ FCR_RX_DMA_MODE

#define FCR_RX_DMA_MODE (1UL << 9)

◆ FCR_RX_DMA_MODE_NORMAL

#define FCR_RX_DMA_MODE_NORMAL (0UL << 9)

◆ FCR_RX_DMA_MODE_DEDICATE

#define FCR_RX_DMA_MODE_DEDICATE (1UL << 9)

◆ FCR_RX_FIFO_ACCESS_SIZE

#define FCR_RX_FIFO_ACCESS_SIZE (3UL << 10)

◆ FCR_RX_FIFO_ACCESS_SIZE_BYTE

#define FCR_RX_FIFO_ACCESS_SIZE_BYTE (0UL << 10)

◆ FCR_RX_FIFO_ACCESS_SIZE_WORD

#define FCR_RX_FIFO_ACCESS_SIZE_WORD (1UL << 10)

◆ FCR_RX_FIFO_ACCESS_SIZE_BY_BUS

#define FCR_RX_FIFO_ACCESS_SIZE_BY_BUS (3UL << 10)

◆ FCR_RF_TEST

#define FCR_RF_TEST (1UL << 14)

◆ FCR_RF_RST

#define FCR_RF_RST (1UL << 15)

◆ FCR_TX_TRIG_LEVEL

#define FCR_TX_TRIG_LEVEL ( __LVL )

Value:

((__LVL) << 16)

◆ FCR_TX_FIFO_ACCESS_SIZE

#define FCR_TX_FIFO_ACCESS_SIZE (3UL << 26)

◆ FCR_TX_FIFO_ACCESS_SIZE_BYTE

#define FCR_TX_FIFO_ACCESS_SIZE_BYTE (0UL << 26)

◆ FCR_TX_FIFO_ACCESS_SIZE_WORD

#define FCR_TX_FIFO_ACCESS_SIZE_WORD (1UL << 26)

◆ FCR_TX_FIFO_ACCESS_SIZE_BY_BUS

#define FCR_TX_FIFO_ACCESS_SIZE_BY_BUS (3UL << 26)

◆ FCR_TF_TEST

#define FCR_TF_TEST (1UL << 30)

◆ FCR_TF_RST

#define FCR_TF_RST (1UL << 31)

◆ SPI_FSR

#define SPI_FSR 0x01c

◆ SPI_WCR

#define SPI_WCR 0x020

◆ SPI_CCR

#define SPI_CCR 0x024

◆ CCR_CDR2

#define CCR_CDR2 ( __N )

Value:

((__N) << 0)

◆ CCR_CDR1

#define CCR_CDR1 ( _N )

Value:

((__N) << 8)

◆ CCR_DRS

#define CCR_DRS (1UL << 12)

◆ CCR_DRS_CDR1

#define CCR_DRS_CDR1 (0UL << 12)

◆ CCR_DRS_CDR2

#define CCR_DRS_CDR2 (1UL << 12)

◆ SPI_MBC

#define SPI_MBC 0x030

◆ SPI_MTC

#define SPI_MTC 0x034

◆ SPI_BCC

#define SPI_BCC 0x038

◆ SPI_TXD

#define SPI_TXD 0x200

◆ SPI_RXD

#define SPI_RXD 0x300

◆ TCON_BASE

#define TCON_BASE ((tcon_reg_t *)0x01C0C000)

◆ TCON_CTRL

#define TCON_CTRL 0x000

◆ TCON_CTRL_MODULE_EN

#define TCON_CTRL_MODULE_EN (1UL << 31)

◆ TCON_CTRL_IO_MAP_SEL

#define TCON_CTRL_IO_MAP_SEL (1UL << 0)

◆ TCON_CTRL_IO_MAP_SEL_TCON0

#define TCON_CTRL_IO_MAP_SEL_TCON0 (0UL << 0)

◆ TCON_CTRL_IO_MAP_SEL_TCON1

#define TCON_CTRL_IO_MAP_SEL_TCON1 (1UL << 0)

◆ TCON_INT_REG0

#define TCON_INT_REG0 0x004

◆ TCON_INT_REG1

#define TCON_INT_REG1 0x008

◆ TCON_FRM_CTRL

#define TCON_FRM_CTRL 0x010

◆ TCON_FRM_CTRL_TCON0_FRM_EN

#define TCON_FRM_CTRL_TCON0_FRM_EN (1UL << 31)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_R

#define TCON_FRM_CTRL_TCON0_FRM_MODE_R (1UL << 6)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_R6

#define TCON_FRM_CTRL_TCON0_FRM_MODE_R6 (0UL << 6)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_R5

#define TCON_FRM_CTRL_TCON0_FRM_MODE_R5 (1UL << 6)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_G

#define TCON_FRM_CTRL_TCON0_FRM_MODE_G (1UL << 5)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_G6

#define TCON_FRM_CTRL_TCON0_FRM_MODE_G6 (0UL << 5)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_G5

#define TCON_FRM_CTRL_TCON0_FRM_MODE_G5 (1UL << 5)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_B

#define TCON_FRM_CTRL_TCON0_FRM_MODE_B (1UL << 4)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_B6

#define TCON_FRM_CTRL_TCON0_FRM_MODE_B6 (0UL << 4)

◆ TCON_FRM_CTRL_TCON0_FRM_MODE_B5

#define TCON_FRM_CTRL_TCON0_FRM_MODE_B5 (1UL << 4)

◆ TCON_FRM_SEED0_R

#define TCON_FRM_SEED0_R 0x014

◆ TCON_FRM_SEED0_G

#define TCON_FRM_SEED0_G 0x018

◆ TCON_FRM_SEED0_B

#define TCON_FRM_SEED0_B 0x01c

◆ TCON_FRM_SEED1_R

#define TCON_FRM_SEED1_R 0x020

◆ TCON_FRM_SEED1_G

#define TCON_FRM_SEED1_G 0x024

◆ TCON_FRM_SEED1_B

#define TCON_FRM_SEED1_B 0x028

◆ TCON_FRM_TBL0

#define TCON_FRM_TBL0 0x02c

◆ TCON_FRM_TBL1

#define TCON_FRM_TBL1 0x030

◆ TCON_FRM_TBL2

#define TCON_FRM_TBL2 0x034

◆ TCON_FRM_TBL3

#define TCON_FRM_TBL3 0x038

◆ TCON0_CTRL

#define TCON0_CTRL 0x040

◆ TCON0_CTRL_EN

#define TCON0_CTRL_EN (1UL << 31)

◆ TCON0_CTRL_IF

#define TCON0_CTRL_IF (3UL << 24)

◆ TCON0_CTRL_IF_HV

#define TCON0_CTRL_IF_HV (0UL << 24)

◆ TCON0_CTRL_IF_8080

#define TCON0_CTRL_IF_8080 (1UL << 24)

◆ TCON0_CTRL_RBG_GBR

#define TCON0_CTRL_RBG_GBR (1UL << 23)

◆ __TCON0_CTRL_STA_DLY

#define __TCON0_CTRL_STA_DLY ( __DLY )

Value:

((__DLY) << 4)

◆ TCON0_CTRL_STA_DLY

#define TCON0_CTRL_STA_DLY ( ... )

Value:

__TCON0_CTRL_STA_DLY((0x1FUL, ##__VA_ARGS__))

__TCON0_CTRL_STA_DLY

#define __TCON0_CTRL_STA_DLY(__DLY)

Definition f1c100s_reg.h:579

◆ TCON0_CLK_CTRL

#define TCON0_CLK_CTRL 0x044

◆ TCON0_CLK_CTRL_LCKL_EN

#define TCON0_CLK_CTRL_LCKL_EN (0xFUL << 28)

◆ __TCON0_CLK_CTRL_DCLKDIV

#define __TCON0_CLK_CTRL_DCLKDIV ( __DIV )

Value:

((__DIV) << 0)

◆ TCON0_CLK_CTRL_DCLKDIV

#define TCON0_CLK_CTRL_DCLKDIV ( ... )

Value:

__TCON0_CLK_CTRL_DCLKDIV((255UL, ##__VA_ARGS__))

__TCON0_CLK_CTRL_DCLKDIV

#define __TCON0_CLK_CTRL_DCLKDIV(__DIV)

Definition f1c100s_reg.h:584

◆ TCON0_BASIC_TIMING0

#define TCON0_BASIC_TIMING0 0x048

◆ TCON0_BASIC_TIMING1

#define TCON0_BASIC_TIMING1 0x04c

◆ TCON0_BASIC_TIMING2

#define TCON0_BASIC_TIMING2 0x050

◆ TCON0_BASIC_TIMING3

#define TCON0_BASIC_TIMING3 0x054

◆ TCON0_HV_TIMING

#define TCON0_HV_TIMING 0x058

◆ TCON0_CPU_IF

#define TCON0_CPU_IF 0x060

◆ TCON0_CPU_WR

#define TCON0_CPU_WR 0x064

◆ TCON0_CPU_RD

#define TCON0_CPU_RD 0x068

◆ TCON0_CPU_RD_NX

#define TCON0_CPU_RD_NX 0x06c

◆ TCON0_IO_CTRL0

#define TCON0_IO_CTRL0 0x088

◆ TCON0_IO_CTRL0_DCLK_SEL

#define TCON0_IO_CTRL0_DCLK_SEL (3UL << 28)

◆ TCON0_IO_CTRL0_DCLK_SEL_DCLK0

#define TCON0_IO_CTRL0_DCLK_SEL_DCLK0 (0UL << 28)

◆ TCON0_IO_CTRL0_DCLK_SEL_DCLK1

#define TCON0_IO_CTRL0_DCLK_SEL_DCLK1 (1UL << 28)

◆ TCON0_IO_CTRL0_DCLK_SEL_DCLK2

#define TCON0_IO_CTRL0_DCLK_SEL_DCLK2 (2UL << 28)

◆ TCON0_IO_CTRL0_IO3_INV

#define TCON0_IO_CTRL0_IO3_INV (1UL << 27)

◆ TCON0_IO_CTRL0_IO2_INV

#define TCON0_IO_CTRL0_IO2_INV (1UL << 26)

◆ TCON0_IO_CTRL0_IO1_INV

#define TCON0_IO_CTRL0_IO1_INV (1UL << 25)

◆ TCON0_IO_CTRL0_IO0_INV

#define TCON0_IO_CTRL0_IO0_INV (1UL << 24)

◆ TCON0_IO_CTRL1

#define TCON0_IO_CTRL1 0x08c

◆ TCON1_CTRL

#define TCON1_CTRL 0x090

◆ TCON1_CTRL_EN

#define TCON1_CTRL_EN (1UL << 31)

◆ TCON1_BASIC0

#define TCON1_BASIC0 0x094

◆ TCON1_BASIC1

#define TCON1_BASIC1 0x098

◆ TCON1_BASIC2

#define TCON1_BASIC2 0x09c

◆ TCON1_BASIC3

#define TCON1_BASIC3 0x0a0

◆ TCON1_BASIC4

#define TCON1_BASIC4 0x0a4

◆ TCON1_BASIC5

#define TCON1_BASIC5 0x0a8

◆ TCON1_IO_CTRL0

#define TCON1_IO_CTRL0 0x0f0

◆ TCON1_IO_CTRL1

#define TCON1_IO_CTRL1 0x0f4

◆ TCON_DEBUG_INFO

#define TCON_DEBUG_INFO 0x0fc

◆ DEBE_BASE

#define DEBE_BASE ((debe_reg_t *)0x01E60000)

◆ DEBE_MODE_CTRL

#define DEBE_MODE_CTRL 0x800

◆ DEBE_MODE_CTRL_LAYER_EN

#define DEBE_MODE_CTRL_LAYER_EN ( __LAYER )

Value:

((1UL << __LAYER) << 8)

◆ DEBE_MODE_CTRL_CHANNEL_START

#define DEBE_MODE_CTRL_CHANNEL_START (1UL << 1)

◆ DEBE_MODE_CTRL_DEBE_EN

#define DEBE_MODE_CTRL_DEBE_EN (1UL << 0)

◆ DEBE_BACKCOLOR

#define DEBE_BACKCOLOR 0x804

◆ DEBE_DISP_SIZE

#define DEBE_DISP_SIZE 0x808

◆ DEBE_DISP_SIZE_WIDTH

#define DEBE_DISP_SIZE_WIDTH ( __W )

Value:

(((__W) - 1) << 0)

◆ DEBE_DISP_SIZE_HEIGHT

#define DEBE_DISP_SIZE_HEIGHT ( __H )

Value:

(((__H) - 1) << 16)

◆ DEBE_LAY0_SIZE

#define DEBE_LAY0_SIZE 0x810

◆ DEBE_LAY1_SIZE

#define DEBE_LAY1_SIZE 0x814

◆ DEBE_LAY2_SIZE

#define DEBE_LAY2_SIZE 0x818

◆ DEBE_LAY3_SIZE

#define DEBE_LAY3_SIZE 0x81c

◆ DEBE_LAY_SIZE_WIDTH

#define DEBE_LAY_SIZE_WIDTH ( __W )

Value:

(((__W) - 1) << 0)

◆ DEBE_LAY_SIZE_HEIGHT

#define DEBE_LAY_SIZE_HEIGHT ( __H )

Value:

(((__H) - 1) << 16)

◆ DEBE_LAY0_CODNT

#define DEBE_LAY0_CODNT 0x820

◆ DEBE_LAY1_CODNT

#define DEBE_LAY1_CODNT 0x824

◆ DEBE_LAY2_CODNT

#define DEBE_LAY2_CODNT 0x828

◆ DEBE_LAY3_CODNT

#define DEBE_LAY3_CODNT 0x82c

◆ DEBE_LAY_CODNT_X

#define DEBE_LAY_CODNT_X ( __X )

Value:

((__X) << 0)

◆ DEBE_LAY_CODNT_Y

#define DEBE_LAY_CODNT_Y ( __Y )

Value:

((__Y) << 16)

◆ DEBE_LAY0_LINEWIDTH

#define DEBE_LAY0_LINEWIDTH 0x840

◆ DEBE_LAY1_LINEWIDTH

#define DEBE_LAY1_LINEWIDTH 0x844

◆ DEBE_LAY2_LINEWIDTH

#define DEBE_LAY2_LINEWIDTH 0x848

◆ DEBE_LAY3_LINEWIDTH

#define DEBE_LAY3_LINEWIDTH 0x84c

◆ DEBE_LAY_LINEWIDTH_BIT

#define DEBE_LAY_LINEWIDTH_BIT ( __W )

Value:

(__W)

◆ DEBE_LAY_LINEWIDTH_BYTE

#define DEBE_LAY_LINEWIDTH_BYTE ( __W )

Value:

((__W) << 3)

◆ DEBE_LAY_LINEWIDTH_HWORD

#define DEBE_LAY_LINEWIDTH_HWORD ( __W )

Value:

((__W) << 4)

◆ DEBE_LAY_LINEWIDTH_WORD

#define DEBE_LAY_LINEWIDTH_WORD ( __W )

Value:

((__W) << 5)

◆ DEBE_LAY0_FB_ADDR0

#define DEBE_LAY0_FB_ADDR0 0x850

◆ DEBE_LAY1_FB_ADDR0

#define DEBE_LAY1_FB_ADDR0 0x854

◆ DEBE_LAY2_FB_ADDR0

#define DEBE_LAY2_FB_ADDR0 0x858

◆ DEBE_LAY3_FB_ADDR0

#define DEBE_LAY3_FB_ADDR0 0x85c

◆ DEBE_LAY0_FB_ADDR1

#define DEBE_LAY0_FB_ADDR1 0x860

◆ DEBE_LAY1_FB_ADDR1

#define DEBE_LAY1_FB_ADDR1 0x864

◆ DEBE_LAY2_FB_ADDR1

#define DEBE_LAY2_FB_ADDR1 0x868

◆ DEBE_LAY3_FB_ADDR1

#define DEBE_LAY3_FB_ADDR1 0x86c

◆ DEBE_REGBUFF_CTRL

#define DEBE_REGBUFF_CTRL 0x870

◆ DEBE_REGBUFF_CTRL_DIABLE_AUTO_RELOAD

#define DEBE_REGBUFF_CTRL_DIABLE_AUTO_RELOAD (1UL << 1)

◆ DEBE_REGBUFF_CTRL_RELOAD

#define DEBE_REGBUFF_CTRL_RELOAD (1UL << 0)

◆ DEBE_CK_MAX

#define DEBE_CK_MAX 0x880

◆ DEBE_CK_MIN

#define DEBE_CK_MIN 0x884

◆ DEBE_CK_CFG

#define DEBE_CK_CFG 0x888

◆ DEBE_LAY0_ATT_CTRL0

#define DEBE_LAY0_ATT_CTRL0 0x890

◆ DEBE_LAY1_ATT_CTRL0

#define DEBE_LAY1_ATT_CTRL0 0x894

◆ DEBE_LAY2_ATT_CTRL0

#define DEBE_LAY2_ATT_CTRL0 0x898

◆ DEBE_LAY3_ATT_CTRL0

#define DEBE_LAY3_ATT_CTRL0 0x89c

◆ DEBE_LAY0_ATT_CTRL1

#define DEBE_LAY0_ATT_CTRL1 0x8a0

◆ DEBE_LAY1_ATT_CTRL1

#define DEBE_LAY1_ATT_CTRL1 0x8a4

◆ DEBE_LAY2_ATT_CTRL1

#define DEBE_LAY2_ATT_CTRL1 0x8a8

◆ DEBE_LAY3_ATT_CTRL1

#define DEBE_LAY3_ATT_CTRL1 0x8ac

◆ DEBE_HWC_CTRL

#define DEBE_HWC_CTRL 0x8d8

◆ DEBE_HWCFB_CTRL

#define DEBE_HWCFB_CTRL 0x8e0

◆ DEBE_WB_CTRL

#define DEBE_WB_CTRL 0x8f0

◆ DEBE_WB_ADDR

#define DEBE_WB_ADDR 0x8f4

◆ DEBE_WB_LW

#define DEBE_WB_LW 0x8f8

◆ DEBE_IYUV_CH_CTRL

#define DEBE_IYUV_CH_CTRL 0x920

◆ DEBE_CH0_YUV_FB_ADDR

#define DEBE_CH0_YUV_FB_ADDR 0x930

◆ DEBE_CH1_YUV_FB_ADDR

#define DEBE_CH1_YUV_FB_ADDR 0x934

◆ DEBE_CH2_YUV_FB_ADDR

#define DEBE_CH2_YUV_FB_ADDR 0x938

◆ DEBE_CH0_YUV_BLW

#define DEBE_CH0_YUV_BLW 0x940

◆ DEBE_CH1_YUV_BLW

#define DEBE_CH1_YUV_BLW 0x944

◆ DEBE_CH2_YUV_BLW

#define DEBE_CH2_YUV_BLW 0x948

◆ DEBE_COEF00

#define DEBE_COEF00 0x950

◆ DEBE_COEF01

#define DEBE_COEF01 0x954

◆ DEBE_COEF02

#define DEBE_COEF02 0x958

◆ DEBE_COEF03

#define DEBE_COEF03 0x95c

◆ DEBE_COEF10

#define DEBE_COEF10 0x960

◆ DEBE_COEF11

#define DEBE_COEF11 0x964

◆ DEBE_COEF12

#define DEBE_COEF12 0x968

◆ DEBE_COEF13

#define DEBE_COEF13 0x96c

◆ DEBE_COEF20

#define DEBE_COEF20 0x970

◆ DEBE_COEF21

#define DEBE_COEF21 0x974

◆ DEBE_COEF22

#define DEBE_COEF22 0x978

◆ DEBE_COEF23

#define DEBE_COEF23 0x97c

◆ TVE_BASE

#define TVE_BASE ((tve_reg_t *)0x01c0a000)

◆ TVE_ENABLE

#define TVE_ENABLE 0x000

◆ __TVE_ENABLE_DAC_MAP

#define __TVE_ENABLE_DAC_MAP	(		__DAC,
			__OUT )

Value:

((__OUT) << (((__DAC) + 1) << 2))

◆ TVE_ENABLE_DAC_MAP

#define TVE_ENABLE_DAC_MAP	(		__DAC,
			... )

Value:

__TVE_ENABLE_DAC_MAP(_DAC, (0xF, ##__VA_ARGS__))

__TVE_ENABLE_DAC_MAP

#define __TVE_ENABLE_DAC_MAP(__DAC, __OUT)

Definition f1c100s_reg.h:705

◆ TVE_ENABLE_EN

#define TVE_ENABLE_EN (1UL << 0)

◆ TVE_CFG0

#define TVE_CFG0 0x004

◆ TVE_CFG0_YC_EN

#define TVE_CFG0_YC_EN (1UL << 17)

◆ TVE_CFG0_CVBS_EN

#define TVE_CFG0_CVBS_EN (1UL << 16)

◆ TVE_CFG0_TVMODE_SELECT

#define TVE_CFG0_TVMODE_SELECT ( ... )

Value:

((0xF, ##__VA_ARGS__) << 0)

◆ TVE_DAC1

#define TVE_DAC1 0x008

◆ TVE_DAC1_CLOCK_INVERT

#define TVE_DAC1_CLOCK_INVERT (1UL << 24)

◆ TVE_DAC1_DAC_EN

#define TVE_DAC1_DAC_EN ( __DAC )

Value:

(1UL << (__DAC))

◆ TVE_NOTCH

#define TVE_NOTCH 0x00c

◆ TVE_CHROMA_FREQUENCY

#define TVE_CHROMA_FREQUENCY 0x010

◆ TVE_PORCH

#define TVE_PORCH 0x014

◆ TVE_LINE

#define TVE_LINE 0x01c

◆ TVE_LEVEL

#define TVE_LEVEL 0x020

◆ TVE_DAC2

#define TVE_DAC2 0x024

◆ TVE_DETECT_STATUS

#define TVE_DETECT_STATUS 0x038

◆ TVE_CBCR_LEVEL

#define TVE_CBCR_LEVEL 0x10c

◆ TVE_BURST_WIDTH

#define TVE_BURST_WIDTH 0x114

◆ TVE_CBCR_GAIN

#define TVE_CBCR_GAIN 0x118

◆ TVE_SYNC_VBI

#define TVE_SYNC_VBI 0x11c

◆ TVE_ACTIVE_LINE

#define TVE_ACTIVE_LINE 0x124

◆ TVE_CHROMA

#define TVE_CHROMA 0x128

◆ TVE_ENCODER

#define TVE_ENCODER 0x12c

◆ TVE_RESYNC

#define TVE_RESYNC 0x130

◆ TVE_SLAVE

#define TVE_SLAVE 0x134

◆ TIMER_BASE

#define TIMER_BASE ((timer_reg_t *)0x01c20c00)

◆ TMR_IRQ_EN

#define TMR_IRQ_EN 0x000

◆ TMR_IRQ_STA

#define TMR_IRQ_STA 0x004

◆ TMR0_CTRL

#define TMR0_CTRL 0x010

◆ TMR0_INTV_VALUE

#define TMR0_INTV_VALUE 0x014

◆ TMR0_CUR_VALUE

#define TMR0_CUR_VALUE 0x018

◆ TMR1_CTRL

#define TMR1_CTRL 0x020

◆ TMR1_INTV_VALUE

#define TMR1_INTV_VALUE 0x024

◆ TMR1_CUR_VALUE

#define TMR1_CUR_VALUE 0x028

◆ TMR2_CTRL

#define TMR2_CTRL 0x030

◆ TMR2_INTV_VALUE

#define TMR2_INTV_VALUE 0x034

◆ TMR2_CUR_VALUE

#define TMR2_CUR_VALUE 0x038

◆ TMR_CTRL_MODE

#define TMR_CTRL_MODE (1UL << 7)

◆ TMR_CTRL_MODE_CONTINUOUS

#define TMR_CTRL_MODE_CONTINUOUS (0UL << 7)

◆ TMR_CTRL_MODE_SINGLE

#define TMR_CTRL_MODE_SINGLE (1UL << 7)

◆ TMR_CTRL_CLK_SRC

#define TMR_CTRL_CLK_SRC (3UL << 2)

◆ TMR_CTRL_CLK_SRC_LOSC

#define TMR_CTRL_CLK_SRC_LOSC (0UL << 2)

◆ TMR_CTRL_CLK_SRC_OSC24M

#define TMR_CTRL_CLK_SRC_OSC24M (1UL << 2)

◆ TMR_CTRL_RELOAD

#define TMR_CTRL_RELOAD (1UL << 1)

◆ TMR_CTRL_EN

#define TMR_CTRL_EN (1UL << 0)

◆ AVS_CNT_CTL

#define AVS_CNT_CTL 0x080

◆ AVS_CNT0

#define AVS_CNT0 0x084

◆ AVS_CNT1

#define AVS_CNT1 0x088

◆ AVS_CNT_DIV

#define AVS_CNT_DIV 0x08c

◆ WDOG_IRQ_EN

#define WDOG_IRQ_EN 0x0a0

◆ WDOG_IRQ_STA

#define WDOG_IRQ_STA 0x0a4

◆ WDOG_CTRL

#define WDOG_CTRL 0x0b0

◆ WDOG_CFG

#define WDOG_CFG 0x0b4

◆ WDOG_MODE

#define WDOG_MODE 0x0b8

◆ MUSB_BASE

#define MUSB_BASE ((musb_reg_t *)0x01c13000)

◆ MUSB_FAddr

#define MUSB_FAddr 0x0098

◆ MUSB_Power

#define MUSB_Power 0x0040

◆ MUSBD_Power_ISOUpdate

#define MUSBD_Power_ISOUpdate (1UL << 7)

◆ MUSBD_Power_SoftConn

#define MUSBD_Power_SoftConn (1UL << 6)

◆ MUSBD_Power_HSEnab

#define MUSBD_Power_HSEnab (1UL << 5)

◆ MUSB_Power_HSMode

#define MUSB_Power_HSMode (1UL << 4)

◆ MUSB_Power_Reset

#define MUSB_Power_Reset (1UL << 3)

◆ MUSB_Power_Resume

#define MUSB_Power_Resume (1UL << 2)

◆ MUSB_Power_SuspendMode

#define MUSB_Power_SuspendMode (1UL << 1)

◆ MUSB_Power_EnableSuspendM

#define MUSB_Power_EnableSuspendM (1UL << 0)

◆ MUSB_IntrTx

#define MUSB_IntrTx 0x0044

◆ MUSB_IntrRx

#define MUSB_IntrRx 0x0046

◆ MUSB_IntrTxE

#define MUSB_IntrTxE 0x0048

◆ MUSB_IntrRxE

#define MUSB_IntrRxE 0x004a

◆ MUSB_IntrUSB

#define MUSB_IntrUSB 0x004c

◆ MUSBD_IntrUSB_VBusError

#define MUSBD_IntrUSB_VBusError (1UL << 7)

◆ MUSB_IntrUSB_SessReq

#define MUSB_IntrUSB_SessReq (1UL << 6)

◆ MUSB_IntrUSB_Discon

#define MUSB_IntrUSB_Discon (1UL << 5)

◆ MUSBH_IntrUSB_Conn

#define MUSBH_IntrUSB_Conn (1UL << 4)

◆ MUSB_IntrUSB_SOF

#define MUSB_IntrUSB_SOF (1UL << 3)

◆ MUSBD_IntrUSB_Reset

#define MUSBD_IntrUSB_Reset (1UL << 2)

◆ MUSBH_IntrUSB_Babble

#define MUSBH_IntrUSB_Babble (1UL << 2)

◆ MUSB_IntrUSB_Resume

#define MUSB_IntrUSB_Resume (1UL << 1)

◆ MUSBD_IntrUSB_Suspend

#define MUSBD_IntrUSB_Suspend (1UL << 0)

◆ MUSB_IntrUSBE

#define MUSB_IntrUSBE 0x0050

◆ MUSBD_IntrUSBE_VBusError

#define MUSBD_IntrUSBE_VBusError (1UL << 7)

◆ MUSB_IntrUSBE_SessReq

#define MUSB_IntrUSBE_SessReq (1UL << 6)

◆ MUSB_IntrUSBE_Discon

#define MUSB_IntrUSBE_Discon (1UL << 5)

◆ MUSBH_IntrUSBE_Conn

#define MUSBH_IntrUSBE_Conn (1UL << 4)

◆ MUSB_IntrUSBE_SOF

#define MUSB_IntrUSBE_SOF (1UL << 3)

◆ MUSBD_IntrUSBE_Reset

#define MUSBD_IntrUSBE_Reset (1UL << 2)

◆ MUSBH_IntrUSBE_Babble

#define MUSBH_IntrUSBE_Babble (1UL << 2)

◆ MUSB_IntrUSBE_Resume

#define MUSB_IntrUSBE_Resume (1UL << 1)

◆ MUSBD_IntrUSBE_Suspend

#define MUSBD_IntrUSBE_Suspend (1UL << 0)

◆ MUSB_Frame

#define MUSB_Frame 0x0054

◆ MUSB_Index

#define MUSB_Index 0x0042

◆ MUSB_Testmode

#define MUSB_Testmode 0x007c

◆ MUSB_TxMaxP

#define MUSB_TxMaxP 0x0080

◆ MUSB_CSR0

#define MUSB_CSR0 0x0082

◆ MUSBD_CSR0_FlushFIFO

#define MUSBD_CSR0_FlushFIFO (1UL << 8)

◆ MUSBD_CSR0_ServicedSetupEnd

#define MUSBD_CSR0_ServicedSetupEnd (1UL << 7)

◆ MUSBD_CSR0_ServicedRxPktRdy

#define MUSBD_CSR0_ServicedRxPktRdy (1UL << 6)

◆ MUSBD_CSR0_SendStall

#define MUSBD_CSR0_SendStall (1UL << 5)

◆ MUSBD_CSR0_SetupEnd

#define MUSBD_CSR0_SetupEnd (1UL << 4)

◆ MUSBD_CSR0_DataEnd

#define MUSBD_CSR0_DataEnd (1UL << 3)

◆ MUSBD_CSR0_SentStall

#define MUSBD_CSR0_SentStall (1UL << 2)

◆ MUSBD_CSR0_TxPktRdy

#define MUSBD_CSR0_TxPktRdy (1UL << 1)

◆ MUSBD_CSR0_RxPktRdy

#define MUSBD_CSR0_RxPktRdy (1UL << 0)

◆ MUSBH_CSR0_DisPing

#define MUSBH_CSR0_DisPing (1UL << 11)

◆ MUSBH_CSR0_DataToggleWrEnable

#define MUSBH_CSR0_DataToggleWrEnable (1UL << 10)

◆ MUSBH_CSR0_DataToggle

#define MUSBH_CSR0_DataToggle (1UL << 9)

◆ MUSBH_CSR0_FlushFIFO

#define MUSBH_CSR0_FlushFIFO (1UL << 8)

◆ MUSBH_CSR0_NAKTimeout

#define MUSBH_CSR0_NAKTimeout (1UL << 7)

◆ MUSBH_CSR0_StatusPkt

#define MUSBH_CSR0_StatusPkt (1UL << 6)

◆ MUSBH_CSR0_ReqPkt

#define MUSBH_CSR0_ReqPkt (1UL << 5)

◆ MUSBH_CSR0_Error

#define MUSBH_CSR0_Error (1UL << 4)

◆ MUSBH_CSR0_SetupPkt

#define MUSBH_CSR0_SetupPkt (1UL << 3)

◆ MUSBH_CSR0_RxStall

#define MUSBH_CSR0_RxStall (1UL << 2)

◆ MUSBH_CSR0_TxPktRdy

#define MUSBH_CSR0_TxPktRdy (1UL << 1)

◆ MUSBH_CSR0_RxPktRdy

#define MUSBH_CSR0_RxPktRdy (1UL << 0)

◆ MUSB_TxCSR

#define MUSB_TxCSR 0x0082

◆ MUSBD_TxCSRL_IncompTx

#define MUSBD_TxCSRL_IncompTx (1UL << 7)

◆ MUSBD_TxCSRL_ClrDataTog

#define MUSBD_TxCSRL_ClrDataTog (1UL << 6)

◆ MUSBD_TxCSRL_SentStall

#define MUSBD_TxCSRL_SentStall (1UL << 5)

◆ MUSBD_TxCSRL_SendStall

#define MUSBD_TxCSRL_SendStall (1UL << 4)

◆ MUSBD_TxCSRL_FlushFIFO

#define MUSBD_TxCSRL_FlushFIFO (1UL << 3)

◆ MUSBD_TxCSRL_UnderRun

#define MUSBD_TxCSRL_UnderRun (1UL << 2)

◆ MUSBD_TxCSRL_FIFONotEmpty

#define MUSBD_TxCSRL_FIFONotEmpty (1UL << 1)

◆ MUSBD_TxCSRL_TxPktRdy

#define MUSBD_TxCSRL_TxPktRdy (1UL << 0)

◆ MUSBD_TxCSRH_NAKTimeout

#define MUSBD_TxCSRH_NAKTimeout (1UL << 7)

◆ MUSBD_TxCSRH_AutoSet

#define MUSBD_TxCSRH_AutoSet (1UL << 7)

◆ MUSBD_TxCSRH_ISO

#define MUSBD_TxCSRH_ISO (1UL << 6)

◆ MUSBD_TxCSRH_Mode

#define MUSBD_TxCSRH_Mode (1UL << 5)

◆ MUSBD_TxCSRH_Mode_Tx

#define MUSBD_TxCSRH_Mode_Tx (1UL << 5)

◆ MUSBD_TxCSRH_Mode_Rx

#define MUSBD_TxCSRH_Mode_Rx (0UL << 5)

◆ MUSBD_TxCSRH_DMAReqEnab

#define MUSBD_TxCSRH_DMAReqEnab (1UL << 4)

◆ MUSBD_TxCSRH_FrcDataTog

#define MUSBD_TxCSRH_FrcDataTog (1UL << 3)

◆ MUSBD_TxCSRH_DMAReqMode

#define MUSBD_TxCSRH_DMAReqMode (1UL << 2)

◆ MUSBH_TxCSRL_NAKTimeout

#define MUSBH_TxCSRL_NAKTimeout (1UL << 7)

◆ MUSBH_TxCSRL_IncomTx

#define MUSBH_TxCSRL_IncomTx (1UL << 7)

◆ MUSBH_TxCSRL_ClrDataTog

#define MUSBH_TxCSRL_ClrDataTog (1UL << 6)

◆ MUSBH_TxCSRL_RxStall

#define MUSBH_TxCSRL_RxStall (1UL << 5)

◆ MUSBH_TxCSRL_SetupPkt

#define MUSBH_TxCSRL_SetupPkt (1UL << 4)

◆ MUSBH_TxCSRL_FlushFIFO

#define MUSBH_TxCSRL_FlushFIFO (1UL << 3)

◆ MUSBH_TxCSRL_Error

#define MUSBH_TxCSRL_Error (1UL << 2)

◆ MUSBH_TxCSRL_FIFONotEmpty

#define MUSBH_TxCSRL_FIFONotEmpty (1UL << 1)

◆ MUSBH_TxCSRL_TxPktRdy

#define MUSBH_TxCSRL_TxPktRdy (1UL << 0)

◆ MUSBH_TxCSRH_AutoSet

#define MUSBH_TxCSRH_AutoSet (1UL << 7)

◆ MUSBH_TxCSRH_Mode

#define MUSBH_TxCSRH_Mode (1UL << 6)

◆ MUSBH_TxCSRH_Mode_Tx

#define MUSBH_TxCSRH_Mode_Tx (1UL << 5)

◆ MUSBH_TxCSRH_Mode_Rx

#define MUSBH_TxCSRH_Mode_Rx (0UL << 5)

◆ MUSBH_TxCSRH_DMAReqEnab

#define MUSBH_TxCSRH_DMAReqEnab (1UL << 4)

◆ MUSBH_TxCSRH_FrcDataTog

#define MUSBH_TxCSRH_FrcDataTog (1UL << 3)

◆ MUSBH_TxCSRH_DMAReqMode

#define MUSBH_TxCSRH_DMAReqMode (1UL << 2)

◆ MUSBH_TxCSRH_DataToggleWrEnable

#define MUSBH_TxCSRH_DataToggleWrEnable (1UL << 1)

◆ MUSBH_TxCSRH_DataToggle

#define MUSBH_TxCSRH_DataToggle (1UL << 0)

◆ MUSB_RxMaxP

#define MUSB_RxMaxP 0x0084

◆ MUSB_RxCSR

#define MUSB_RxCSR 0x0086

◆ MUSBD_RxCSRL_ClrDataTog

#define MUSBD_RxCSRL_ClrDataTog (1UL << 7)

◆ MUSBD_RxCSRL_SentStall

#define MUSBD_RxCSRL_SentStall (1UL << 6)

◆ MUSBD_RxCSRL_SendStall

#define MUSBD_RxCSRL_SendStall (1UL << 5)

◆ MUSBD_RxCSRL_FlushFIFO

#define MUSBD_RxCSRL_FlushFIFO (1UL << 4)

◆ MUSBD_RxCSRL_DataError

#define MUSBD_RxCSRL_DataError (1UL << 3)

◆ MUSBD_RxCSRL_OverRun

#define MUSBD_RxCSRL_OverRun (1UL << 2)

◆ MUSBD_RxCSRL_FIFOFull

#define MUSBD_RxCSRL_FIFOFull (1UL << 1)

◆ MUSBD_RxCSRL_RxPktRdy

#define MUSBD_RxCSRL_RxPktRdy (1UL << 0)

◆ MUSBD_RxCSRH_AutoClear

#define MUSBD_RxCSRH_AutoClear (1UL << 7)

◆ MUSBD_RxCSRH_ISO

#define MUSBD_RxCSRH_ISO (1UL << 6)

◆ MUSBD_RxCSRH_DMAReqEnab

#define MUSBD_RxCSRH_DMAReqEnab (1UL << 5)

◆ MUSBD_RxCSRH_DisNyet

#define MUSBD_RxCSRH_DisNyet (1UL << 4)

◆ MUSBD_RxCSRH_PIDError

#define MUSBD_RxCSRH_PIDError (1UL << 4)

◆ MUSBD_RxCSRH_DMAReqMode

#define MUSBD_RxCSRH_DMAReqMode (1UL << 3)

◆ MUSBD_RxCSRH_IncompRx

#define MUSBD_RxCSRH_IncompRx (1UL << 0)

◆ MUSBH_RxCSRL_ClrDataTog

#define MUSBH_RxCSRL_ClrDataTog (1UL << 7)

◆ MUSBH_RxCSRL_RxStall

#define MUSBH_RxCSRL_RxStall (1UL << 6)

◆ MUSBH_RxCSRL_ReqPkt

#define MUSBH_RxCSRL_ReqPkt (1UL << 5)

◆ MUSBH_RxCSRL_FlushFIFO

#define MUSBH_RxCSRL_FlushFIFO (1UL << 4)

◆ MUSBH_RxCSRL_DataError

#define MUSBH_RxCSRL_DataError (1UL << 3)

◆ MUSBH_RxCSRL_NAKTimeout

#define MUSBH_RxCSRL_NAKTimeout (1UL << 3)

◆ MUSBH_RxCSRL_Error

#define MUSBH_RxCSRL_Error (1UL << 2)

◆ MUSBH_RxCSRL_FIFOFull

#define MUSBH_RxCSRL_FIFOFull (1UL << 1)

◆ MUSBH_RxCSRL_RxPktRdy

#define MUSBH_RxCSRL_RxPktRdy (1UL << 0)

◆ MUSBH_RxCSRH_AutoClear

#define MUSBH_RxCSRH_AutoClear (1UL << 7)

◆ MUSBH_RxCSRH_AutoReq

#define MUSBH_RxCSRH_AutoReq (1UL << 6)

◆ MUSBH_RxCSRH_DMAReqEnab

#define MUSBH_RxCSRH_DMAReqEnab (1UL << 5)

◆ MUSBH_RxCSRH_PIDError

#define MUSBH_RxCSRH_PIDError (1UL << 4)

◆ MUSBH_RxCSRH_DMAReqMode

#define MUSBH_RxCSRH_DMAReqMode (1UL << 3)

◆ MUSBH_RxCSRH_DataToggleWrEnable

#define MUSBH_RxCSRH_DataToggleWrEnable (1UL << 2)

◆ MUSBH_RxCSRH_DataToggle

#define MUSBH_RxCSRH_DataToggle (1UL << 1)

◆ MUSBH_RxCSRH_IncompRx

#define MUSBH_RxCSRH_IncompRx (1UL << 0)

◆ MUSB_Count0

#define MUSB_Count0 0x0088

◆ MUSB_RxCount

#define MUSB_RxCount 0x0088

◆ MUSB_Type0

#define MUSB_Type0 0x008c

◆ MUSB_TxType

#define MUSB_TxType 0x008c

◆ MUSB_NAKLimit0

#define MUSB_NAKLimit0 0x008d

◆ MUSB_TxInterval

#define MUSB_TxInterval 0x008d

◆ MUSB_RxType

#define MUSB_RxType 0x008e

◆ MUSB_RxInterval

#define MUSB_RxInterval 0x008f

◆ MUSB_ConfigData

#define MUSB_ConfigData 0x001f

◆ MUSB_FIFO0

#define MUSB_FIFO0 0x0000

◆ MUSB_FIFO1

#define MUSB_FIFO1 0x0004

◆ MUSB_FIFO2

#define MUSB_FIFO2 0x0008

◆ MUSB_FIFO3

#define MUSB_FIFO3 0x000c

◆ MUSB_FIFO4

#define MUSB_FIFO4 0x0010

◆ MUSB_FIFO5

#define MUSB_FIFO5 0x0014

◆ MUSB_DevCtl

#define MUSB_DevCtl 0x0041

◆ MUSB_DevCtl_FSDev

#define MUSB_DevCtl_FSDev (1UL << 6)

◆ MUSB_DevCtl_LSDev

#define MUSB_DevCtl_LSDev (1UL << 5)

◆ MUSB_DevCtl_HostMode

#define MUSB_DevCtl_HostMode (1UL << 2)

◆ MUSB_DevCtl_Session

#define MUSB_DevCtl_Session (1UL << 0)

◆ MUSB_MISC

#define MUSB_MISC

◆ MUSB_TxFIFOsz

#define MUSB_TxFIFOsz 0x0090

◆ MUSB_RxFIFOsz

#define MUSB_RxFIFOsz 0x0094

◆ MUSB_TxFIFOadd

#define MUSB_TxFIFOadd 0x0092

◆ MUSB_RxFIFOadd

#define MUSB_RxFIFOadd 0x0096

◆ MUSB_TxFuncAddr

#define MUSB_TxFuncAddr 0x0098

◆ MUSB_TxHubAddr

#define MUSB_TxHubAddr 0x009a

◆ MUSB_TxHubPort

#define MUSB_TxHubPort 0x009b

◆ MUSB_RxFuncAddr

#define MUSB_RxFuncAddr 0x009c

◆ MUSB_RxHubAddr

#define MUSB_RxHubAddr 0x009e

◆ MUSB_RxHubPort

#define MUSB_RxHubPort 0x009f

◆ MUSB_Vendor0

#define MUSB_Vendor0 0x0043

◆ MUSB_Vendor1

#define MUSB_Vendor1 0x007d

◆ MUSB_Vendor2

#define MUSB_Vendor2 0x007e

◆ MUSB_HWVers

#define MUSB_HWVers

◆ MUSB_EPInfo

#define MUSB_EPInfo 0x0078

◆ MUSB_RAMInfo

#define MUSB_RAMInfo 0x0079

◆ MUSB_LinkInfo

#define MUSB_LinkInfo 0x007a

◆ MUSB_VPLen

#define MUSB_VPLen 0x007b

◆ MUSB_HS_EOF1

#define MUSB_HS_EOF1 0x007c

◆ MUSB_FS_EOF1

#define MUSB_FS_EOF1 0x007d

◆ MUSB_LS_EOF1

#define MUSB_LS_EOF1 0x007e

◆ MUSB_SOFT_RST

#define MUSB_SOFT_RST

◆ MUSB_ISCR

#define MUSB_ISCR 0x0400

◆ MUSB_ISCR_VBUS_VALID_FROM_DATA

#define MUSB_ISCR_VBUS_VALID_FROM_DATA (1UL << 30)

◆ MUSB_ISCR_VBUS_VALID_FROM_VBUS

#define MUSB_ISCR_VBUS_VALID_FROM_VBUS (1UL << 29)

◆ MUSB_ISCR_EXT_ID_STATUS

#define MUSB_ISCR_EXT_ID_STATUS (1UL << 28)

◆ MUSB_ISCR_EXT_DM_STATUS

#define MUSB_ISCR_EXT_DM_STATUS (1UL << 27)

◆ MUSB_ISCR_EXT_DP_STATUS

#define MUSB_ISCR_EXT_DP_STATUS (1UL << 26)

◆ MUSB_ISCR_MERGED_VBUS_STATUS

#define MUSB_ISCR_MERGED_VBUS_STATUS (1UL << 25)

◆ MUSB_ISCR_MERGED_ID_STATUS

#define MUSB_ISCR_MERGED_ID_STATUS (1UL << 24)

◆ MUSB_ISCR_ID_PULLUP_EN

#define MUSB_ISCR_ID_PULLUP_EN (1UL << 17)

◆ MUSB_ISCR_DPDM_PULLUP_EN

#define MUSB_ISCR_DPDM_PULLUP_EN (1UL << 16)

◆ MUSB_ISCR_FORCE_ID

#define MUSB_ISCR_FORCE_ID (3UL << 14)

◆ MUSB_ISCR_FORCE_ID_DEVICE

#define MUSB_ISCR_FORCE_ID_DEVICE (3UL << 14)

◆ MUSB_ISCR_FORCE_ID_HOST

#define MUSB_ISCR_FORCE_ID_HOST (2UL << 14)

◆ MUSB_ISCR_FORCE_VBUS_VALID

#define MUSB_ISCR_FORCE_VBUS_VALID (3UL << 12)

◆ MUSB_ISCR_FORCE_VBUS_VALID_HIGH

#define MUSB_ISCR_FORCE_VBUS_VALID_HIGH (3UL << 12)

◆ MUSB_ISCR_FORCE_VBUS_VALID_LOW

#define MUSB_ISCR_FORCE_VBUS_VALID_LOW (2UL << 12)

◆ MUSB_ISCR_VBUS_VALID_SRC

#define MUSB_ISCR_VBUS_VALID_SRC (1UL << 10)

◆ MUSB_ISCR_HOSC_EN

#define MUSB_ISCR_HOSC_EN (1UL << 7)

◆ MUSB_ISCR_VBUS_CHANGE_DETECT

#define MUSB_ISCR_VBUS_CHANGE_DETECT (1UL << 6)

◆ MUSB_ISCR_ID_CHANGE_DETECT

#define MUSB_ISCR_ID_CHANGE_DETECT (1UL << 5)

◆ MUSB_ISCR_DPDM_CHANGE_DETECT

#define MUSB_ISCR_DPDM_CHANGE_DETECT (1UL << 4)

◆ MUSB_ISCR_IRQ_ENABLE

#define MUSB_ISCR_IRQ_ENABLE (1UL << 3)

◆ MUSB_ISCR_VBUS_CHANGE_DETECT_EN

#define MUSB_ISCR_VBUS_CHANGE_DETECT_EN (1UL << 2)

◆ MUSB_ISCR_ID_CHANGE_DETECT_EN

#define MUSB_ISCR_ID_CHANGE_DETECT_EN (1UL << 1)

◆ MUSB_ISCR_DPDM_CHANGE_DETECT_EN

#define MUSB_ISCR_DPDM_CHANGE_DETECT_EN (1UL << 0)

◆ TP_BASE

#define TP_BASE ((tp_reg_t *)0x01c24800)

◆ TP_CTRL0

#define TP_CTRL0 0x00

◆ ADC_FIRST_DLY

#define ADC_FIRST_DLY ( __DLY )

Value:

((__DLY) << 24) /* 8 bits */

◆ ADC_FIRST_DLY_MODE

#define ADC_FIRST_DLY_MODE ( __DLY_MODE )

Value:

((__DLY_MODE) << 23)

◆ ADC_CLK_SEL

#define ADC_CLK_SEL ( __CLK_SEL )

Value:

((__CLK_SEL) << 22)

◆ ADC_CLK_DIV

#define ADC_CLK_DIV ( __CLK_DIV )

Value:

((__CLK_DIV) << 20) /* 3 bits */

◆ FS_DIV

#define FS_DIV ( x )

Value:

((x) << 16) /* 4 bits */

◆ T_ACQ

#define T_ACQ ( x )

Value:

((x) << 0) /* 16 bits */

◆ TP_CTRL1

#define TP_CTRL1 0x04

◆ STYLUS_UP_DEBOUN

#define STYLUS_UP_DEBOUN ( x )

Value:

((x) << 12) /* 8 bits */

◆ STYLUS_UP_DEBOUN_EN

#define STYLUS_UP_DEBOUN_EN ( x )

Value:

((x) << 9)

◆ TOUCH_PAN_CALI_EN

#define TOUCH_PAN_CALI_EN ( x )

Value:

((x) << 6)

◆ TP_DUAL_EN

#define TP_DUAL_EN ( x )

Value:

((x) << 5)

◆ TP_MODE_EN

#define TP_MODE_EN ( x )

Value:

((x) << 4)

◆ TP_ADC_SELECT

#define TP_ADC_SELECT ( x )

Value:

((x) << 3)

◆ ADC_CHAN_SELECT

#define ADC_CHAN_SELECT ( x )

Value:

((x) << 0) /* 3 bits */

◆ TP_CTRL2

#define TP_CTRL2 0x08

◆ TP_SENSITIVE_ADJUST

#define TP_SENSITIVE_ADJUST ( x )

Value:

((x) << 28) /* 4 bits */

◆ TP_MODE_SELECT

#define TP_MODE_SELECT ( x )

Value:

((x) << 26) /* 2 bits */

◆ PRE_MEA_EN

#define PRE_MEA_EN ( x )

Value:

((x) << 24)

◆ PRE_MEA_THRE_CNT

#define PRE_MEA_THRE_CNT ( x )

Value:

((x) << 0) /* 24 bits */

◆ TP_CTRL3

#define TP_CTRL3 0x0c

◆ FILTER_EN

#define FILTER_EN ( x )

Value:

((x) << 2)

◆ FILTER_TYPE

#define FILTER_TYPE ( x )

Value:

((x) << 0) /* 2 bits */

◆ TP_INT_FIFOC

#define TP_INT_FIFOC 0x10

◆ TEMP_IRQ_EN

#define TEMP_IRQ_EN ( x )

Value:

((x) << 18)

◆ OVERRUN_IRQ_EN

#define OVERRUN_IRQ_EN ( x )

Value:

((x) << 17)

◆ DATA_IRQ_EN

#define DATA_IRQ_EN ( x )

Value:

((x) << 16)

◆ TP_DATA_XY_CHANGE

#define TP_DATA_XY_CHANGE ( x )

Value:

((x) << 13)

◆ FIFO_TRIG

#define FIFO_TRIG ( x )

Value:

((x) << 8) /* 5 bits */

◆ DATA_DRQ_EN

#define DATA_DRQ_EN ( x )

Value:

((x) << 7)

◆ FIFO_FLUSH

#define FIFO_FLUSH ( x )

Value:

((x) << 4)

◆ TP_UP_IRQ_EN

#define TP_UP_IRQ_EN ( x )

Value:

((x) << 1)

◆ TP_DOWN_IRQ_EN

#define TP_DOWN_IRQ_EN ( x )

Value:

((x) << 0)

◆ TP_INT_FIFOS

#define TP_INT_FIFOS 0x14

◆ TEMP_DATA_PENDING

#define TEMP_DATA_PENDING (1 << 18)

◆ FIFO_OVERRUN_PENDING

#define FIFO_OVERRUN_PENDING (1 << 17)

◆ FIFO_DATA_PENDING

#define FIFO_DATA_PENDING (1 << 16)

◆ TP_IDLE_FLG

#define TP_IDLE_FLG (1 << 2)

◆ TP_UP_PENDING

#define TP_UP_PENDING (1 << 1)

◆ TP_DOWN_PENDING

#define TP_DOWN_PENDING (1 << 0)

◆ TP_TPR

#define TP_TPR 0x18

◆ TEMP_ENABLE

#define TEMP_ENABLE ( x )

Value:

((x) << 16)

◆ TEMP_PERIOD

#define TEMP_PERIOD ( x )

Value:

((x) << 0) /* t = x * 256 * 16 / clkin */

◆ TP_CDAT

#define TP_CDAT 0x1c

◆ TP_TEMP_DATA

#define TP_TEMP_DATA 0x20

◆ TP_DATA

#define TP_DATA 0x24

◆ read_reg8

#define read_reg8	(		__base,
			__reg )

Value:

(*(volatile uint8_t *)((uint32_t)(__base) + (__reg)))

uint32_t

unsigned uint32_t

Definition stdint.h:9

uint8_t

unsigned char uint8_t

Definition stdint.h:5

◆ read_reg16

#define read_reg16	(		__base,
			__reg )

Value:

(*(volatile uint16_t *)((uint32_t)(__base) + (__reg)))

uint16_t

unsigned short uint16_t

Definition stdint.h:7

◆ read_reg32

#define read_reg32	(		__base,
			__reg )

Value:

(*(volatile uint32_t *)((uint32_t)(__base) + (__reg)))

◆ write_reg8

#define write_reg8	(	__base,
		__reg,
		__value )

Value:

(*(volatile uint8_t *)((uint32_t)(__base) + (__reg)) = (uint8_t)(__value))

◆ write_reg16

#define write_reg16	(	__base,
		__reg,
		__value )

Value:

(*(volatile uint16_t *)((uint32_t)(__base) + (__reg)) = (uint16_t)(__value))

◆ write_reg32

#define write_reg32	(	__base,
		__reg,
		__value )

Value:

(*(volatile uint32_t *)((uint32_t)(__base) + (__reg)) = (uint32_t)(__value))

◆ __REG_TYPE__

#define __REG_TYPE__

◆ __REG_CONNECT

#define __REG_CONNECT	(		__A,
			__B )

Value:

__A##__B

◆ __REG_RSVD_NAME

#define __REG_RSVD_NAME ( __NAME )

Value:

__REG_CONNECT(__unused_, __NAME)

__REG_CONNECT

#define __REG_CONNECT(__A, __B)

Definition f1c100s_reg.h:1041

◆ ____REG_RSVD

#define ____REG_RSVD	(		__NAME,
			__BIT )

Value:

reg##__BIT##_t __NAME : __BIT;

reg

class vsf_$ * reg

◆ ____REG_RSVD_N

#define ____REG_RSVD_N	(	__NAME,
		__BIT,
		__N )

Value:

reg##__BIT##_t __NAME[__N];

◆ __REG_RSVD

#define __REG_RSVD ( __BIT )

Value:

____REG_RSVD(REG_RSVD_NAME, __BIT)

____REG_RSVD

#define ____REG_RSVD(__NAME, __BIT)

Definition f1c100s_reg.h:1044

REG_RSVD_NAME

#define REG_RSVD_NAME

Definition f1c100s_reg.h:1051

◆ __REG_RSVD_N

#define __REG_RSVD_N	(		__BIT,
			__N )

Value:

____REG_RSVD_N(REG_RSVD_NAME, __BIT, (__N))

____REG_RSVD_N

#define ____REG_RSVD_N(__NAME, __BIT, __N)

Definition f1c100s_reg.h:1046

◆ REG_RSVD_NAME

#define REG_RSVD_NAME __REG_RSVD_NAME(__LINE__)

◆ REG_RSVD

#define REG_RSVD ( __BIT )

Value:

__REG_RSVD(__BIT)

__REG_RSVD

#define __REG_RSVD(__BIT)

Definition f1c100s_reg.h:1048

◆ REG_RSVD_N

#define REG_RSVD_N	(		__BIT,
			__N )

Value:

__REG_RSVD_N(__BIT, (__N))

__REG_RSVD_N

#define __REG_RSVD_N(__BIT, __N)

Definition f1c100s_reg.h:1049

◆ REG_RSVD_U8

#define REG_RSVD_U8 REG_RSVD(8)

◆ REG_RSVD_U16

#define REG_RSVD_U16 REG_RSVD(16)

◆ REG_RSVD_U32

#define REG_RSVD_U32 REG_RSVD(32)

◆ REG_RSVD_U8N

#define REG_RSVD_U8N ( __N )

Value:

REG_RSVD_N(8, (__N))

REG_RSVD_N

#define REG_RSVD_N(__BIT, __N)

Definition f1c100s_reg.h:1053

◆ REG_RSVD_U16N

#define REG_RSVD_U16N ( __N )

Value:

REG_RSVD_N(16, (__N))

◆ REG_RSVD_U32N

#define REG_RSVD_U32N ( __N )

Value:

REG_RSVD_N(32, (__N))

◆ REG8_RSVD_N

#define REG8_RSVD_N ( __N )

Value:

REG_RSVD_U8N(__N)

REG_RSVD_U8N

#define REG_RSVD_U8N(__N)

Definition f1c100s_reg.h:1059

◆ REG8_RSVD_B

#define REG8_RSVD_B ( __BYTE_CNT )

Value:

REG8_RSVD_N(__BYTE_CNT)

REG8_RSVD_N

#define REG8_RSVD_N(__N)

Definition f1c100s_reg.h:1063

◆ REG8_RSVD_8B

#define REG8_RSVD_8B REG8_RSVD_B(8)

◆ REG8_RSVD_16B

#define REG8_RSVD_16B REG8_RSVD_B(16)

◆ REG8_RSVD_32B

#define REG8_RSVD_32B REG8_RSVD_B(32)

◆ REG8_RSVD_64B

#define REG8_RSVD_64B REG8_RSVD_B(64)

◆ REG8_RSVD_128B

#define REG8_RSVD_128B REG8_RSVD_B(128)

◆ REG8_RSVD_256B

#define REG8_RSVD_256B REG8_RSVD_B(256)

◆ REG8_RSVD_512B

#define REG8_RSVD_512B REG8_RSVD_B(512)

◆ REG8_RSVD_1K

#define REG8_RSVD_1K REG8_RSVD_B(1024)

◆ REG8_RSVD_2K

#define REG8_RSVD_2K REG8_RSVD_B(2048)

◆ REG8_RSVD_4K

#define REG8_RSVD_4K REG8_RSVD_B(4096)

◆ REG8_RSVD_8K

#define REG8_RSVD_8K REG8_RSVD_B(8192)

◆ REG8_RSVD_16K

#define REG8_RSVD_16K REG8_RSVD_B(16 * 1024)

◆ REG8_RSVD_32K

#define REG8_RSVD_32K REG8_RSVD_B(32 * 1024)

◆ REG8_RSVD_64K

#define REG8_RSVD_64K REG8_RSVD_B(64 * 1024)

◆ REG8_RSVD_128K

#define REG8_RSVD_128K REG8_RSVD_B(128 * 1024)

◆ REG8_RSVD_256K

#define REG8_RSVD_256K REG8_RSVD_B(256 * 1024)

◆ REG8_RSVD_512K

#define REG8_RSVD_512K REG8_RSVD_B(512 * 1024)

◆ REG8_RSVD_1M

#define REG8_RSVD_1M REG8_RSVD_B(1024 * 1024)

◆ REG16_RSVD_N

#define REG16_RSVD_N ( __N )

Value:

REG_RSVD_U16N(__N)

REG_RSVD_U16N

#define REG_RSVD_U16N(__N)

Definition f1c100s_reg.h:1060

◆ REG16_RSVD_B

#define REG16_RSVD_B ( __BYTE_CNT )

Value:

REG16_RSVD_N(__BYTE_CNT >> 1)

REG16_RSVD_N

#define REG16_RSVD_N(__N)

Definition f1c100s_reg.h:1084

◆ REG16_RSVD_8B

#define REG16_RSVD_8B REG16_RSVD_B(8)

◆ REG16_RSVD_16B

#define REG16_RSVD_16B REG16_RSVD_B(16)

◆ REG16_RSVD_32B

#define REG16_RSVD_32B REG16_RSVD_B(32)

◆ REG16_RSVD_64B

#define REG16_RSVD_64B REG16_RSVD_B(64)

◆ REG16_RSVD_128B

#define REG16_RSVD_128B REG16_RSVD_B(128)

◆ REG16_RSVD_256B

#define REG16_RSVD_256B REG16_RSVD_B(256)

◆ REG16_RSVD_512B

#define REG16_RSVD_512B REG16_RSVD_B(512)

◆ REG16_RSVD_1K

#define REG16_RSVD_1K REG16_RSVD_B(1024)

◆ REG16_RSVD_2K

#define REG16_RSVD_2K REG16_RSVD_B(2048)

◆ REG16_RSVD_4K

#define REG16_RSVD_4K REG16_RSVD_B(4096)

◆ REG16_RSVD_8K

#define REG16_RSVD_8K REG16_RSVD_B(8192)

◆ REG16_RSVD_16K

#define REG16_RSVD_16K REG16_RSVD_B(16 * 1024)

◆ REG16_RSVD_32K

#define REG16_RSVD_32K REG16_RSVD_B(32 * 1024)

◆ REG16_RSVD_64K

#define REG16_RSVD_64K REG16_RSVD_B(64 * 1024)

◆ REG16_RSVD_128K

#define REG16_RSVD_128K REG16_RSVD_B(128 * 1024)

◆ REG16_RSVD_256K

#define REG16_RSVD_256K REG16_RSVD_B(256 * 1024)

◆ REG16_RSVD_512K

#define REG16_RSVD_512K REG16_RSVD_B(512 * 1024)

◆ REG16_RSVD_1M

#define REG16_RSVD_1M REG16_RSVD_B(1024 * 1024)

◆ REG32_RSVD_N

#define REG32_RSVD_N ( __N )

Value:

REG_RSVD_U32N(__N)

REG_RSVD_U32N

#define REG_RSVD_U32N(__N)

Definition f1c100s_reg.h:1061

◆ REG32_RSVD_B

#define REG32_RSVD_B ( __BYTE_CNT )

Value:

REG_RSVD_U32N(__BYTE_CNT >> 2)

◆ REG32_RSVD_8B

#define REG32_RSVD_8B REG32_RSVD_B(8)

◆ REG32_RSVD_16B

#define REG32_RSVD_16B REG32_RSVD_B(16)

◆ REG32_RSVD_32B

#define REG32_RSVD_32B REG32_RSVD_B(32)

◆ REG32_RSVD_64B

#define REG32_RSVD_64B REG32_RSVD_B(64)

◆ REG32_RSVD_128B

#define REG32_RSVD_128B REG32_RSVD_B(128)

◆ REG32_RSVD_256B

#define REG32_RSVD_256B REG32_RSVD_B(256)

◆ REG32_RSVD_512B

#define REG32_RSVD_512B REG32_RSVD_B(512)

◆ REG32_RSVD_1K

#define REG32_RSVD_1K REG32_RSVD_B(1024)

◆ REG32_RSVD_2K

#define REG32_RSVD_2K REG32_RSVD_B(2048)

◆ REG32_RSVD_4K

#define REG32_RSVD_4K REG32_RSVD_B(4096)

◆ REG32_RSVD_8K

#define REG32_RSVD_8K REG32_RSVD_B(8192)

◆ REG32_RSVD_16K

#define REG32_RSVD_16K REG32_RSVD_B(16 * 1024)

◆ REG32_RSVD_32K

#define REG32_RSVD_32K REG32_RSVD_B(32 * 1024)

◆ REG32_RSVD_64K

#define REG32_RSVD_64K REG32_RSVD_B(64 * 1024)

◆ REG32_RSVD_128K

#define REG32_RSVD_128K REG32_RSVD_B(128 * 1024)

◆ REG32_RSVD_256K

#define REG32_RSVD_256K REG32_RSVD_B(256 * 1024)

◆ REG32_RSVD_512K

#define REG32_RSVD_512K REG32_RSVD_B(512 * 1024)

◆ REG32_RSVD_1M

#define REG32_RSVD_1M REG32_RSVD_B(1024 * 1024)

Typedef Documentation

◆ IRQn_Type

typedef enum IRQn IRQn_Type

◆ syscon_reg_t

typedef struct syscon_reg_t syscon_reg_t

◆ ccu_reg_t

typedef struct ccu_reg_t ccu_reg_t

◆ dram_reg_t

typedef struct dram_reg_t dram_reg_t

◆ pio_port_t

typedef struct pio_port_t pio_port_t

◆ pio_port_int_t

typedef struct pio_port_int_t pio_port_int_t

◆ pio_reg_t

typedef struct pio_reg_t pio_reg_t

◆ uart_reg_t

typedef struct uart_reg_t uart_reg_t

◆ spi_reg_t

typedef struct spi_reg_t spi_reg_t

◆ tcon_reg_t

typedef struct tcon_reg_t tcon_reg_t

◆ debe_reg_t

typedef struct debe_reg_t debe_reg_t

◆ tve_reg_t

typedef struct tve_reg_t tve_reg_t

◆ timer_reg_t

typedef struct timer_reg_t timer_reg_t

◆ musb_reg_t

typedef struct musb_reg_t musb_reg_t

◆ tp_reg_t

typedef struct tp_reg_t tp_reg_t

Enumeration Type Documentation

◆ IRQn

enum IRQn

Enumerator
UART0_IRQn
UART1_IRQn
UART2_IRQn
OWA_IRQn
CIR_IRQn
TWI0_IRQn
TWI1_IRQn	IRQ8
TWI2_IRQn
SPI0_IRQn
SPI1_IRQn	IRQ12
Timer0_IRQn
Timer1_IRQn
Timer2_IRQn
WatchDog_IRQn	IRQ16
RSB_IRQn
DMA_IRQn
TouchPanel_IRQn	IRQ20
AudioCodec_IRQn
KEYADC_IRQn
SDC0_IRQn
SDC1_IRQn	IRQ24
USBOTG_IRQn
TVD_IRQn
TVE_IRQn	IRQ28
TCON_IRQn
DEFE_IRQn
DEBE_IRQn
CSI_IRQn	IRQ32
DEInterlacer_IRQn
VE_IRQn
DAUDIO_IRQn
PIOD_IRQn
PIOE_IRQn
PIOF_IRQn	IRQ40
SWI0_IRQn	IRQ60
SWI1_IRQn
SWI2_IRQn
SWI3_IRQn

Data Structures

Macros

Typedefs

Enumerations

Macro Definition Documentation

◆ SYSCON_BASE

◆ SYSCON_USB_CTRL

◆ USB_FIFO_MODE

◆ USB_FIFO_MODE_8KB

◆ CCU_BASE

◆ CCU_PLL_CPU_CTRL

◆ PLL_CPU_CTRL_PLL_ENABLE

◆ PLL_CPU_CTRL_LOCK

◆ __PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P

◆ __PLL_CPU_CTRL_PLL_FACTOR_N

◆ __PLL_CPU_CTRL_PLL_FACTOR_K

◆ __PLL_CPU_CTRL_PLL_FACTOR_M

◆ PLL_CPU_CTRL_PLL_OUT_EVT_DIV_P

◆ PLL_CPU_CTRL_PLL_FACTOR_N

◆ PLL_CPU_CTRL_PLL_FACTOR_K

◆ PLL_CPU_CTRL_PLL_FACTOR_M

◆ CCU_PLL_AUDIO_CTRL

◆ PLL_AUDIO_CTRL_PLL_ENABLE

◆ PLL_AUDIO_CTRL_LOCK

◆ PLL_AUDIO_CTRL_PLL_SDM_EN

◆ __PLL_AUDIO_CTRL_PLL_FACTOR_N

◆ __PLL_AUDIO_CTRL_PLL_PREDIV_M

◆ PLL_AUDIO_CTRL_PLL_FACTOR_N

◆ PLL_AUDIO_CTRL_PLL_PREDIV_M

◆ CCU_PLL_VIDEO_CTRL

◆ PLL_VIDEO_CTRL_PLL_ENABLE

◆ PLL_VIDEO_CTRL_PLL_MODE

◆ PLL_VIDEO_CTRL_PLL_MODE_AUTO

◆ PLL_VIDEO_CTRL_PLL_MODE_MANUAL

◆ PLL_VIDEO_CTRL_LOCK

◆ PLL_VIDEO_CTRL_FRAC_CLK_OUT

◆ PLL_VIDEO_CTRL_PLL_MODE_SEL

◆ PLL_VIDEO_CTRL_PLL_MODE_INTEGER

◆ PLL_VIDEO_CTRL_PLL_MODE_FRACTIONAL

◆ PLL_VIDEO_CTRL_PLL_SDM_EN

◆ __PLL_VIDEO_CTRL_PLL_FACTOR_N

◆ __PLL_VIDEO_CTRL_PLL_PREDIV_M

◆ PLL_VIDEO_CTRL_PLL_FACTOR_N

◆ PLL_VIDEO_CTRL_PLL_PREDIV_M

◆ CCU_PLL_VE_CTRL

◆ PLL_VE_CTRL_PLL_ENABLE

◆ PLL_VE_CTRL_LOCK

◆ PLL_VE_CTRL_FRAC_CLK_OUT

◆ PLL_VE_CTRL_PLL_MODE_SEL

◆ PLL_VE_CTRL_PLL_MODE_FRACTIONAL

◆ PLL_VE_CTRL_PLL_MODE_INTEGER

◆ __PLL_VE_CTRL_PLL_FACTOR_N

◆ __PLL_VE_CTRL_PLL_PREDIV_M

◆ PLL_VE_CTRL_PLL_FACTOR_N

◆ PLL_VE_CTRL_PLL_PREDIV_M

◆ CCU_PLL_DDR_CTRL

◆ PLL_DDR_CTRL_PLL_ENABLE

◆ PLL_DDR_CTRL_LOCK

◆ PLL_DDR_CTRL_SDRAM_SIGMA_DELTA_EN

◆ PLL_DDR_CTRL_PLL_DDR_CFG_UPDATE

◆ __PLL_DDR_CTRL_PLL_FACTOR_N

◆ __PLL_DDR_CTRL_PLL_FACTOR_K

◆ __PLL_DDR_CTRL_PLL_FACTOR_M

◆ PLL_DDR_CTRL_PLL_FACTOR_N

◆ PLL_DDR_CTRL_PLL_FACTOR_K

◆ PLL_DDR_CTRL_PLL_FACTOR_M

◆ CCU_PLL_PERIPH_CTRL

◆ PLL_PERIPH_CTRL_PLL_ENABLE

◆ PLL_PERIPH_CTRL_LOCK

◆ PLL_PERIPH_CTRL_PLL_24M_OUT_EN

◆ __PLL_PERIPH_CTRL_PLL_FACTOR_N

◆ __PLL_PERIPH_CTRL_PLL_FACTOR_K

◆ PLL_PERIPH_CTRL_PLL_FACTOR_N

◆ PLL_PERIPH_CTRL_PLL_FACTOR_K

◆ CCU_CPU_CLK_SRC

◆ CPU_CLK_SRC_SEL

◆ CPU_CLK_SRC_SEL_LOSC

◆ CPU_CLK_SRC_SEL_OSC24M

◆ CPU_CLK_SRC_SEL_PLL_CPU

◆ CCU_AHB_APB_HCLKC_CFG