36#ifndef CMSDK_ARMv8MML_SP_H
37#define CMSDK_ARMv8MML_SP_H
125#if defined (__CC_ARM)
128#elif defined (__ICCARM__)
129 #pragma language=extended
130#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
131 #pragma clang diagnostic push
132 #pragma clang diagnostic ignored "-Wc11-extensions"
133 #pragma clang diagnostic ignored "-Wreserved-id-macro"
134#elif defined (__GNUC__)
136#elif defined (__TMS470__)
138#elif defined (__TASKING__)
140#elif defined (__CSMC__)
143 #warning Not supported compiler type
148#define __ARMv8MML_REV 0x0001U
149#define __SAUREGION_PRESENT 1U
150#define __MPU_PRESENT 1U
151#define __VTOR_PRESENT 1U
152#define __NVIC_PRIO_BITS 3U
153#define __Vendor_SysTickConfig 0U
154#define __FPU_PRESENT 1U
156#define __DSP_PRESENT 0U
158#include "core_armv8mml.h"
181#define CMSDK_UART_DATA_Pos 0
182#define CMSDK_UART_DATA_Msk (0xFFUL )
185#define CMSDK_UART_STATE_RXOR_Pos 3
186#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos)
188#define CMSDK_UART_STATE_TXOR_Pos 2
189#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos)
191#define CMSDK_UART_STATE_RXBF_Pos 1
192#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos)
194#define CMSDK_UART_STATE_TXBF_Pos 0
195#define CMSDK_UART_STATE_TXBF_Msk (0x1UL )
198#define CMSDK_UART_CTRL_HSTM_Pos 6
199#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos)
201#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5
202#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos)
204#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4
205#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos)
207#define CMSDK_UART_CTRL_RXIRQEN_Pos 3
208#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos)
210#define CMSDK_UART_CTRL_TXIRQEN_Pos 2
211#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos)
213#define CMSDK_UART_CTRL_RXEN_Pos 1
214#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos)
216#define CMSDK_UART_CTRL_TXEN_Pos 0
217#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL )
219#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3
220#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos)
222#define CMSDK_UART_CTRL_TXORIRQ_Pos 2
223#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos)
225#define CMSDK_UART_CTRL_RXIRQ_Pos 1
226#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos)
228#define CMSDK_UART_CTRL_TXIRQ_Pos 0
229#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL )
232#define CMSDK_UART_BAUDDIV_Pos 0
233#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL )
250#define CMSDK_TIMER_CTRL_IRQEN_Pos 3
251#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos)
253#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2
254#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos)
256#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1
257#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos)
259#define CMSDK_TIMER_CTRL_EN_Pos 0
260#define CMSDK_TIMER_CTRL_EN_Msk (0x01UL )
263#define CMSDK_TIMER_VAL_CURRENT_Pos 0
264#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFUL )
267#define CMSDK_TIMER_RELOAD_VAL_Pos 0
268#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFUL )
271#define CMSDK_TIMER_INTSTATUS_Pos 0
272#define CMSDK_TIMER_INTSTATUS_Msk (0x01UL )
275#define CMSDK_TIMER_INTCLEAR_Pos 0
276#define CMSDK_TIMER_INTCLEAR_Msk (0x01UL )
315#define CMSDK_DUALTIMER_LOAD_Pos 0
316#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFUL )
319#define CMSDK_DUALTIMER_VALUE_Pos 0
320#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFUL )
323#define CMSDK_DUALTIMER_CTRL_EN_Pos 7
324#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos)
326#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6
327#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos)
329#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5
330#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos)
332#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2
333#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos)
335#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1
336#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos)
338#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0
339#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1UL )
342#define CMSDK_DUALTIMER_INTCLR_Pos 0
343#define CMSDK_DUALTIMER_INTCLR_Msk (0x1UL )
346#define CMSDK_DUALTIMER_RIS_Pos 0
347#define CMSDK_DUALTIMER_RIS_Msk (0x1UL )
350#define CMSDK_DUALTIMER_MIS_Pos 0
351#define CMSDK_DUALTIMER_MIS_Msk (0x1UL )
354#define CMSDK_DUALTIMER_BGLOAD_Pos 0
355#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFUL )
384#define CMSDK_GPIO_DATA_Pos 0
385#define CMSDK_GPIO_DATA_Msk (0xFFFFUL )
388#define CMSDK_GPIO_DATAOUT_Pos 0
389#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFUL )
392#define CMSDK_GPIO_OUTENSET_Pos 0
393#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFUL )
396#define CMSDK_GPIO_OUTENCLR_Pos 0
397#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFUL )
400#define CMSDK_GPIO_ALTFUNCSET_Pos 0
401#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFUL )
404#define CMSDK_GPIO_ALTFUNCCLR_Pos 0
405#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFUL )
408#define CMSDK_GPIO_INTENSET_Pos 0
409#define CMSDK_GPIO_INTENSET_Msk (0xFFFFUL )
412#define CMSDK_GPIO_INTENCLR_Pos 0
413#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFUL )
416#define CMSDK_GPIO_INTTYPESET_Pos 0
417#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFUL )
420#define CMSDK_GPIO_INTTYPECLR_Pos 0
421#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFUL )
424#define CMSDK_GPIO_INTPOLSET_Pos 0
425#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFUL )
428#define CMSDK_GPIO_INTPOLCLR_Pos 0
429#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFUL )
432#define CMSDK_GPIO_INTSTATUS_Pos 0
433#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL )
436#define CMSDK_GPIO_INTCLEAR_Pos 0
437#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL )
440#define CMSDK_GPIO_MASKLOWBYTE_Pos 0
441#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFUL )
444#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0
445#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00UL )
459#define CMSDK_SYSCON_REMAP_Pos 0
460#define CMSDK_SYSCON_REMAP_Msk (0x1UL )
463#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
464#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x1UL )
467#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
468#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x1UL )
471#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
472#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos)
474#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
475#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos)
477#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
478#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos)
480#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
481#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x7UL )
484#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
485#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos)
487#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
488#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos)
490#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
491#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x1UL )
512#define CMSDK_Watchdog_LOAD_Pos 0
513#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFUL )
516#define CMSDK_Watchdog_VALUE_Pos 0
517#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFUL )
520#define CMSDK_Watchdog_CTRL_RESEN_Pos 1
521#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos)
523#define CMSDK_Watchdog_CTRL_INTEN_Pos 0
524#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1UL )
527#define CMSDK_Watchdog_INTCLR_Pos 0
528#define CMSDK_Watchdog_INTCLR_Msk (0x1UL )
531#define CMSDK_Watchdog_RAWINTSTAT_Pos 0
532#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1UL )
535#define CMSDK_Watchdog_MASKINTSTAT_Pos 0
536#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1UL )
539#define CMSDK_Watchdog_LOCK_Pos 0
540#define CMSDK_Watchdog_LOCK_Msk (0x1UL )
543#define CMSDK_Watchdog_INTEGTESTEN_Pos 0
544#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1UL )
547#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1
548#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1UL )
553#if defined (__CC_ARM)
555#elif defined (__ICCARM__)
557#elif (__ARMCC_VERSION >= 6010050)
558 #pragma clang diagnostic pop
559#elif defined (__GNUC__)
561#elif defined (__TMS470__)
563#elif defined (__TASKING__)
564 #pragma warning restore
565#elif defined (__CSMC__)
568 #warning Not supported compiler type
579#define CMSDK_FLASH_BASE (0x00000000UL)
580#define CMSDK_SRAM_BASE (0x20000000UL)
581#define CMSDK_PERIPH_BASE (0x40000000UL)
583#define CMSDK_RAM_BASE (0x20000000UL)
584#define CMSDK_APB_BASE (0x40000000UL)
585#define CMSDK_AHB_BASE (0x40010000UL)
586#define CMSDK_S_APB_BASE (0x50000000UL)
589#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
590#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
591#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
592#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
593#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
594#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
595#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
596#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
597#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
600#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
601#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
602#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
605#define CMSDK_SECURETIMER0_BASE (CMSDK_S_APB_BASE + 0x0000UL)
606#define CMSDK_SECURETIMER1_BASE (CMSDK_S_APB_BASE + 0x1000UL)
613#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
614#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
615#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
616#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
617#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
618#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
619#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
620#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
621#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
622#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
623#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
624#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
625#define CMSDK_SECURETIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER0_BASE)
626#define CMSDK_SECURETIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER1_BASE)
@ SPI_0B_IRQn
Definition CMSDK_ARMv8MML_SP.h:109
@ GPIO2_IRQn
Definition CMSDK_ARMv8MML_SP.h:77
@ GPIO1_14_IRQn
Definition CMSDK_ARMv8MML_SP.h:107
@ PendSV_IRQn
Definition CMSDK_ARMv8MML_SP.h:57
@ UART4TX_IRQn
Definition CMSDK_ARMv8MML_SP.h:82
@ TIMER1_IRQn
Definition CMSDK_ARMv8MML_SP.h:70
@ UART2RX_IRQn
Definition CMSDK_ARMv8MML_SP.h:65
@ I2S_IRQn
Definition CMSDK_ARMv8MML_SP.h:75
@ UART4RX_IRQn
Definition CMSDK_ARMv8MML_SP.h:81
@ SECURETIMER0_IRQn
Definition CMSDK_ARMv8MML_SP.h:111
@ UART2TX_IRQn
Definition CMSDK_ARMv8MML_SP.h:66
@ TIMER0_IRQn
Definition CMSDK_ARMv8MML_SP.h:69
@ UART3TX_IRQn
Definition CMSDK_ARMv8MML_SP.h:80
@ GPIO1_6_IRQn
Definition CMSDK_ARMv8MML_SP.h:99
@ GPIO0_6_IRQn
Definition CMSDK_ARMv8MML_SP.h:91
@ MemoryManagement_IRQn
Definition CMSDK_ARMv8MML_SP.h:51
@ SPI_3B_IRQn
Definition CMSDK_ARMv8MML_SP.h:115
@ SPI_4B_IRQn
Definition CMSDK_ARMv8MML_SP.h:116
@ SVCall_IRQn
Definition CMSDK_ARMv8MML_SP.h:55
@ GPIO1_10_IRQn
Definition CMSDK_ARMv8MML_SP.h:103
@ UART0TX_IRQn
Definition CMSDK_ARMv8MML_SP.h:62
@ GPIO1_5_IRQn
Definition CMSDK_ARMv8MML_SP.h:98
@ GPIO0_2_IRQn
Definition CMSDK_ARMv8MML_SP.h:87
@ GPIO3_IRQn
Definition CMSDK_ARMv8MML_SP.h:78
@ SPI_2B_IRQn
Definition CMSDK_ARMv8MML_SP.h:114
@ GPIO1ALL_IRQn
Definition CMSDK_ARMv8MML_SP.h:68
@ GPIO1_13_IRQn
Definition CMSDK_ARMv8MML_SP.h:106
@ UsageFault_IRQn
Definition CMSDK_ARMv8MML_SP.h:53
@ UART_0_1_2_OVF_IRQn
Definition CMSDK_ARMv8MML_SP.h:73
@ SysTick_IRQn
Definition CMSDK_ARMv8MML_SP.h:58
@ GPIO1_1_IRQn
Definition CMSDK_ARMv8MML_SP.h:94
@ GPIO0_3_IRQn
Definition CMSDK_ARMv8MML_SP.h:88
@ ETHERNET_IRQn
Definition CMSDK_ARMv8MML_SP.h:74
@ GPIO1_7_IRQn
Definition CMSDK_ARMv8MML_SP.h:100
@ UART1TX_IRQn
Definition CMSDK_ARMv8MML_SP.h:64
@ GPIO1_4_IRQn
Definition CMSDK_ARMv8MML_SP.h:97
@ BusFault_IRQn
Definition CMSDK_ARMv8MML_SP.h:52
@ DebugMonitor_IRQn
Definition CMSDK_ARMv8MML_SP.h:56
@ GPIO1_11_IRQn
Definition CMSDK_ARMv8MML_SP.h:104
@ GPIO0ALL_IRQn
Definition CMSDK_ARMv8MML_SP.h:67
@ SecureFault_IRQn
Definition CMSDK_ARMv8MML_SP.h:54
@ GPIO0_5_IRQn
Definition CMSDK_ARMv8MML_SP.h:90
@ UART0RX_IRQn
Definition CMSDK_ARMv8MML_SP.h:61
@ GPIO1_12_IRQn
Definition CMSDK_ARMv8MML_SP.h:105
@ HardFault_IRQn
Definition CMSDK_ARMv8MML_SP.h:50
@ GPIO0_4_IRQn
Definition CMSDK_ARMv8MML_SP.h:89
@ DUALTIMER_IRQn
Definition CMSDK_ARMv8MML_SP.h:71
@ GPIO1_0_IRQn
Definition CMSDK_ARMv8MML_SP.h:93
@ GPIO1_9_IRQn
Definition CMSDK_ARMv8MML_SP.h:102
@ GPIO0_1_IRQn
Definition CMSDK_ARMv8MML_SP.h:86
@ GPIO1_3_IRQn
Definition CMSDK_ARMv8MML_SP.h:96
@ SPI_1B_IRQn
Definition CMSDK_ARMv8MML_SP.h:113
@ TOUCHSCREEN_IRQn
Definition CMSDK_ARMv8MML_SP.h:76
@ GPIO1_8_IRQn
Definition CMSDK_ARMv8MML_SP.h:101
@ GPIO1_2_IRQn
Definition CMSDK_ARMv8MML_SP.h:95
@ SPI_3_4_IRQn
Definition CMSDK_ARMv8MML_SP.h:84
@ SECURETIMER1_IRQn
Definition CMSDK_ARMv8MML_SP.h:112
@ Reserved_IRQn
Definition CMSDK_ARMv8MML_SP.h:110
@ UART1RX_IRQn
Definition CMSDK_ARMv8MML_SP.h:63
@ NonMaskableInt_IRQn
Definition CMSDK_ARMv8MML_SP.h:49
@ GPIO0_7_IRQn
Definition CMSDK_ARMv8MML_SP.h:92
@ SPI_2_IRQn
Definition CMSDK_ARMv8MML_SP.h:83
@ SPI_0_1_IRQn
Definition CMSDK_ARMv8MML_SP.h:72
@ GPIO1_15_IRQn
Definition CMSDK_ARMv8MML_SP.h:108
@ UART3RX_IRQn
Definition CMSDK_ARMv8MML_SP.h:79
@ GPIO0_0_IRQn
Definition CMSDK_ARMv8MML_SP.h:85
IRQn
Definition f1c100s_reg.h:1131
#define __OM
Definition i_reg_gpio.h:47
#define __IM
Definition i_reg_gpio.h:42
#define __IOM
Definition i_reg_gpio.h:52
unsigned uint32_t
Definition stdint.h:9
Definition CMSDK_ARMv8MBL.h:278
Definition CMSDK_ARMv8MBL.h:301
Definition CMSDK_ARMv8MBL.h:357
Definition CMSDK_ARMv8MBL.h:447
Definition CMSDK_ARMv8MBL.h:235
Definition CMSDK_ARMv8MBL.h:165
Definition CMSDK_ARMv8MBL.h:493
CMSIS Device System Header File for CMSDK_ARMv8MML Device.