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CMSDK_CM0plus.h
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1/**************************************************************************/
8/* Copyright (c) 2011 - 2016 ARM LIMITED
9
10 All rights reserved.
11 Redistribution and use in source and binary forms, with or without
12 modification, are permitted provided that the following conditions are met:
13 - Redistributions of source code must retain the above copyright
14 notice, this list of conditions and the following disclaimer.
15 - Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18 - Neither the name of ARM nor the names of its contributors may be used
19 to endorse or promote products derived from this software without
20 specific prior written permission.
21 *
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 POSSIBILITY OF SUCH DAMAGE.
33 ---------------------------------------------------------------------------*/
34
35
36#ifndef CMSDK_CM0plus_H
37#define CMSDK_CM0plus_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43
44/* ------------------------- Interrupt Number Definition ------------------------ */
45
46typedef enum IRQn
47{
48/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
49 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
50 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
51
52
53
54 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
55
56 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
57 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
58
59/* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers ------------------ */
60 UART0RX_IRQn = 0, /* UART 0 receive interrupt */
61 UART0TX_IRQn = 1, /* UART 0 transmit interrupt */
62 UART1RX_IRQn = 2, /* UART 1 receive interrupt */
63 UART1TX_IRQn = 3, /* UART 1 transmit interrupt */
64 UART2RX_IRQn = 4, /* UART 2 receive interrupt */
65 UART2TX_IRQn = 5, /* UART 2 transmit interrupt */
66 GPIO0ALL_IRQn = 6, /* GPIO 0 combined interrupt */
67 GPIO1ALL_IRQn = 7, /* GPIO 1 combined interrupt */
68 TIMER0_IRQn = 8, /* Timer 0 interrupt */
69 TIMER1_IRQn = 9, /* Timer 1 interrupt */
70 DUALTIMER_IRQn = 10, /* Dual Timer interrupt */
71 SPI_0_1_IRQn = 11, /* SPI #0, #1 interrupt */
72 UART_0_1_2_OVF_IRQn = 12, /* UART overflow (0, 1 & 2) interrupt */
73 ETHERNET_IRQn = 13, /* Ethernet interrupt */
74 I2S_IRQn = 14, /* Audio I2S interrupt */
75 TOUCHSCREEN_IRQn = 15, /* Touch Screen interrupt */
76 GPIO2_IRQn = 16, /* GPIO 2 combined interrupt */
77 GPIO3_IRQn = 17, /* GPIO 3 combined interrupt */
78 UART3RX_IRQn = 18, /* UART 3 receive interrupt */
79 UART3TX_IRQn = 19, /* UART 3 transmit interrupt */
80 UART4RX_IRQn = 20, /* UART 4 receive interrupt */
81 UART4TX_IRQn = 21, /* UART 4 transmit interrupt */
82 SPI_2_IRQn = 22, /* SPI #2 interrupt */
83 SPI_3_4_IRQn = 23, /* SPI #3, SPI #4 interrupt */
84 GPIO0_0_IRQn = 24, /* GPIO 0 individual interrupt ( 0) */
85 GPIO0_1_IRQn = 25, /* GPIO 0 individual interrupt ( 1) */
86 GPIO0_2_IRQn = 26, /* GPIO 0 individual interrupt ( 2) */
87 GPIO0_3_IRQn = 27, /* GPIO 0 individual interrupt ( 3) */
88 GPIO0_4_IRQn = 28, /* GPIO 0 individual interrupt ( 4) */
89 GPIO0_5_IRQn = 29, /* GPIO 0 individual interrupt ( 5) */
90 GPIO0_6_IRQn = 30, /* GPIO 0 individual interrupt ( 6) */
91 GPIO0_7_IRQn = 31 /* GPIO 0 individual interrupt ( 7) */
92} IRQn_Type;
93
94
95/* ================================================================================ */
96/* ================ Processor and Core Peripheral Section ================ */
97/* ================================================================================ */
98
99/* ------- Start of section using anonymous unions and disabling warnings ------- */
100#if defined (__CC_ARM)
101 #pragma push
102 #pragma anon_unions
103#elif defined (__ICCARM__)
104 #pragma language=extended
105#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
106 #pragma clang diagnostic push
107 #pragma clang diagnostic ignored "-Wc11-extensions"
108 #pragma clang diagnostic ignored "-Wreserved-id-macro"
109#elif defined (__GNUC__)
110 /* anonymous unions are enabled by default */
111#elif defined (__TMS470__)
112 /* anonymous unions are enabled by default */
113#elif defined (__TASKING__)
114 #pragma warning 586
115#elif defined (__CSMC__)
116 /* anonymous unions are enabled by default */
117#else
118 #warning Not supported compiler type
119#endif
120
121
122/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
123#define __CM0PLUS_REV 0x0000U /* Core revision r0p0 */
124#define __MPU_PRESENT 1 /* MPU present */
125#define __VTOR_PRESENT 1 /* VTOR present */
126#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
127#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
128
129#include "core_cm0plus.h" /* Processor and core peripherals */
130#include "system_CMSDK_CM0plus.h" /* System Header */
131
132
133/* ================================================================================ */
134/* ================ Device Specific Peripheral Section ================ */
135/* ================================================================================ */
136
137/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
138typedef struct
139{
140 __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
141 __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
142 __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
143 union {
144 __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
145 __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
146 };
147 __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
148
149} CMSDK_UART_TypeDef;
150
151/* CMSDK_UART DATA Register Definitions */
152#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
153#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
154
155/* CMSDK_UART STATE Register Definitions */
156#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
157#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
158
159#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
160#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
161
162#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
163#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
164
165#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
166#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
167
168/* CMSDK_UART CTRL Register Definitions */
169#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
170#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
171
172#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
173#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
174
175#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
176#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
177
178#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
179#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
180
181#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
182#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
183
184#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
185#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
186
187#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
188#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
189
190#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
191#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
192
193#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
194#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
195
196#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
197#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
198
199#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
200#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
201
202/* CMSDK_UART BAUDDIV Register Definitions */
203#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
204#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
205
206
207/*----------------------------- Timer (TIMER) -------------------------------*/
208typedef struct
209{
210 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
211 __IOM uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
212 __IOM uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
213 union {
214 __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
215 __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
216 };
217
218} CMSDK_TIMER_TypeDef;
219
220/* CMSDK_TIMER CTRL Register Definitions */
221#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
222#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
223
224#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
225#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
226
227#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
228#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
229
230#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
231#define CMSDK_TIMER_CTRL_EN_Msk (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */
232
233/* CMSDK_TIMER VAL Register Definitions */
234#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
235#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */
236
237/* CMSDK_TIMER RELOAD Register Definitions */
238#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
239#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */
240
241/* CMSDK_TIMER INTSTATUS Register Definitions */
242#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
243#define CMSDK_TIMER_INTSTATUS_Msk (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
244
245/* CMSDK_TIMER INTCLEAR Register Definitions */
246#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
247#define CMSDK_TIMER_INTCLEAR_Msk (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
248
249
250/*------------- Timer (TIM) --------------------------------------------------*/
251typedef struct
252{
253 __IOM uint32_t T1LOAD; /* Offset: 0x000 (R/W) Timer 1 Load */
254 __IM uint32_t T1VALUE; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
255 __IOM uint32_t T1CTRL; /* Offset: 0x008 (R/W) Timer 1 Control */
256 __OM uint32_t T1INTCLR; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
257 __IM uint32_t T1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
258 __IM uint32_t T1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
259 __IOM uint32_t T1BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */
260 uint32_t RESERVED0;
261 __IOM uint32_t T2LOAD; /* Offset: 0x020 (R/W) Timer 2 Load */
262 __IM uint32_t T2VALUE; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
263 __IOM uint32_t T2CTRL; /* Offset: 0x028 (R/W) Timer 2 Control */
264 __OM uint32_t T2INTCLR; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
265 __IM uint32_t T2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
266 __IM uint32_t T2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
267 __IOM uint32_t T2BGLOAD; /* Offset: 0x038 (R/W) Background Load Register */
268 uint32_t RESERVED1[945];
269 __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
270 __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
271} CMSDK_DUALTIMER_BOTH_TypeDef;
272
273
274typedef struct
275{
276 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Timer Load */
277 __IM uint32_t VALUE; /* Offset: 0x000 (R/W) Timer Counter Current Value */
278 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Timer Control */
279 __OM uint32_t INTCLR; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
280 __IM uint32_t RIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
281 __IM uint32_t MIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
282 __IOM uint32_t BGLOAD; /* Offset: 0x000 (R/W) Background Load Register */
283} CMSDK_DUALTIMER_SINGLE_TypeDef;
284
285/* CMSDK_DUALTIMER_SINGLE LOAD Register Definitions */
286#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
287#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
288
289/* CMSDK_DUALTIMER_SINGLE VALUE Register Definitions */
290#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
291#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
292
293/* CMSDK_DUALTIMER_SINGLE CTRL Register Definitions */
294#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
295#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
296
297#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
298#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
299
300#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
301#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
302
303#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
304#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
305
306#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
307#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
308
309#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
310#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
311
312/* CMSDK_DUALTIMER_SINGLE INTCLR Register Definitions */
313#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
314#define CMSDK_DUALTIMER_INTCLR_Msk (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
315
316/* CMSDK_DUALTIMER_SINGLE RIS Register Definitions */
317#define CMSDK_DUALTIMER_RIS_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
318#define CMSDK_DUALTIMER_RIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
319
320/* CMSDK_DUALTIMER_SINGLE MIS Register Definitions */
321#define CMSDK_DUALTIMER_MIS_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
322#define CMSDK_DUALTIMER_MIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
323
324/* CMSDK_DUALTIMER_SINGLE BGLOAD Register Definitions */
325#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
326#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
327
328
329/*-------------------- General Purpose Input Output (GPIO) -------------------*/
330typedef struct
331{
332 __IOM uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
333 __IOM uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
334 uint32_t RESERVED0[2];
335 __IOM uint32_t OUTENSET; /* Offset: 0x010 (R/W) Output Enable Set Register */
336 __IOM uint32_t OUTENCLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
337 __IOM uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
338 __IOM uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
339 __IOM uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
340 __IOM uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
341 __IOM uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
342 __IOM uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
343 __IOM uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
344 __IOM uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
345 union {
346 __IM uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
347 __OM uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
348 };
349 uint32_t RESERVED1[241];
350 __IOM uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
351 __IOM uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
352} CMSDK_GPIO_TypeDef;
353
354/* CMSDK_GPIO DATA Register Definitions */
355#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
356#define CMSDK_GPIO_DATA_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */
357
358/* CMSDK_GPIO DATAOUT Register Definitions */
359#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
360#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
361
362/* CMSDK_GPIO OUTENSET Register Definitions */
363#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
364#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
365
366/* CMSDK_GPIO OUTENCLR Register Definitions */
367#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
368#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
369
370/* CMSDK_GPIO ALTFUNCSET Register Definitions */
371#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
372#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
373
374/* CMSDK_GPIO ALTFUNCCLR Register Definitions */
375#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
376#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
377
378/* CMSDK_GPIO INTENSET Register Definitions */
379#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
380#define CMSDK_GPIO_INTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
381
382/* CMSDK_GPIO INTENCLR Register Definitions */
383#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
384#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
385
386/* CMSDK_GPIO INTTYPESET Register Definitions */
387#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
388#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
389
390/* CMSDK_GPIO INTTYPECLR Register Definitions */
391#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
392#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
393
394/* CMSDK_GPIO INTPOLSET Register Definitions */
395#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
396#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
397
398/* CMSDK_GPIO INTPOLCLR Register Definitions */
399#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
400#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
401
402/* CMSDK_GPIO INTCLEAR Register Definitions */
403#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
404#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
405
406/* CMSDK_GPIO INTCLEAR Register Definitions */
407#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
408#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
409
410/* CMSDK_GPIO MASKLOWBYTE Register Definitions */
411#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
412#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
413
414/* CMSDK_GPIO MASKHIGHBYTE Register Definitions */
415#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
416#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
417
418
419/*------------- System Control (SYSCON) --------------------------------------*/
420typedef struct
421{
422 __IOM uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
423 __IOM uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
424 __IOM uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
425 __IOM uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
426 __IOM uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
427} CMSDK_SYSCON_TypeDef;
428
429/* CMSDK_SYSCON REMAP Register Definitions */
430#define CMSDK_SYSCON_REMAP_Pos 0
431#define CMSDK_SYSCON_REMAP_Msk (0x1UL /*<< CMSDK_SYSCON_REMAP_Pos*/) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
432
433/* CMSDK_SYSCON PMUCTRL Register Definitions */
434#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
435#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x1UL /*<< CMSDK_SYSCON_PMUCTRL_EN_Pos*/) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
436
437/* CMSDK_SYSCON LOCKUPRST Register Definitions */
438#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
439#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x1UL /*<< CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos*/) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
440
441/* CMSDK_SYSCON EMICTRL Register Definitions */
442#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
443#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
444
445#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
446#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
447
448#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
449#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
450
451#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
452#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x7UL /*<< CMSDK_SYSCON_EMICTRL_RCYC_Pos*/) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
453
454/* CMSDK_SYSCON RSTINFO Register Definitions */
455#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
456#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
457
458#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
459#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
460
461#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
462#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x1UL /*<< CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos*/) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
463
464
465/*------------------- Watchdog ----------------------------------------------*/
466typedef struct
467{
468
469 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
470 __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
471 __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
472 __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
473 __IM uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
474 __IM uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
475 uint32_t RESERVED0[762];
476 __IOM uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
477 uint32_t RESERVED1[191];
478 __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
479 __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
480}CMSDK_WATCHDOG_TypeDef;
481
482/* CMSDK_WATCHDOG LOAD Register Definitions */
483#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
484#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */
485
486/* CMSDK_WATCHDOG VALUE Register Definitions */
487#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
488#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */
489
490/* CMSDK_WATCHDOG CTRL Register Definitions */
491#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
492#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
493
494#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
495#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
496
497/* CMSDK_WATCHDOG INTCLR Register Definitions */
498#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
499#define CMSDK_Watchdog_INTCLR_Msk (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
500
501/* CMSDK_WATCHDOG RAWINTSTAT Register Definitions */
502#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
503#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
504
505/* CMSDK_WATCHDOG MASKINTSTAT Register Definitions */
506#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
507#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
508
509/* CMSDK_WATCHDOG LOCK Register Definitions */
510#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
511#define CMSDK_Watchdog_LOCK_Msk (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */
512
513/* CMSDK_WATCHDOG INTEGTESTEN Register Definitions */
514#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
515#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
516
517/* CMSDK_WATCHDOG INTEGTESTOUTSET Register Definitions */
518#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
519#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
520
521
522
523/* -------------------- End of section using anonymous unions ------------------- */
524#if defined (__CC_ARM)
525 #pragma pop
526#elif defined (__ICCARM__)
527 /* leave anonymous unions enabled */
528#elif (__ARMCC_VERSION >= 6010050)
529 #pragma clang diagnostic pop
530#elif defined (__GNUC__)
531 /* anonymous unions are enabled by default */
532#elif defined (__TMS470__)
533 /* anonymous unions are enabled by default */
534#elif defined (__TASKING__)
535 #pragma warning restore
536#elif defined (__CSMC__)
537 /* anonymous unions are enabled by default */
538#else
539 #warning Not supported compiler type
540#endif
541
542
543
544
545/* ================================================================================ */
546/* ================ Peripheral memory map ================ */
547/* ================================================================================ */
548
549/* Peripheral and SRAM base address */
550#define CMSDK_FLASH_BASE (0x00000000UL)
551#define CMSDK_SRAM_BASE (0x20000000UL)
552#define CMSDK_PERIPH_BASE (0x40000000UL)
553
554#define CMSDK_RAM_BASE (0x20000000UL)
555#define CMSDK_APB_BASE (0x40000000UL)
556#define CMSDK_AHB_BASE (0x40010000UL)
557
558/* APB peripherals */
559#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
560#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
561#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
562#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
563#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
564#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
565#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
566#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
567#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
568
569/* AHB peripherals */
570#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
571#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
572#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
573
574
575/* ================================================================================ */
576/* ================ Peripheral declaration ================ */
577/* ================================================================================ */
578
579#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
580#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
581#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
582#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
583#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
584#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
585#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
586#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
587#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
588#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
589#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
590#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
591
592
593#ifdef __cplusplus
594}
595#endif
596
597#endif /* CMSDK_CM0plus_H */
IRQn_Type
enum IRQn IRQn_Type
GPIO2_IRQn
@ GPIO2_IRQn
Definition CMSDK_CM0plus.h:76
PendSV_IRQn
@ PendSV_IRQn
Definition CMSDK_CM0plus.h:56
UART4TX_IRQn
@ UART4TX_IRQn
Definition CMSDK_CM0plus.h:81
TIMER1_IRQn
@ TIMER1_IRQn
Definition CMSDK_CM0plus.h:69
UART2RX_IRQn
@ UART2RX_IRQn
Definition CMSDK_CM0plus.h:64
I2S_IRQn
@ I2S_IRQn
Definition CMSDK_CM0plus.h:74
UART4RX_IRQn
@ UART4RX_IRQn
Definition CMSDK_CM0plus.h:80
UART2TX_IRQn
@ UART2TX_IRQn
Definition CMSDK_CM0plus.h:65
TIMER0_IRQn
@ TIMER0_IRQn
Definition CMSDK_CM0plus.h:68
UART3TX_IRQn
@ UART3TX_IRQn
Definition CMSDK_CM0plus.h:79
GPIO0_6_IRQn
@ GPIO0_6_IRQn
Definition CMSDK_CM0plus.h:90
SVCall_IRQn
@ SVCall_IRQn
Definition CMSDK_CM0plus.h:54
UART0TX_IRQn
@ UART0TX_IRQn
Definition CMSDK_CM0plus.h:61
GPIO0_2_IRQn
@ GPIO0_2_IRQn
Definition CMSDK_CM0plus.h:86
GPIO3_IRQn
@ GPIO3_IRQn
Definition CMSDK_CM0plus.h:77
GPIO1ALL_IRQn
@ GPIO1ALL_IRQn
Definition CMSDK_CM0plus.h:67
UART_0_1_2_OVF_IRQn
@ UART_0_1_2_OVF_IRQn
Definition CMSDK_CM0plus.h:72
SysTick_IRQn
@ SysTick_IRQn
Definition CMSDK_CM0plus.h:57
GPIO0_3_IRQn
@ GPIO0_3_IRQn
Definition CMSDK_CM0plus.h:87
ETHERNET_IRQn
@ ETHERNET_IRQn
Definition CMSDK_CM0plus.h:73
UART1TX_IRQn
@ UART1TX_IRQn
Definition CMSDK_CM0plus.h:63
GPIO0ALL_IRQn
@ GPIO0ALL_IRQn
Definition CMSDK_CM0plus.h:66
GPIO0_5_IRQn
@ GPIO0_5_IRQn
Definition CMSDK_CM0plus.h:89
UART0RX_IRQn
@ UART0RX_IRQn
Definition CMSDK_CM0plus.h:60
HardFault_IRQn
@ HardFault_IRQn
Definition CMSDK_CM0plus.h:50
GPIO0_4_IRQn
@ GPIO0_4_IRQn
Definition CMSDK_CM0plus.h:88
DUALTIMER_IRQn
@ DUALTIMER_IRQn
Definition CMSDK_CM0plus.h:70
GPIO0_1_IRQn
@ GPIO0_1_IRQn
Definition CMSDK_CM0plus.h:85
TOUCHSCREEN_IRQn
@ TOUCHSCREEN_IRQn
Definition CMSDK_CM0plus.h:75
SPI_3_4_IRQn
@ SPI_3_4_IRQn
Definition CMSDK_CM0plus.h:83
UART1RX_IRQn
@ UART1RX_IRQn
Definition CMSDK_CM0plus.h:62
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition CMSDK_CM0plus.h:49
GPIO0_7_IRQn
@ GPIO0_7_IRQn
Definition CMSDK_CM0plus.h:91
SPI_2_IRQn
@ SPI_2_IRQn
Definition CMSDK_CM0plus.h:82
SPI_0_1_IRQn
@ SPI_0_1_IRQn
Definition CMSDK_CM0plus.h:71
UART3RX_IRQn
@ UART3RX_IRQn
Definition CMSDK_CM0plus.h:78
GPIO0_0_IRQn
@ GPIO0_0_IRQn
Definition CMSDK_CM0plus.h:84
IRQn
IRQn
Definition f1c100s_reg.h:1131
__OM
#define __OM
Definition i_reg_gpio.h:47
__IM
#define __IM
Definition i_reg_gpio.h:42
__IOM
#define __IOM
Definition i_reg_gpio.h:52
uint32_t
unsigned uint32_t
Definition stdint.h:9
CMSDK_DUALTIMER_BOTH_TypeDef
Definition CMSDK_ARMv8MBL.h:278
CMSDK_DUALTIMER_SINGLE_TypeDef
Definition CMSDK_ARMv8MBL.h:301
CMSDK_GPIO_TypeDef
Definition CMSDK_ARMv8MBL.h:357
CMSDK_SYSCON_TypeDef
Definition CMSDK_ARMv8MBL.h:447
CMSDK_TIMER_TypeDef
Definition CMSDK_ARMv8MBL.h:235
CMSDK_UART_TypeDef
Definition CMSDK_ARMv8MBL.h:165
CMSDK_WATCHDOG_TypeDef
Definition CMSDK_ARMv8MBL.h:493
system_CMSDK_CM0plus.h
CMSIS Device System Header File for CMSDK_CM0plus Device.
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