Go to the source code of this file.
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enum | vsf_eth_phy_mode_t {
VSF_ETH_PHY_MODE_SPEED_10M = 1 << 0
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VSF_ETH_PHY_MODE_SPEED_100M = 1 << 1
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VSF_ETH_PHY_MODE_SPEED_1000M = 1 << 2
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VSF_ETH_PHY_MODE_DUPLEX_HALF = 1 << 3
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VSF_ETH_PHY_MODE_DUPLEX_FULL = 1 << 4
} |
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enum | vsf_eth_mode_t {
VSF_ETH_MODE_TX_CHECKSUM_OFFLOAD = 1 << 5
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VSF_ETH_MODE_RX_CHECKSUM_OFFLOAD = 1 << 6
} |
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enum | vsf_eth_irq_mask_t {
VSF_ETH_IRQ_MASK_RX_AVAILABLE = (1 << 0)
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VSF_ETH_IRQ_MASK_TX_COMPLETE = (1 << 1)
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VSF_ETH_IRQ_MASK_SG_RX_AVAILABLE = (1 << 2)
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VSF_ETH_IRQ_MASK_SG_TX_COMPLETE = (1 << 3)
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VSF_ETH_IRQ_MASK_PHY_LINK_CHANGE = (1 << 4)
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VSF_ETH_IRQ_MASK_ERROR = (1 << 5)
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VSF_ETH_IRQ_MASK_OVERFLOW = (1 << 6)
} |
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enum | vsf_eth_ctrl_t { VSF_ETH_CTRL_GET_MAC_ADDRESS
} |
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enum | vsf_eth_buf_mode_t {
VSF_ETH_BUF_MODE_TX_CHECKSUM_OFFLOAD = 1 << 0
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VSF_ETH_BUF_MODE_RX_CHECKSUM_OFFLOAD = 1 << 1
} |
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◆ __HAL_DRIVER_
#define __HAL_DRIVER_ ${SERIES/ETH_IP}_ETH_H__ |
◆ VSF_
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_PHY_MODE
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_PHY_MODE ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_MODE
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_MODE ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_IRQ_MASK
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_IRQ_MASK ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_CTRL
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_CTRL ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_CFG
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_CFG ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_STATUS
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_STATUS ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_CAPABILITY
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_CAPABILITY ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_BUF_MODE
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_BUF_MODE ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_BUF_DESC
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_BUF_DESC ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_SEND_BUF_DESC
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_SEND_BUF_DESC ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_RECV_BUF_DESC
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_RECV_BUF_DESC ENABLED |
◆ VSF_ETH_CFG_REIMPLEMENT_TYPE_SG_BUF_DESC
#define VSF_ETH_CFG_REIMPLEMENT_TYPE_SG_BUF_DESC ENABLED |
◆ vsf_eth_phy_mode_t
◆ vsf_eth_mode_t
◆ vsf_eth_irq_mask_t
◆ vsf_eth_ctrl_t
◆ vsf_eth_t
◆ vsf_eth_isr_handler_t
◆ vsf_eth_isr_t
◆ vsf_eth_cfg_t
◆ vsf_eth_status_t
◆ vsf_eth_capability_t
◆ vsf_eth_buf_mode_t
◆ vsf_eth_buf_desc_t
◆ vsf_eth_send_buf_desc_t
◆ vsf_eth_recv_buf_desc_t
◆ vsf_eth_send_sg_buf_desc_t
◆ vsf_eth_recv_sg_buf_desc_t
◆ vsf_eth_phy_mode_t
Enumerator |
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VSF_ETH_PHY_MODE_SPEED_10M | |
VSF_ETH_PHY_MODE_SPEED_100M | |
VSF_ETH_PHY_MODE_SPEED_1000M | |
VSF_ETH_PHY_MODE_DUPLEX_HALF | |
VSF_ETH_PHY_MODE_DUPLEX_FULL | |
◆ vsf_eth_mode_t
Enumerator |
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VSF_ETH_MODE_TX_CHECKSUM_OFFLOAD | |
VSF_ETH_MODE_RX_CHECKSUM_OFFLOAD | |
◆ vsf_eth_irq_mask_t
Enumerator |
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VSF_ETH_IRQ_MASK_RX_AVAILABLE | |
VSF_ETH_IRQ_MASK_TX_COMPLETE | |
VSF_ETH_IRQ_MASK_SG_RX_AVAILABLE | |
VSF_ETH_IRQ_MASK_SG_TX_COMPLETE | |
VSF_ETH_IRQ_MASK_PHY_LINK_CHANGE | |
VSF_ETH_IRQ_MASK_ERROR | |
VSF_ETH_IRQ_MASK_OVERFLOW | |
◆ vsf_eth_ctrl_t
Enumerator |
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VSF_ETH_CTRL_GET_MAC_ADDRESS | |
◆ vsf_eth_buf_mode_t
Enumerator |
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VSF_ETH_BUF_MODE_TX_CHECKSUM_OFFLOAD | |
VSF_ETH_BUF_MODE_RX_CHECKSUM_OFFLOAD | |
◆ reg
◆ isr