#include "hal/vsf_hal_cfg.h"
#include "common.h"

Macros
#define	VSF_HW_FLASH_CFG_BASE_ADDRESS 0x08000000

#define	VSF_HW_FLASH_CFG_ERASE_SECTORE_SIZE 0x1000

#define	VSF_HW_FLASH_CFG_WRITE_SECTORE_SIZE 0x100

#define	__ROM_APITBL_BASE ((unsigned int *)0x00000180UL)

#define	__ROM_FlashChipSizeGet ((unsigned int (*)(void))__ROM_APITBL_BASE[2])

#define	__ROM_FlashErase ((int (*)(unsigned int a4k, unsigned int len))__ROM_APITBL_BASE[4])

#define	__ROM_FlashWrite ((int (*)(unsigned int adr, unsigned int len, unsigned int buf))__ROM_APITBL_BASE[5])

#define	__ROM_FlashRead ((int (*)(unsigned int adr, unsigned int len, unsigned int buf))__ROM_APITBL_BASE[6])

#define	__ROM_FlashCacheInvalidRange ((void (*)(unsigned int adr, unsigned int len))__ROM_APITBL_BASE[8])

#define	VSF_AIC8800_USB_CFG_SPEED USB_SPEED_HIGH

#define	VSF_DWCOTG_HCD_WORKAROUND_PORT_DISABLE_AS_DISCONNECT ENABLED

#define	USB_OTG_COUNT 1

#define	USB_DWCOTG_MAX_EP_NUM 16

#define	USB_OTG0_IRQHandler USBDMA_IRQHandler

#define	USB_OTG0_CONFIG

#define	VSF_HW_GPIO_PORT_COUNT 2

#define	VSF_HW_GPIO_PIN_COUNT 16

#define	VSF_HW_GPIO_EXTI_PORT_MASK 0x01

#define	VSF_HW_GPIO_FUNCTION_MAX 10

#define	VSF_HW_GPIO0_BASE_ADDRESS (0x40504000UL)

#define	VSF_HW_GPIO0_IOMUX_REG_BASE (0x40503000)

#define	VSF_HW_GPIO0_MAP {1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0}

#define	VSF_HW_GPIO0_GPIO_PIN_MASK (0x00000000)

#define	VSF_HW_GPIO0_IRQ_IDX GPIO_IRQn

#define	VSF_HW_GPIO0_IRQ GPIO_IRQHandler

#define	VSF_HW_GPIO0_IS_PMIC false

#define	VSF_HW_GPIO1_BASE_ADDRESS (0x50011000UL)

#define	VSF_HW_GPIO1_IOMUX_REG_BASE (0x50012000)

#define	VSF_HW_GPIO1_MAP {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

#define	VSF_HW_GPIO1_GPIO_PIN_MASK (0x0000FFFC)

#define	VSF_HW_GPIO1_IRQ_IDX 0

#define	VSF_HW_GPIO1_IRQ GPIOB_IRQHandler

#define	VSF_HW_GPIO1_IS_PMIC true

#define	VSF_HW_RNG_COUNT 1

#define	VSF_HW_RNG_BITLEN 32

#define	VSF_HW_RNG0_IRQHandler TRNG_IRQHandler

#define	VSF_HW_RNG0_CONFIG

#define	VSF_HW_USART_COUNT 2

#define	VSF_HW_USART_MASK ((1 << 1) \| (1 << 2))

#define	VSF_HW_USART1_REG AIC_UART1_BASE

#define	VSF_HW_USART2_REG AIC_UART2_BASE

#define	VSF_HW_I2C_COUNT 1

#define	VSF_HW_I2C0_IRQ_IDX I2CM_IRQn

#define	VSF_HW_I2C0_IRQ I2CM_IRQHandler

#define	VSF_HW_I2C0_REG (AIC_I2CM_TypeDef *)AIC_I2CM0_BASE

#define	VSF_HW_I2C0_PCLKME_EN_BIT CSC_PCLKME_I2CM_EN_BIT

#define	VSF_HW_SPI_COUNT 1

#define	VSF_HW_SPI0_IRQ_IDX SPI_IRQn

#define	VSF_HW_SPI0_IRQ SPI0_IRQHandler

#define	VSF_HW_SPI0_RXDMA_IRQ_IDX DMA08_IRQn

#define	VSF_HW_SPI0_TXDMA_IRQ_IDX DMA09_IRQn

#define	VSF_HW_SPI0_RXDMA_IRQ DMA08_IRQHandler

#define	VSF_HW_SPI0_TXDMA_IRQ DMA09_IRQHandler

#define	VSF_HW_SPI0_RXDMA_CH_IDX DMA_CHANNEL_SPI0_RX

#define	VSF_HW_SPI0_TXDMA_CH_IDX DMA_CHANNEL_SPI0_TX

#define	VSF_HW_SPI0_RXDMA_CID REQ_CID_SPI_RX

#define	VSF_HW_SPI0_TXDMA_CID REQ_CID_SPI_TX

#define	VSF_HW_SPI0_PCLKME_EN_BIT CSC_PCLKME_SPI_EN_BIT

#define	VSF_HW_SPI0_OCLKME_EN_BIT CSC_OCLKME_SPI_EN_BIT

#define	VSF_HW_SPI0_HCLKME_EN_BIT CSC_HCLKME_DMA_EN_BIT

#define	VSF_HW_SDIO_COUNT 1

#define	VSF_HW_SDIO0_IRQ_IDX SDMMC_IRQn

#define	VSF_HW_SDIO0_IRQ SDMMC_IRQHandler

#define	VSF_HW_SDIO0_REG (AIC_SDMMC_TypeDef *)AIC_SDMMC_BASE

#define	VSF_HW_I2S_COUNT 2

#define	VSF_HW_I2S0_REG (HWP_AUD_PROC_T *)REG_AUD_PROC_BASE

#define	VSF_HW_I2S0_IDX 0

#define	VSF_HW_I2S0_OCLK (CSC_OCLKME_AUDIO_PROC_EN_BIT \| CSC_OCLKME_BCK0_EN_BIT)

#define	VSF_HW_I2S0_RXPATH AUD_PATH_RX01

#define	VSF_HW_I2S0_RXDMA_CH DMA_CH_1

#define	VSF_HW_I2S0_RXDMA_IRQN DMA01_IRQn

#define	VSF_HW_I2S0_TXPATH AUD_PATH_TX01

#define	VSF_HW_I2S0_TXDMA_CH DMA_CH_4

#define	VSF_HW_I2S0_TXDMA_IRQN DMA04_IRQn

#define	VSF_HW_I2S1_REG (HWP_AUD_PROC_T *)REG_AUD_PROC_BASE

#define	VSF_HW_I2S1_IDX 1

#define	VSF_HW_I2S1_OCLK (CSC_OCLKME_AUDIO_PROC_EN_BIT \| CSC_OCLKME_BCK1_EN_BIT)

#define	VSF_HW_I2S1_RXPATH AUD_PATH_RX01

#define	VSF_HW_I2S1_RXDMA_CH DMA_CH_3

#define	VSF_HW_I2S1_RXDMA_IRQN DMA03_IRQn

#define	VSF_HW_I2S1_TXPATH AUD_PATH_TX01

#define	VSF_HW_I2S1_TXDMA_CH DMA_CH_2

#define	VSF_HW_I2S1_TXDMA_IRQN DMA02_IRQn

#define	VSF_HW_ADC_COUNT 1

#define	VSF_HW_PWM_COUNT 1

#define	VSF_HW_PWM0_BASE_ADDRESS 0x50014000

#define	VSF_HW_PWM0_CHANNAL_COUNT 6

#define	VSF_HW_PWM0_TIMER_COUNT 3

#define	VSF_AIC_PWM_COUNT 3

#define	VSF_AIC_PWM0_CHANNAL_COUNT 1

#define	VSF_AIC_PWM0_CHANNAL_COUNT 1

#define	VSF_AIC_PWM1_CHANNAL_COUNT 1

#define	VSF_AIC_PWM2_CHANNAL_COUNT 1

#define	VSF_HW_FLASH_COUNT 1

#define	VSF_HW_RTC_COUNT 1

#define	VSF_HW_TIMER_COUNT 6

#define	VSF_HW_TIMER0_BASE_ADDRESS (AIC_TIM0_BASE + 0x20 * 0)

#define	VSF_HW_TIMER0_IRQN TIMER00_IRQn

#define	VSF_HW_TIMER0_OCLK_EN_BIT CSC_OCLKME_TIMER00_EN_BIT

#define	VSF_HW_TIMER0_PCLK_EN_BIT CSC_PCLKME_TIMER0_EN_BIT

#define	VSF_HW_TIMER0_IRQHandler TIMER00_IRQHandler

#define	VSF_HW_TIMER1_BASE_ADDRESS (AIC_TIM0_BASE + 0x20 * 1)

#define	VSF_HW_TIMER1_IRQN TIMER01_IRQn

#define	VSF_HW_TIMER1_OCLK_EN_BIT CSC_OCLKME_TIMER01_EN_BIT

#define	VSF_HW_TIMER1_PCLK_EN_BIT CSC_PCLKME_TIMER0_EN_BIT

#define	VSF_HW_TIMER1_IRQHandler TIMER01_IRQHandler

#define	VSF_HW_TIMER2_BASE_ADDRESS (AIC_TIM0_BASE + 0x20 * 2)

#define	VSF_HW_TIMER2_IRQN TIMER02_IRQn

#define	VSF_HW_TIMER2_OCLK_EN_BIT CSC_OCLKME_TIMER02_EN_BIT

#define	VSF_HW_TIMER2_PCLK_EN_BIT CSC_PCLKME_TIMER0_EN_BIT

#define	VSF_HW_TIMER2_IRQHandler TIMER02_IRQHandler

#define	VSF_HW_TIMER3_BASE_ADDRESS (AIC_TIM1_BASE + 0x20 * 0)

#define	VSF_HW_TIMER3_IRQN TIMER10_IRQn

#define	VSF_HW_TIMER3_OCLK_EN_BIT CSC_OCLKME_TIMER10_EN_BIT

#define	VSF_HW_TIMER3_PCLK_EN_BIT CSC_PCLKME_TIMER1_EN_BIT

#define	VSF_HW_TIMER3_IRQHandler TIMER10_IRQHandler

#define	VSF_HW_TIMER4_BASE_ADDRESS (AIC_TIM1_BASE + 0x20 * 1)

#define	VSF_HW_TIMER4_IRQN TIMER11_IRQn

#define	VSF_HW_TIMER4_OCLK_EN_BIT CSC_OCLKME_TIMER11_EN_BIT

#define	VSF_HW_TIMER4_PCLK_EN_BIT CSC_PCLKME_TIMER1_EN_BIT

#define	VSF_HW_TIMER4_IRQHandler TIMER11_IRQHandler

#define	VSF_HW_TIMER5_BASE_ADDRESS (AIC_TIM1_BASE + 0x20 * 2)

#define	VSF_HW_TIMER5_IRQN TIMER12_IRQn

#define	VSF_HW_TIMER5_OCLK_EN_BIT CSC_OCLKME_TIMER12_EN_BIT

#define	VSF_HW_TIMER5_PCLK_EN_BIT CSC_PCLKME_TIMER1_EN_BIT

#define	VSF_HW_TIMER5_IRQHandler TIMER12_IRQHandler

#define	VSF_HW_WDT_COUNT 1

#define	VSF_HW_WDT0_BASE_ADDRESS AIC_WDT0_BASE

#define	VSF_HW_WDT0_IRQN WDT0_IRQn

#define	VSF_HW_WDT0_OCLK_EN_BIT (CSC_OCLKME_RTC_WDG0_EN_BIT \| CSC_OCLKMD_RTC_ALWAYS_DIS_BIT)

#define	VSF_HW_WDT0_PCLK_EN_BIT CSC_PCLKME_WDG0_EN_BIT

#define	VSF_HW_WDT0_IRQHandler WDT0_IRQHandler

Macro Definition Documentation

◆ VSF_HW_FLASH_CFG_BASE_ADDRESS

#define VSF_HW_FLASH_CFG_BASE_ADDRESS 0x08000000

◆ VSF_HW_FLASH_CFG_ERASE_SECTORE_SIZE

#define VSF_HW_FLASH_CFG_ERASE_SECTORE_SIZE 0x1000

◆ VSF_HW_FLASH_CFG_WRITE_SECTORE_SIZE

#define VSF_HW_FLASH_CFG_WRITE_SECTORE_SIZE 0x100

◆ __ROM_APITBL_BASE

#define __ROM_APITBL_BASE ((unsigned int *)0x00000180UL)

◆ __ROM_FlashChipSizeGet

#define __ROM_FlashChipSizeGet ((unsigned int (*)(void))__ROM_APITBL_BASE[2])

◆ __ROM_FlashErase

#define __ROM_FlashErase ((int (*)(unsigned int a4k, unsigned int len))__ROM_APITBL_BASE[4])

◆ __ROM_FlashWrite

#define __ROM_FlashWrite ((int (*)(unsigned int adr, unsigned int len, unsigned int buf))__ROM_APITBL_BASE[5])

◆ __ROM_FlashRead

#define __ROM_FlashRead ((int (*)(unsigned int adr, unsigned int len, unsigned int buf))__ROM_APITBL_BASE[6])

◆ __ROM_FlashCacheInvalidRange

#define __ROM_FlashCacheInvalidRange ((void (*)(unsigned int adr, unsigned int len))__ROM_APITBL_BASE[8])

◆ VSF_AIC8800_USB_CFG_SPEED

#define VSF_AIC8800_USB_CFG_SPEED USB_SPEED_HIGH

◆ VSF_DWCOTG_HCD_WORKAROUND_PORT_DISABLE_AS_DISCONNECT

#define VSF_DWCOTG_HCD_WORKAROUND_PORT_DISABLE_AS_DISCONNECT ENABLED

◆ USB_OTG_COUNT

#define USB_OTG_COUNT 1

◆ USB_DWCOTG_MAX_EP_NUM

#define USB_DWCOTG_MAX_EP_NUM 16

◆ USB_OTG0_IRQHandler

#define USB_OTG0_IRQHandler USBDMA_IRQHandler

◆ USB_OTG0_CONFIG

#define USB_OTG0_CONFIG

Value:

            .dc_ep_num              = 4 << 1,                                   \
            .hc_ep_num              = 5,                                        \
            .reg                    = (void *)AIC_USB_BASE,                     \
            /* vk_dwcotg_hw_info_t */                                           \
                .buffer_word_size   = 948,                                      \
                .speed              = VSF_AIC8800_USB_CFG_SPEED,                \
                .dma_en             = true,                                     \
                .ulpi_en            = true,                                     \
                .utmi_en            = false,                                    \
                .vbus_en            = false,

◆ VSF_HW_GPIO_PORT_COUNT

#define VSF_HW_GPIO_PORT_COUNT 2

◆ VSF_HW_GPIO_PIN_COUNT

#define VSF_HW_GPIO_PIN_COUNT 16

◆ VSF_HW_GPIO_EXTI_PORT_MASK

#define VSF_HW_GPIO_EXTI_PORT_MASK 0x01

◆ VSF_HW_GPIO_FUNCTION_MAX

#define VSF_HW_GPIO_FUNCTION_MAX 10

◆ VSF_HW_GPIO0_BASE_ADDRESS

#define VSF_HW_GPIO0_BASE_ADDRESS (0x40504000UL)

◆ VSF_HW_GPIO0_IOMUX_REG_BASE

#define VSF_HW_GPIO0_IOMUX_REG_BASE (0x40503000)

◆ VSF_HW_GPIO0_MAP

#define VSF_HW_GPIO0_MAP {1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0}

◆ VSF_HW_GPIO0_GPIO_PIN_MASK

#define VSF_HW_GPIO0_GPIO_PIN_MASK (0x00000000)

◆ VSF_HW_GPIO0_IRQ_IDX

#define VSF_HW_GPIO0_IRQ_IDX GPIO_IRQn

◆ VSF_HW_GPIO0_IRQ

#define VSF_HW_GPIO0_IRQ GPIO_IRQHandler

◆ VSF_HW_GPIO0_IS_PMIC

#define VSF_HW_GPIO0_IS_PMIC false

◆ VSF_HW_GPIO1_BASE_ADDRESS

#define VSF_HW_GPIO1_BASE_ADDRESS (0x50011000UL)

◆ VSF_HW_GPIO1_IOMUX_REG_BASE

#define VSF_HW_GPIO1_IOMUX_REG_BASE (0x50012000)

◆ VSF_HW_GPIO1_MAP

#define VSF_HW_GPIO1_MAP {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

◆ VSF_HW_GPIO1_GPIO_PIN_MASK

#define VSF_HW_GPIO1_GPIO_PIN_MASK (0x0000FFFC)

◆ VSF_HW_GPIO1_IRQ_IDX

#define VSF_HW_GPIO1_IRQ_IDX 0

◆ VSF_HW_GPIO1_IRQ

#define VSF_HW_GPIO1_IRQ GPIOB_IRQHandler

◆ VSF_HW_GPIO1_IS_PMIC

#define VSF_HW_GPIO1_IS_PMIC true

◆ VSF_HW_RNG_COUNT

#define VSF_HW_RNG_COUNT 1

◆ VSF_HW_RNG_BITLEN

#define VSF_HW_RNG_BITLEN 32

◆ VSF_HW_RNG0_IRQHandler

#define VSF_HW_RNG0_IRQHandler TRNG_IRQHandler

◆ VSF_HW_RNG0_CONFIG

#define VSF_HW_RNG0_CONFIG

Value:

.reg = (void *)AIC_TRNG_BASE, \

.pclk = CSC_PCLKME_TRNG_EN_BIT,

◆ VSF_HW_USART_COUNT

#define VSF_HW_USART_COUNT 2

◆ VSF_HW_USART_MASK

#define VSF_HW_USART_MASK ((1 << 1) | (1 << 2))

◆ VSF_HW_USART1_REG

#define VSF_HW_USART1_REG AIC_UART1_BASE

◆ VSF_HW_USART2_REG

#define VSF_HW_USART2_REG AIC_UART2_BASE

◆ VSF_HW_I2C_COUNT

#define VSF_HW_I2C_COUNT 1

◆ VSF_HW_I2C0_IRQ_IDX

#define VSF_HW_I2C0_IRQ_IDX I2CM_IRQn

◆ VSF_HW_I2C0_IRQ

#define VSF_HW_I2C0_IRQ I2CM_IRQHandler

◆ VSF_HW_I2C0_REG

#define VSF_HW_I2C0_REG (AIC_I2CM_TypeDef *)AIC_I2CM0_BASE

◆ VSF_HW_I2C0_PCLKME_EN_BIT

#define VSF_HW_I2C0_PCLKME_EN_BIT CSC_PCLKME_I2CM_EN_BIT

◆ VSF_HW_SPI_COUNT

#define VSF_HW_SPI_COUNT 1

◆ VSF_HW_SPI0_IRQ_IDX

#define VSF_HW_SPI0_IRQ_IDX SPI_IRQn

◆ VSF_HW_SPI0_IRQ

#define VSF_HW_SPI0_IRQ SPI0_IRQHandler

◆ VSF_HW_SPI0_RXDMA_IRQ_IDX

#define VSF_HW_SPI0_RXDMA_IRQ_IDX DMA08_IRQn

◆ VSF_HW_SPI0_TXDMA_IRQ_IDX

#define VSF_HW_SPI0_TXDMA_IRQ_IDX DMA09_IRQn

◆ VSF_HW_SPI0_RXDMA_IRQ

#define VSF_HW_SPI0_RXDMA_IRQ DMA08_IRQHandler

◆ VSF_HW_SPI0_TXDMA_IRQ

#define VSF_HW_SPI0_TXDMA_IRQ DMA09_IRQHandler

◆ VSF_HW_SPI0_RXDMA_CH_IDX

#define VSF_HW_SPI0_RXDMA_CH_IDX DMA_CHANNEL_SPI0_RX

◆ VSF_HW_SPI0_TXDMA_CH_IDX

#define VSF_HW_SPI0_TXDMA_CH_IDX DMA_CHANNEL_SPI0_TX

◆ VSF_HW_SPI0_RXDMA_CID

#define VSF_HW_SPI0_RXDMA_CID REQ_CID_SPI_RX

◆ VSF_HW_SPI0_TXDMA_CID

#define VSF_HW_SPI0_TXDMA_CID REQ_CID_SPI_TX

◆ VSF_HW_SPI0_PCLKME_EN_BIT

#define VSF_HW_SPI0_PCLKME_EN_BIT CSC_PCLKME_SPI_EN_BIT

◆ VSF_HW_SPI0_OCLKME_EN_BIT

#define VSF_HW_SPI0_OCLKME_EN_BIT CSC_OCLKME_SPI_EN_BIT

◆ VSF_HW_SPI0_HCLKME_EN_BIT

#define VSF_HW_SPI0_HCLKME_EN_BIT CSC_HCLKME_DMA_EN_BIT

◆ VSF_HW_SDIO_COUNT

#define VSF_HW_SDIO_COUNT 1

◆ VSF_HW_SDIO0_IRQ_IDX

#define VSF_HW_SDIO0_IRQ_IDX SDMMC_IRQn

◆ VSF_HW_SDIO0_IRQ

#define VSF_HW_SDIO0_IRQ SDMMC_IRQHandler

◆ VSF_HW_SDIO0_REG

#define VSF_HW_SDIO0_REG (AIC_SDMMC_TypeDef *)AIC_SDMMC_BASE

◆ VSF_HW_I2S_COUNT

#define VSF_HW_I2S_COUNT 2

◆ VSF_HW_I2S0_REG

#define VSF_HW_I2S0_REG (HWP_AUD_PROC_T *)REG_AUD_PROC_BASE

◆ VSF_HW_I2S0_IDX

#define VSF_HW_I2S0_IDX 0

◆ VSF_HW_I2S0_OCLK

#define VSF_HW_I2S0_OCLK (CSC_OCLKME_AUDIO_PROC_EN_BIT | CSC_OCLKME_BCK0_EN_BIT)

◆ VSF_HW_I2S0_RXPATH

#define VSF_HW_I2S0_RXPATH AUD_PATH_RX01

◆ VSF_HW_I2S0_RXDMA_CH

#define VSF_HW_I2S0_RXDMA_CH DMA_CH_1

◆ VSF_HW_I2S0_RXDMA_IRQN

#define VSF_HW_I2S0_RXDMA_IRQN DMA01_IRQn

◆ VSF_HW_I2S0_TXPATH

#define VSF_HW_I2S0_TXPATH AUD_PATH_TX01

◆ VSF_HW_I2S0_TXDMA_CH

#define VSF_HW_I2S0_TXDMA_CH DMA_CH_4

◆ VSF_HW_I2S0_TXDMA_IRQN

#define VSF_HW_I2S0_TXDMA_IRQN DMA04_IRQn

◆ VSF_HW_I2S1_REG

#define VSF_HW_I2S1_REG (HWP_AUD_PROC_T *)REG_AUD_PROC_BASE

◆ VSF_HW_I2S1_IDX

#define VSF_HW_I2S1_IDX 1

◆ VSF_HW_I2S1_OCLK

#define VSF_HW_I2S1_OCLK (CSC_OCLKME_AUDIO_PROC_EN_BIT | CSC_OCLKME_BCK1_EN_BIT)

◆ VSF_HW_I2S1_RXPATH

#define VSF_HW_I2S1_RXPATH AUD_PATH_RX01

◆ VSF_HW_I2S1_RXDMA_CH

#define VSF_HW_I2S1_RXDMA_CH DMA_CH_3

◆ VSF_HW_I2S1_RXDMA_IRQN

#define VSF_HW_I2S1_RXDMA_IRQN DMA03_IRQn

◆ VSF_HW_I2S1_TXPATH

#define VSF_HW_I2S1_TXPATH AUD_PATH_TX01

◆ VSF_HW_I2S1_TXDMA_CH

#define VSF_HW_I2S1_TXDMA_CH DMA_CH_2

◆ VSF_HW_I2S1_TXDMA_IRQN

#define VSF_HW_I2S1_TXDMA_IRQN DMA02_IRQn

◆ VSF_HW_ADC_COUNT

#define VSF_HW_ADC_COUNT 1

◆ VSF_HW_PWM_COUNT

#define VSF_HW_PWM_COUNT 1

◆ VSF_HW_PWM0_BASE_ADDRESS

#define VSF_HW_PWM0_BASE_ADDRESS 0x50014000

◆ VSF_HW_PWM0_CHANNAL_COUNT

#define VSF_HW_PWM0_CHANNAL_COUNT 6

◆ VSF_HW_PWM0_TIMER_COUNT

#define VSF_HW_PWM0_TIMER_COUNT 3

◆ VSF_AIC_PWM_COUNT

#define VSF_AIC_PWM_COUNT 3

◆ VSF_AIC_PWM0_CHANNAL_COUNT [1/2]

#define VSF_AIC_PWM0_CHANNAL_COUNT 1

◆ VSF_AIC_PWM0_CHANNAL_COUNT [2/2]

#define VSF_AIC_PWM0_CHANNAL_COUNT 1

◆ VSF_AIC_PWM1_CHANNAL_COUNT

#define VSF_AIC_PWM1_CHANNAL_COUNT 1

◆ VSF_AIC_PWM2_CHANNAL_COUNT

#define VSF_AIC_PWM2_CHANNAL_COUNT 1

◆ VSF_HW_FLASH_COUNT

#define VSF_HW_FLASH_COUNT 1

◆ VSF_HW_RTC_COUNT

#define VSF_HW_RTC_COUNT 1

◆ VSF_HW_TIMER_COUNT

#define VSF_HW_TIMER_COUNT 6

◆ VSF_HW_TIMER0_BASE_ADDRESS

#define VSF_HW_TIMER0_BASE_ADDRESS (AIC_TIM0_BASE + 0x20 * 0)

◆ VSF_HW_TIMER0_IRQN

#define VSF_HW_TIMER0_IRQN TIMER00_IRQn

◆ VSF_HW_TIMER0_OCLK_EN_BIT

#define VSF_HW_TIMER0_OCLK_EN_BIT CSC_OCLKME_TIMER00_EN_BIT

◆ VSF_HW_TIMER0_PCLK_EN_BIT

#define VSF_HW_TIMER0_PCLK_EN_BIT CSC_PCLKME_TIMER0_EN_BIT

◆ VSF_HW_TIMER0_IRQHandler

#define VSF_HW_TIMER0_IRQHandler TIMER00_IRQHandler

◆ VSF_HW_TIMER1_BASE_ADDRESS

#define VSF_HW_TIMER1_BASE_ADDRESS (AIC_TIM0_BASE + 0x20 * 1)

◆ VSF_HW_TIMER1_IRQN

#define VSF_HW_TIMER1_IRQN TIMER01_IRQn

◆ VSF_HW_TIMER1_OCLK_EN_BIT

#define VSF_HW_TIMER1_OCLK_EN_BIT CSC_OCLKME_TIMER01_EN_BIT

◆ VSF_HW_TIMER1_PCLK_EN_BIT

#define VSF_HW_TIMER1_PCLK_EN_BIT CSC_PCLKME_TIMER0_EN_BIT

◆ VSF_HW_TIMER1_IRQHandler

#define VSF_HW_TIMER1_IRQHandler TIMER01_IRQHandler

◆ VSF_HW_TIMER2_BASE_ADDRESS

#define VSF_HW_TIMER2_BASE_ADDRESS (AIC_TIM0_BASE + 0x20 * 2)

◆ VSF_HW_TIMER2_IRQN

#define VSF_HW_TIMER2_IRQN TIMER02_IRQn

◆ VSF_HW_TIMER2_OCLK_EN_BIT

#define VSF_HW_TIMER2_OCLK_EN_BIT CSC_OCLKME_TIMER02_EN_BIT

◆ VSF_HW_TIMER2_PCLK_EN_BIT

#define VSF_HW_TIMER2_PCLK_EN_BIT CSC_PCLKME_TIMER0_EN_BIT

◆ VSF_HW_TIMER2_IRQHandler

#define VSF_HW_TIMER2_IRQHandler TIMER02_IRQHandler

◆ VSF_HW_TIMER3_BASE_ADDRESS

#define VSF_HW_TIMER3_BASE_ADDRESS (AIC_TIM1_BASE + 0x20 * 0)

◆ VSF_HW_TIMER3_IRQN

#define VSF_HW_TIMER3_IRQN TIMER10_IRQn

◆ VSF_HW_TIMER3_OCLK_EN_BIT

#define VSF_HW_TIMER3_OCLK_EN_BIT CSC_OCLKME_TIMER10_EN_BIT

◆ VSF_HW_TIMER3_PCLK_EN_BIT

#define VSF_HW_TIMER3_PCLK_EN_BIT CSC_PCLKME_TIMER1_EN_BIT

◆ VSF_HW_TIMER3_IRQHandler

#define VSF_HW_TIMER3_IRQHandler TIMER10_IRQHandler

◆ VSF_HW_TIMER4_BASE_ADDRESS

#define VSF_HW_TIMER4_BASE_ADDRESS (AIC_TIM1_BASE + 0x20 * 1)

◆ VSF_HW_TIMER4_IRQN

#define VSF_HW_TIMER4_IRQN TIMER11_IRQn

◆ VSF_HW_TIMER4_OCLK_EN_BIT

#define VSF_HW_TIMER4_OCLK_EN_BIT CSC_OCLKME_TIMER11_EN_BIT

◆ VSF_HW_TIMER4_PCLK_EN_BIT

#define VSF_HW_TIMER4_PCLK_EN_BIT CSC_PCLKME_TIMER1_EN_BIT

◆ VSF_HW_TIMER4_IRQHandler

#define VSF_HW_TIMER4_IRQHandler TIMER11_IRQHandler

◆ VSF_HW_TIMER5_BASE_ADDRESS

#define VSF_HW_TIMER5_BASE_ADDRESS (AIC_TIM1_BASE + 0x20 * 2)

◆ VSF_HW_TIMER5_IRQN

#define VSF_HW_TIMER5_IRQN TIMER12_IRQn

◆ VSF_HW_TIMER5_OCLK_EN_BIT

#define VSF_HW_TIMER5_OCLK_EN_BIT CSC_OCLKME_TIMER12_EN_BIT

◆ VSF_HW_TIMER5_PCLK_EN_BIT

#define VSF_HW_TIMER5_PCLK_EN_BIT CSC_PCLKME_TIMER1_EN_BIT

◆ VSF_HW_TIMER5_IRQHandler

#define VSF_HW_TIMER5_IRQHandler TIMER12_IRQHandler

◆ VSF_HW_WDT_COUNT

#define VSF_HW_WDT_COUNT 1

◆ VSF_HW_WDT0_BASE_ADDRESS

#define VSF_HW_WDT0_BASE_ADDRESS AIC_WDT0_BASE

◆ VSF_HW_WDT0_IRQN

#define VSF_HW_WDT0_IRQN WDT0_IRQn

◆ VSF_HW_WDT0_OCLK_EN_BIT

#define VSF_HW_WDT0_OCLK_EN_BIT (CSC_OCLKME_RTC_WDG0_EN_BIT | CSC_OCLKMD_RTC_ALWAYS_DIS_BIT)

◆ VSF_HW_WDT0_PCLK_EN_BIT

#define VSF_HW_WDT0_PCLK_EN_BIT CSC_PCLKME_WDG0_EN_BIT

◆ VSF_HW_WDT0_IRQHandler

#define VSF_HW_WDT0_IRQHandler WDT0_IRQHandler

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