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◆ __HAL_DEVICE_ALLWINNER_F1C100S_H__
#define __HAL_DEVICE_ALLWINNER_F1C100S_H__ |
◆ VSF_DEV_SWI_LIST
#define VSF_DEV_SWI_LIST 60, 61, 62, 63 |
◆ F1CX00S_DRAM_ADDR
#define F1CX00S_DRAM_ADDR 0x80000000 |
◆ F1CX00S_PLL_CPU_CLK_HZ
#define F1CX00S_PLL_CPU_CLK_HZ (408UL * 1000 * 1000) |
◆ F1CX00S_PLL_DDR_CLK_HZ
#define F1CX00S_PLL_DDR_CLK_HZ (156UL * 1000 * 1000) |
◆ F1CX00S_INTC_BASE_ADDRESS
#define F1CX00S_INTC_BASE_ADDRESS (0x01C20400ul) |
intc register base address
◆ USART_MAX_PORT
#define USART_MAX_PORT 0x03 |
◆ USART_PORT_MASK
#define USART_PORT_MASK 0x07 |
◆ VSF_HW_USART_COUNT
#define VSF_HW_USART_COUNT 3 |