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VSF Documented
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#include "hal/vsf_hal_cfg.h"#include "../../__device.h"#include "hal/driver/common/pm/pm_template.h"Go to the source code of this file.
Data Structures | |
| struct | io_wakeup_cfg_t |
| struct | vsf_pm_pclk_cfg_t |
| struct | vsf_pm_mclk_cfg_t |
| main clock config struct More... | |
| struct | vsf_pm_pll_cfg_t |
| pll config struct More... | |
Typedefs | |
| typedef enum vsf_pm_power_cfg_no_t | vsf_pm_power_cfg_no_t |
| power set index | |
| typedef enum vsf_pm_power_cfg_msk_t | vsf_pm_power_cfg_msk_t |
| power set mask | |
| typedef enum vsf_pm_sleep_mode_t | vsf_pm_sleep_mode_t |
| the lowpower mode | |
| typedef enum pm_periph_clksrc_t | pm_periph_clksrc_t |
| typedef enum pm_periph_clksel_t | pm_periph_clksel_t |
| typedef enum vsf_pm_pclk_no_t | vsf_pm_pclk_no_t |
| peripheral clock index | |
| typedef enum vsf_pm_mclk_no_t | vsf_pm_mclk_no_t |
| typedef enum vsf_pm_sclk_no_t | vsf_pm_sclk_no_t |
| Peripheral AHB Clock Macros. | |
| typedef enum vsf_pm_sclk_msk_t | vsf_pm_sclk_msk_t |
| typedef enum vsf_pm_clk_src_sel_t | vsf_pm_clk_src_sel_t |
| typedef enum vsf_pm_pll_sel_t | vsf_pm_pll_sel_t |
| typedef struct io_wakeup_cfg_t | io_wakeup_cfg_t |
| typedef struct vsf_pm_pclk_cfg_t | vsf_pm_pclk_cfg_t |
| typedef struct vsf_pm_mclk_cfg_t | vsf_pm_mclk_cfg_t |
| main clock config struct | |
| typedef struct vsf_pm_pll_cfg_t | vsf_pm_pll_cfg_t |
| pll config struct | |
Enumerations | |
| enum | vsf_pm_power_cfg_no_t { __def_idx =(POWER_HXT, 0) , __def_idx =(POWER_HXT, 0) , __def_idx =(POWER_HXT, 0) , __def_idx =(POWER_HXT, 0) } |
| power set index More... | |
| enum | vsf_pm_power_cfg_msk_t { __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) } |
| power set mask More... | |
| enum | vsf_pm_sleep_mode_t { VSF_PM_NPD = 0 , VSF_PM_LLPD = 1 , VSF_PM_FWPD = 2 , VSF_PM_SPD0 = 4 , VSF_PM_SPD1 = 5 , VSF_PM_DPD = 6 , VSF_PM_WAIT = VSF_PM_NPD , VSF_PM_SLEEP = VSF_PM_NPD , VSF_PM_DEEP_SLEEP = VSF_PM_DPD , VSF_PM_POWER_OFF = VSF_PM_DPD } |
| the lowpower mode More... | |
| enum | pm_periph_clksrc_t { CLKSRC_HXT , CLKSRC_HXTD2 , CLKSRC_LXT , CLKSRC_HIRC , CLKSRC_HIRCD2 , CLKSRC_LIRC , CLKSRC_PLL , CLKSRC_HCLK , CLKSRC_HCLKD2 , CLKSRC_HCLKD2K , CLKSRC_PCLK0 , CLKSRC_PCLK1 , CLKSRC_TM0_PIN , CLKSRC_TM1_PIN , CLKSRC_TM2_PIN , CLKSRC_TM3_PIN } |
| enum | pm_periph_clksel_t { SDH_CLKSEL_MAP_IDX = 0 , SDH_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_PLL << 4) | (CLKSRC_HCLK << 8) | (CLKSRC_HIRC << 12) , STCLK_CLKSEL_MAP_IDX = 1 , STCLK_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_HXTD2 << 8) | (CLKSRC_HCLKD2 << 12) | (CLKSRC_HIRCD2 << 28) , HCLK_CLKSEL_MAP_IDX = 2 , HCLK_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_PLL << 8) | (CLKSRC_LIRC << 12) | (CLKSRC_HIRC << 28) , WWDT_CLKSEL_MAP_IDX = 3 , WWDT_CLKSEL_MAP = (CLKSRC_HCLKD2K << 8) | (CLKSRC_LIRC << 12) , CLKO_CLKSEL_MAP_IDX = 4 , CLKO_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_HCLK << 8) | (CLKSRC_HIRC << 12) , UART_CLKSEL_MAP_IDX = 5 , UART_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_PLL << 4) | (CLKSRC_LXT << 8) | (CLKSRC_HIRC << 12) , TMR3_CLKSEL_MAP_IDX = 6 , TMR3_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_PCLK1 << 8) | (CLKSRC_TM3_PIN << 12) | (CLKSRC_LIRC << 20) | (CLKSRC_HIRC << 28) , TMR2_CLKSEL_MAP_IDX = 7 , TMR2_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_PCLK1 << 8) | (CLKSRC_TM2_PIN << 12) | (CLKSRC_LIRC << 20) | (CLKSRC_HIRC << 28) , TMR1_CLKSEL_MAP_IDX = 8 , TMR1_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_PCLK0 << 8) | (CLKSRC_TM1_PIN << 12) | (CLKSRC_LIRC << 20) | (CLKSRC_HIRC << 28) , TMR0_CLKSEL_MAP_IDX = 9 , TMR0_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_LXT << 4) | (CLKSRC_PCLK0 << 8) | (CLKSRC_TM0_PIN << 12) | (CLKSRC_LIRC << 20) | (CLKSRC_HIRC << 28) , WDT_CLKSEL_MAP_IDX = 10 , WDT_CLKSEL_MAP = (CLKSRC_LXT << 4) | (CLKSRC_HCLKD2K << 8) | (CLKSRC_LIRC << 12) , SPI13_CLKSEL_MAP_IDX = 11 , SPI13_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_PLL << 4) | (CLKSRC_PCLK0 << 8) | (CLKSRC_HIRC << 12) , SPI02_CLKSEL_MAP_IDX = 12 , SPI02_CLKSEL_MAP = (CLKSRC_HXT << 0) | (CLKSRC_PLL << 4) | (CLKSRC_PCLK1 << 8) | (CLKSRC_HIRC << 12) , BPWM1_CLKSEL_MAP_IDX = 13 , BPWM1_CLKSEL_MAP = (CLKSRC_PLL << 0) | (CLKSRC_PCLK1 << 4) , BPWM0_CLKSEL_MAP_IDX = 14 , BPWM0_CLKSEL_MAP = (CLKSRC_PLL << 0) | (CLKSRC_PCLK0 << 4) , RTC_CLKSEL_MAP_IDX = 15 , RTC_CLKSEL_MAP = (CLKSRC_LXT << 0) | (CLKSRC_LIRC << 4) , SDH0_CLKSEL_MAP_IDX = SDH_CLKSEL_MAP_IDX , SDH1_CLKSEL_MAP_IDX = SDH_CLKSEL_MAP_IDX , UART0_CLKSEL_MAP_IDX = UART_CLKSEL_MAP_IDX , UART1_CLKSEL_MAP_IDX = UART_CLKSEL_MAP_IDX , UART2_CLKSEL_MAP_IDX = UART_CLKSEL_MAP_IDX , UART3_CLKSEL_MAP_IDX = UART_CLKSEL_MAP_IDX , UART4_CLKSEL_MAP_IDX = UART_CLKSEL_MAP_IDX , UART5_CLKSEL_MAP_IDX = UART_CLKSEL_MAP_IDX , SPI0_CLKSEL_MAP_IDX = SPI02_CLKSEL_MAP_IDX , SPI1_CLKSEL_MAP_IDX = SPI13_CLKSEL_MAP_IDX , SPI2_CLKSEL_MAP_IDX = SPI02_CLKSEL_MAP_IDX , SPI3_CLKSEL_MAP_IDX = SPI13_CLKSEL_MAP_IDX , QSPI0_CLKSEL_MAP_IDX = SPI13_CLKSEL_MAP_IDX , EPWM1_CLKSEL_MAP_IDX = BPWM1_CLKSEL_MAP_IDX , EPWM0_CLKSEL_MAP_IDX = BPWM0_CLKSEL_MAP_IDX , I2S0_CLKSEL_MAP_IDX = SPI13_CLKSEL_MAP_IDX , SC0_CLKSEL_MAP_IDX = SPI13_CLKSEL_MAP_IDX , SC1_CLKSEL_MAP_IDX = SPI02_CLKSEL_MAP_IDX , SC2_CLKSEL_MAP_IDX = SPI13_CLKSEL_MAP_IDX } |
| enum | vsf_pm_pclk_no_t { M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) , M480_BIT_FIELD =( HCLK_CLKSEL, 0, 3, true) , __def_pclk =( PCLK_WWDT, WWDT_CLKSEL, 0, WWDT_CLKSEL_MAP_IDX) } |
| peripheral clock index More... | |
| enum | vsf_pm_mclk_no_t { VSF_MCLK_CORE_IDX = 0 } |
| enum | vsf_pm_sclk_no_t { __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) , __def_sclk_idx =( SCLK_DMA, 0, 1 ) } |
| Peripheral AHB Clock Macros. More... | |
| enum | vsf_pm_sclk_msk_t { __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) , __def_msk =(POWER_HXT) } |
| enum | vsf_pm_clk_src_sel_t { __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) , __def_clk_src =( HCLK_CLKSRC_HXT, 0) } |
| enum | vsf_pm_pll_sel_t { VSF_PLL0_IDX } |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_PLL_CFG ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_PLL_SEL ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_POWER_NUMBER ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_POWER_NUMBER_MASK ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_SLEEP_MODE ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_PCLK_NUMBER ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_PCLK_CFG ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_SCLK_NUMBER ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_SCLK_NUMBER_MASK ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_SCLK_SEL ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_MCLK_CFG ENABLED |
| #define VSF_PM_CFG_REIMPLEMENT_TYPE_MCLK_NO ENABLED |
| #define __def_idx | ( | __name, | |
| __no | |||
| ) | VSF_MCONNECT2(__name, _IDX) = (__no) |
| #define __def_msk | ( | __name | ) | VSF_MCONNECT2(__name, _MSK) = VSF_BIT(VSF_MCONNECT2(__name, _IDX) & 0x1F) |
| #define __def_pclk | ( | __name, | |
| __bf_clksel, | |||
| __bf_clkdiv, | |||
| __clksel_map_idx | |||
| ) |
| #define __def_sclk_idx | ( | __name, | |
| __bus_idx, | |||
| __bit_idx | |||
| ) | VSF_MCONNECT2(__name, _IDX) = ((__bit_idx) << 0) | ((__bus_idx) << 5) |
| #define VSF_PM_CFG_DEC_PREFIX vsf_hw |
| #define VSF_PM_CFG_DEC_UPCASE_PREFIX VSF_HW |
| typedef enum vsf_pm_power_cfg_no_t vsf_pm_power_cfg_no_t |
power set index
| typedef enum vsf_pm_power_cfg_msk_t vsf_pm_power_cfg_msk_t |
power set mask
| typedef enum vsf_pm_sleep_mode_t vsf_pm_sleep_mode_t |
the lowpower mode
| typedef enum pm_periph_clksrc_t pm_periph_clksrc_t |
| typedef enum pm_periph_clksel_t pm_periph_clksel_t |
| typedef enum vsf_pm_pclk_no_t vsf_pm_pclk_no_t |
peripheral clock index
| typedef enum vsf_pm_mclk_no_t vsf_pm_mclk_no_t |
| typedef enum vsf_pm_sclk_no_t vsf_pm_sclk_no_t |
Peripheral AHB Clock Macros.
| typedef enum vsf_pm_sclk_msk_t vsf_pm_sclk_msk_t |
| typedef enum vsf_pm_clk_src_sel_t vsf_pm_clk_src_sel_t |
| typedef enum vsf_pm_pll_sel_t vsf_pm_pll_sel_t |
| typedef struct io_wakeup_cfg_t io_wakeup_cfg_t |
| typedef struct vsf_pm_pclk_cfg_t vsf_pm_pclk_cfg_t |
| typedef struct vsf_pm_mclk_cfg_t vsf_pm_mclk_cfg_t |
main clock config struct
| typedef struct vsf_pm_pll_cfg_t vsf_pm_pll_cfg_t |
pll config struct
| enum vsf_pm_sleep_mode_t |
| enum pm_periph_clksrc_t |
| enum pm_periph_clksel_t |
| enum vsf_pm_pclk_no_t |
peripheral clock index
| enum vsf_pm_mclk_no_t |
| enum vsf_pm_sclk_no_t |
Peripheral AHB Clock Macros.
| enum vsf_pm_sclk_msk_t |
| enum vsf_pm_clk_src_sel_t |
| enum vsf_pm_pll_sel_t |
1.9.8