#include "hal/vsf_hal_cfg.h"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/resets.h"
#include "hardware/structs/adc.h"
#include "hardware/structs/clocks.h"
#include "hardware/structs/dma.h"
#include "hardware/structs/io_bank0.h"
#include "hardware/structs/pads_bank0.h"
#include "hardware/structs/pwm.h"
#include "hardware/structs/resets.h"
#include "hardware/structs/rosc.h"
#include "hardware/structs/rtc.h"
#include "hardware/structs/sio.h"
#include "hardware/structs/spi.h"
#include "hardware/structs/timer.h"
#include "hardware/structs/watchdog.h"
#include "hardware/regs/adc.h"
#include "hardware/regs/dma.h"
#include "hardware/regs/psm.h"
#include "hardware/regs/pwm.h"
#include "hardware/regs/rtc.h"
#include "hardware/regs/spi.h"
#include "hardware/regs/timer.h"
#include "hardware/regs/watchdog.h"

Macros
#define	VSF_DEV_SWI_LIST 26, 27, 28

#define	USB_OTG_COUNT 1

#define	USB_DWCOTG_MAX_EP_NUM 16

#define	USB_OTG0_IRQHandler USBDMA_IRQHandler

#define	USB_OTG0_CONFIG

#define	VSF_HW_I2C_COUNT 2

#define	VSF_HW_I2C0_IRQN I2C0_IRQ_IRQn

#define	VSF_HW_I2C0_IRQHandler I2C0_IRQHandler

#define	VSF_HW_I2C0_REG I2C0_BASE

#define	VSF_HW_I2C0_RST_BIT (1u << RESET_I2C0)

#define	VSF_HW_I2C1_IRQN I2C1_IRQ_IRQn

#define	VSF_HW_I2C1_IRQHandler I2C1_IRQHandler

#define	VSF_HW_I2C1_REG I2C1_BASE

#define	VSF_HW_I2C1_RST_BIT (1u << RESET_I2C1)

#define	VSF_HW_USART_COUNT 2

#define	VSF_HW_USART0_IRQN UART0_IRQ_IRQn

#define	VSF_HW_USART0_IRQHandler UART0_IRQHandler

#define	VSF_HW_USART0_REG UART0_BASE

#define	VSF_HW_USART0_RST_BIT (1u << RESET_UART0)

#define	VSF_HW_USART1_IRQN UART1_IRQ_IRQn

#define	VSF_HW_USART1_IRQHandler UART1_IRQHandler

#define	VSF_HW_USART1_REG UART1_BASE

#define	VSF_HW_USART1_RST_BIT (1u << RESET_UART1)

#define	VSF_HW_USART0_TX_DREQ 20

#define	VSF_HW_USART0_RX_DREQ 21

#define	VSF_HW_USART1_TX_DREQ 22

#define	VSF_HW_USART1_RX_DREQ 23

#define	VSF_HW_GPIO_PORT_COUNT 1

#define	VSF_HW_GPIO_PIN_COUNT 30

#define	VSF_HW_GPIO_PIN_MASK 0x3FFFFFFFu

#define	VSF_HW_GPIO0_IRQN IO_IRQ_BANK0_IRQn

#define	VSF_GPIO_CFG_PORT0

#define	VSF_GPIO_CFG_PIN_COUNT 30

#define	VSF_HW_RTC_COUNT 1

#define	VSF_HW_RTC0_IRQN RTC_IRQ_IRQn

#define	VSF_HW_RTC0_IRQHandler RTC_IRQHandler

#define	VSF_HW_RTC0_REG RTC_BASE

#define	VSF_HW_RTC0_RST_BIT (1u << RESET_RTC)

#define	VSF_HW_FLASH_COUNT 1

#define	VSF_HW_FLASH0_SIZE (2 * 1024 * 1024)

#define	VSF_HW_FLASH0_SECTOR_SIZE 4096

#define	VSF_HW_FLASH0_PAGE_SIZE 256

#define	VSF_HW_FLASH0_SECTOR_NUM 512

#define	VSF_HW_FLASH0_BLOCK_SIZE 65536

#define	VSF_HW_FLASH0_XIP_BASE XIP_BASE

#define	VSF_HW_WDT_COUNT 1

#define	VSF_HW_WDT0_REG WATCHDOG_BASE

#define	VSF_HW_ADC_COUNT 1

#define	VSF_HW_ADC0_REG ADC_BASE

#define	VSF_HW_ADC0_RST_BIT (1u << RESET_ADC)

#define	VSF_HW_ADC0_IRQN ADC_IRQ_FIFO_IRQn

#define	VSF_HW_ADC0_IRQHandler ADC_IRQ_FIFO_IRQHandler

#define	VSF_HW_ADC_CHANNEL_COUNT 5

#define	VSF_HW_ADC_TEMP_SENSOR_CHANNEL 4

#define	VSF_HW_ADC_MAX_DATA_BITS 12

#define	VSF_HW_PWM_COUNT 8

#define	VSF_HW_PWM0_IRQN PWM_IRQ_WRAP_IRQn

#define	VSF_HW_PWM_IRQHandler PWM_IRQ_WRAP_IRQHandler

#define	VSF_HW_PWM0_REG PWM_BASE

#define	VSF_HW_PWM0_RST_BIT (1u << RESET_PWM)

#define	VSF_HW_PWM1_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM1_REG PWM_BASE

#define	VSF_HW_PWM1_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_PWM2_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM2_REG PWM_BASE

#define	VSF_HW_PWM2_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_PWM3_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM3_REG PWM_BASE

#define	VSF_HW_PWM3_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_PWM4_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM4_REG PWM_BASE

#define	VSF_HW_PWM4_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_PWM5_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM5_REG PWM_BASE

#define	VSF_HW_PWM5_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_PWM6_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM6_REG PWM_BASE

#define	VSF_HW_PWM6_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_PWM7_IRQN VSF_HW_PWM0_IRQN

#define	VSF_HW_PWM7_REG PWM_BASE

#define	VSF_HW_PWM7_RST_BIT VSF_HW_PWM0_RST_BIT

#define	VSF_HW_TIMER_COUNT 4

#define	VSF_HW_TIMER0_REG TIMER_BASE

#define	VSF_HW_TIMER1_REG TIMER_BASE

#define	VSF_HW_TIMER2_REG TIMER_BASE

#define	VSF_HW_TIMER3_REG TIMER_BASE

#define	VSF_HW_TIMER0_IRQN TIMER_IRQ_0_IRQn

#define	VSF_HW_TIMER1_IRQN TIMER_IRQ_1_IRQn

#define	VSF_HW_TIMER2_IRQN TIMER_IRQ_2_IRQn

#define	VSF_HW_TIMER3_IRQN TIMER_IRQ_3_IRQn

#define	VSF_HW_TIMER0_IRQHandler TIMER_IRQ_0_IRQHandler

#define	VSF_HW_TIMER1_IRQHandler TIMER_IRQ_1_IRQHandler

#define	VSF_HW_TIMER2_IRQHandler TIMER_IRQ_2_IRQHandler

#define	VSF_HW_TIMER3_IRQHandler TIMER_IRQ_3_IRQHandler

#define	VSF_HW_TIMER_CHANNEL_COUNT 2

#define	VSF_HW_SPI_COUNT 2

#define	VSF_HW_SPI0_IRQN SPI0_IRQ_IRQn

#define	VSF_HW_SPI0_IRQHandler SPI0_IRQHandler

#define	VSF_HW_SPI0_REG SPI0_BASE

#define	VSF_HW_SPI0_RST_BIT (1u << RESET_SPI0)

#define	VSF_HW_SPI1_IRQN SPI1_IRQ_IRQn

#define	VSF_HW_SPI1_IRQHandler SPI1_IRQHandler

#define	VSF_HW_SPI1_REG SPI1_BASE

#define	VSF_HW_SPI1_RST_BIT (1u << RESET_SPI1)

#define	VSF_HW_RNG_COUNT 1

#define	VSF_HW_RNG_BITLEN 32

#define	VSF_HW_DMA_COUNT 1

#define	VSF_HW_DMA_MASK 0x1

#define	VSF_HW_DMA_CHANNEL_NUM 12

#define	VSF_HW_DMA0_REG DMA_BASE

#define	VSF_HW_DMA0_RST_BIT (1u << RESET_DMA)

#define	VSF_HW_DMA0_IRQN DMA_IRQ_0_IRQn

#define	VSF_HW_DMA0_IRQN_0 VSF_HW_DMA0_IRQN

#define	VSF_HW_DMA0_IRQN_1 DMA_IRQ_1_IRQn

#define	VSF_HW_DMA0_IRQHandler VSF_HW_DMA0_IRQ_0_Handler

#define	VSF_HW_DMA0_IRQ_0_Handler DMA_IRQ_0_Handler

#define	VSF_HW_DMA0_IRQ_1_Handler DMA_IRQ_1_Handler

#define	VSF_HW_DMA0_IRQ_Handler_COUNT 2

Macro Definition Documentation

◆ VSF_DEV_SWI_LIST

#define VSF_DEV_SWI_LIST 26, 27, 28

◆ USB_OTG_COUNT

#define USB_OTG_COUNT 1

◆ USB_DWCOTG_MAX_EP_NUM

#define USB_DWCOTG_MAX_EP_NUM 16

◆ USB_OTG0_IRQHandler

#define USB_OTG0_IRQHandler USBDMA_IRQHandler

◆ USB_OTG0_CONFIG

#define USB_OTG0_CONFIG

Value:

    .dc_ep_num = 4 << 1, .hc_ep_num = 5,                                        \
    .reg = (void *)0, /* vk_dwcotg_hw_info_t */                                 \
        .buffer_word_size = 948, .speed = USB_SPEED_FULL, .dma_en = true,       \
    .ulpi_en = true, .utmi_en = false, .vbus_en = false,

◆ VSF_HW_I2C_COUNT

#define VSF_HW_I2C_COUNT 2

◆ VSF_HW_I2C0_IRQN

#define VSF_HW_I2C0_IRQN I2C0_IRQ_IRQn

◆ VSF_HW_I2C0_IRQHandler

#define VSF_HW_I2C0_IRQHandler I2C0_IRQHandler

◆ VSF_HW_I2C0_REG

#define VSF_HW_I2C0_REG I2C0_BASE

◆ VSF_HW_I2C0_RST_BIT

#define VSF_HW_I2C0_RST_BIT (1u << RESET_I2C0)

◆ VSF_HW_I2C1_IRQN

#define VSF_HW_I2C1_IRQN I2C1_IRQ_IRQn

◆ VSF_HW_I2C1_IRQHandler

#define VSF_HW_I2C1_IRQHandler I2C1_IRQHandler

◆ VSF_HW_I2C1_REG

#define VSF_HW_I2C1_REG I2C1_BASE

◆ VSF_HW_I2C1_RST_BIT

#define VSF_HW_I2C1_RST_BIT (1u << RESET_I2C1)

◆ VSF_HW_USART_COUNT

#define VSF_HW_USART_COUNT 2

◆ VSF_HW_USART0_IRQN

#define VSF_HW_USART0_IRQN UART0_IRQ_IRQn

◆ VSF_HW_USART0_IRQHandler

#define VSF_HW_USART0_IRQHandler UART0_IRQHandler

◆ VSF_HW_USART0_REG

#define VSF_HW_USART0_REG UART0_BASE

◆ VSF_HW_USART0_RST_BIT

#define VSF_HW_USART0_RST_BIT (1u << RESET_UART0)

◆ VSF_HW_USART1_IRQN

#define VSF_HW_USART1_IRQN UART1_IRQ_IRQn

◆ VSF_HW_USART1_IRQHandler

#define VSF_HW_USART1_IRQHandler UART1_IRQHandler

◆ VSF_HW_USART1_REG

#define VSF_HW_USART1_REG UART1_BASE

◆ VSF_HW_USART1_RST_BIT

#define VSF_HW_USART1_RST_BIT (1u << RESET_UART1)

◆ VSF_HW_USART0_TX_DREQ

#define VSF_HW_USART0_TX_DREQ 20

◆ VSF_HW_USART0_RX_DREQ

#define VSF_HW_USART0_RX_DREQ 21

◆ VSF_HW_USART1_TX_DREQ

#define VSF_HW_USART1_TX_DREQ 22

◆ VSF_HW_USART1_RX_DREQ

#define VSF_HW_USART1_RX_DREQ 23

◆ VSF_HW_GPIO_PORT_COUNT

#define VSF_HW_GPIO_PORT_COUNT 1

◆ VSF_HW_GPIO_PIN_COUNT

#define VSF_HW_GPIO_PIN_COUNT 30

◆ VSF_HW_GPIO_PIN_MASK

#define VSF_HW_GPIO_PIN_MASK 0x3FFFFFFFu

◆ VSF_HW_GPIO0_IRQN

#define VSF_HW_GPIO0_IRQN IO_IRQ_BANK0_IRQn

◆ VSF_GPIO_CFG_PORT0

#define VSF_GPIO_CFG_PORT0

◆ VSF_GPIO_CFG_PIN_COUNT

#define VSF_GPIO_CFG_PIN_COUNT 30

◆ VSF_HW_RTC_COUNT

#define VSF_HW_RTC_COUNT 1

◆ VSF_HW_RTC0_IRQN

#define VSF_HW_RTC0_IRQN RTC_IRQ_IRQn

◆ VSF_HW_RTC0_IRQHandler

#define VSF_HW_RTC0_IRQHandler RTC_IRQHandler

◆ VSF_HW_RTC0_REG

#define VSF_HW_RTC0_REG RTC_BASE

◆ VSF_HW_RTC0_RST_BIT

#define VSF_HW_RTC0_RST_BIT (1u << RESET_RTC)

◆ VSF_HW_FLASH_COUNT

#define VSF_HW_FLASH_COUNT 1

◆ VSF_HW_FLASH0_SIZE

#define VSF_HW_FLASH0_SIZE (2 * 1024 * 1024)

◆ VSF_HW_FLASH0_SECTOR_SIZE

#define VSF_HW_FLASH0_SECTOR_SIZE 4096

◆ VSF_HW_FLASH0_PAGE_SIZE

#define VSF_HW_FLASH0_PAGE_SIZE 256

◆ VSF_HW_FLASH0_SECTOR_NUM

#define VSF_HW_FLASH0_SECTOR_NUM 512

◆ VSF_HW_FLASH0_BLOCK_SIZE

#define VSF_HW_FLASH0_BLOCK_SIZE 65536

◆ VSF_HW_FLASH0_XIP_BASE

#define VSF_HW_FLASH0_XIP_BASE XIP_BASE

◆ VSF_HW_WDT_COUNT

#define VSF_HW_WDT_COUNT 1

◆ VSF_HW_WDT0_REG

#define VSF_HW_WDT0_REG WATCHDOG_BASE

◆ VSF_HW_ADC_COUNT

#define VSF_HW_ADC_COUNT 1

◆ VSF_HW_ADC0_REG

#define VSF_HW_ADC0_REG ADC_BASE

◆ VSF_HW_ADC0_RST_BIT

#define VSF_HW_ADC0_RST_BIT (1u << RESET_ADC)

◆ VSF_HW_ADC0_IRQN

#define VSF_HW_ADC0_IRQN ADC_IRQ_FIFO_IRQn

◆ VSF_HW_ADC0_IRQHandler

#define VSF_HW_ADC0_IRQHandler ADC_IRQ_FIFO_IRQHandler

◆ VSF_HW_ADC_CHANNEL_COUNT

#define VSF_HW_ADC_CHANNEL_COUNT 5

◆ VSF_HW_ADC_TEMP_SENSOR_CHANNEL

#define VSF_HW_ADC_TEMP_SENSOR_CHANNEL 4

◆ VSF_HW_ADC_MAX_DATA_BITS

#define VSF_HW_ADC_MAX_DATA_BITS 12

◆ VSF_HW_PWM_COUNT

#define VSF_HW_PWM_COUNT 8

◆ VSF_HW_PWM0_IRQN

#define VSF_HW_PWM0_IRQN PWM_IRQ_WRAP_IRQn

◆ VSF_HW_PWM_IRQHandler

#define VSF_HW_PWM_IRQHandler ( void ) PWM_IRQ_WRAP_IRQHandler

◆ VSF_HW_PWM0_REG

#define VSF_HW_PWM0_REG PWM_BASE

◆ VSF_HW_PWM0_RST_BIT

#define VSF_HW_PWM0_RST_BIT (1u << RESET_PWM)

◆ VSF_HW_PWM1_IRQN

#define VSF_HW_PWM1_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM1_REG

#define VSF_HW_PWM1_REG PWM_BASE

◆ VSF_HW_PWM1_RST_BIT

#define VSF_HW_PWM1_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_PWM2_IRQN

#define VSF_HW_PWM2_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM2_REG

#define VSF_HW_PWM2_REG PWM_BASE

◆ VSF_HW_PWM2_RST_BIT

#define VSF_HW_PWM2_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_PWM3_IRQN

#define VSF_HW_PWM3_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM3_REG

#define VSF_HW_PWM3_REG PWM_BASE

◆ VSF_HW_PWM3_RST_BIT

#define VSF_HW_PWM3_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_PWM4_IRQN

#define VSF_HW_PWM4_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM4_REG

#define VSF_HW_PWM4_REG PWM_BASE

◆ VSF_HW_PWM4_RST_BIT

#define VSF_HW_PWM4_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_PWM5_IRQN

#define VSF_HW_PWM5_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM5_REG

#define VSF_HW_PWM5_REG PWM_BASE

◆ VSF_HW_PWM5_RST_BIT

#define VSF_HW_PWM5_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_PWM6_IRQN

#define VSF_HW_PWM6_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM6_REG

#define VSF_HW_PWM6_REG PWM_BASE

◆ VSF_HW_PWM6_RST_BIT

#define VSF_HW_PWM6_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_PWM7_IRQN

#define VSF_HW_PWM7_IRQN VSF_HW_PWM0_IRQN

◆ VSF_HW_PWM7_REG

#define VSF_HW_PWM7_REG PWM_BASE

◆ VSF_HW_PWM7_RST_BIT

#define VSF_HW_PWM7_RST_BIT VSF_HW_PWM0_RST_BIT

◆ VSF_HW_TIMER_COUNT

#define VSF_HW_TIMER_COUNT 4

◆ VSF_HW_TIMER0_REG

#define VSF_HW_TIMER0_REG TIMER_BASE

◆ VSF_HW_TIMER1_REG

#define VSF_HW_TIMER1_REG TIMER_BASE

◆ VSF_HW_TIMER2_REG

#define VSF_HW_TIMER2_REG TIMER_BASE

◆ VSF_HW_TIMER3_REG

#define VSF_HW_TIMER3_REG TIMER_BASE

◆ VSF_HW_TIMER0_IRQN

#define VSF_HW_TIMER0_IRQN TIMER_IRQ_0_IRQn

◆ VSF_HW_TIMER1_IRQN

#define VSF_HW_TIMER1_IRQN TIMER_IRQ_1_IRQn

◆ VSF_HW_TIMER2_IRQN

#define VSF_HW_TIMER2_IRQN TIMER_IRQ_2_IRQn

◆ VSF_HW_TIMER3_IRQN

#define VSF_HW_TIMER3_IRQN TIMER_IRQ_3_IRQn

◆ VSF_HW_TIMER0_IRQHandler

#define VSF_HW_TIMER0_IRQHandler TIMER_IRQ_0_IRQHandler

◆ VSF_HW_TIMER1_IRQHandler

#define VSF_HW_TIMER1_IRQHandler TIMER_IRQ_1_IRQHandler

◆ VSF_HW_TIMER2_IRQHandler

#define VSF_HW_TIMER2_IRQHandler TIMER_IRQ_2_IRQHandler

◆ VSF_HW_TIMER3_IRQHandler

#define VSF_HW_TIMER3_IRQHandler TIMER_IRQ_3_IRQHandler

◆ VSF_HW_TIMER_CHANNEL_COUNT

#define VSF_HW_TIMER_CHANNEL_COUNT 2

◆ VSF_HW_SPI_COUNT

#define VSF_HW_SPI_COUNT 2

◆ VSF_HW_SPI0_IRQN

#define VSF_HW_SPI0_IRQN SPI0_IRQ_IRQn

◆ VSF_HW_SPI0_IRQHandler

#define VSF_HW_SPI0_IRQHandler SPI0_IRQHandler

◆ VSF_HW_SPI0_REG

#define VSF_HW_SPI0_REG SPI0_BASE

◆ VSF_HW_SPI0_RST_BIT

#define VSF_HW_SPI0_RST_BIT (1u << RESET_SPI0)

◆ VSF_HW_SPI1_IRQN

#define VSF_HW_SPI1_IRQN SPI1_IRQ_IRQn

◆ VSF_HW_SPI1_IRQHandler

#define VSF_HW_SPI1_IRQHandler SPI1_IRQHandler

◆ VSF_HW_SPI1_REG

#define VSF_HW_SPI1_REG SPI1_BASE

◆ VSF_HW_SPI1_RST_BIT

#define VSF_HW_SPI1_RST_BIT (1u << RESET_SPI1)

◆ VSF_HW_RNG_COUNT

#define VSF_HW_RNG_COUNT 1

◆ VSF_HW_RNG_BITLEN

#define VSF_HW_RNG_BITLEN 32

◆ VSF_HW_DMA_COUNT

#define VSF_HW_DMA_COUNT 1

◆ VSF_HW_DMA_MASK

#define VSF_HW_DMA_MASK 0x1

◆ VSF_HW_DMA_CHANNEL_NUM

#define VSF_HW_DMA_CHANNEL_NUM 12

◆ VSF_HW_DMA0_REG

#define VSF_HW_DMA0_REG DMA_BASE

◆ VSF_HW_DMA0_RST_BIT

#define VSF_HW_DMA0_RST_BIT (1u << RESET_DMA)

◆ VSF_HW_DMA0_IRQN

#define VSF_HW_DMA0_IRQN DMA_IRQ_0_IRQn

◆ VSF_HW_DMA0_IRQN_0

#define VSF_HW_DMA0_IRQN_0 VSF_HW_DMA0_IRQN

◆ VSF_HW_DMA0_IRQN_1

#define VSF_HW_DMA0_IRQN_1 DMA_IRQ_1_IRQn

◆ VSF_HW_DMA0_IRQHandler

#define VSF_HW_DMA0_IRQHandler VSF_HW_DMA0_IRQ_0_Handler

◆ VSF_HW_DMA0_IRQ_0_Handler

#define VSF_HW_DMA0_IRQ_0_Handler DMA_IRQ_0_Handler

◆ VSF_HW_DMA0_IRQ_1_Handler

#define VSF_HW_DMA0_IRQ_1_Handler ( void ) DMA_IRQ_1_Handler

◆ VSF_HW_DMA0_IRQ_Handler_COUNT

#define VSF_HW_DMA0_IRQ_Handler_COUNT 2

Macros