Go to the source code of this file.
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| enum | vsf_i2c_mode_t {
VSF_I2C_MODE_MASTER = (0x1ul << 28)
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VSF_I2C_MODE_SLAVE = (0x0ul << 28)
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VSF_I2C_SPEED_STANDARD_MODE = (0x0ul << 29)
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VSF_I2C_SPEED_FAST_MODE = (0x1ul << 29)
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VSF_I2C_SPEED_FAST_MODE_PLUS = (0x2ul << 29)
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VSF_I2C_SPEED_HIGH_SPEED_MODE = (0x3ul << 29)
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VSF_I2C_ADDR_7_BITS = (0x0ul << 31)
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VSF_I2C_ADDR_10_BITS = (0x1ul << 31)
} |
| |
| enum | vsf_i2c_cmd_t {
VSF_I2C_CMD_WRITE = (0x00ul << 0)
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VSF_I2C_CMD_READ = (0x01ul << 0)
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VSF_I2C_CMD_START = (0x00ul << 28)
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VSF_I2C_CMD_NO_START = (0x01ul << 28)
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VSF_I2C_CMD_STOP = (0x00ul << 29)
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VSF_I2C_CMD_RESTART = (0x01ul << 30)
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VSF_I2C_CMD_NO_STOP_RESTART = (0x01ul << 30)
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VSF_I2C_CMD_7_BITS = (0x00ul << 31)
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VSF_I2C_CMD_10_BITS = (0x01ul << 31)
} |
| |
| enum | vsf_i2c_irq_mask_t {
VSF_I2C_IRQ_MASK_MASTER_TX = (0x1ul << 0)
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VSF_I2C_IRQ_MASK_MASTER_RX = (0x1ul << 1)
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VSF_I2C_IRQ_MASK_MASTER_TRANSFER_COMPLETE = (0x1ul << 2)
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VSF_I2C_IRQ_MASK_MASTER_ARBITRATION_LOST = (0x1ul << 3)
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VSF_I2C_IRQ_MASK_MASTER_ADDRESS_NACK = (0x1ul << 4)
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VSF_I2C_IRQ_MASK_MASTER_TX_NACK_DETECT = (0x1ul << 5)
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VSF_I2C_IRQ_MASK_MASTER_START_OR_RESTART_DETECT = (0x1ul << 6)
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VSF_I2C_IRQ_MASK_MASTER_STOP_DETECT = (0x1ul << 7)
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VSF_I2C_IRQ_MASK_SLAVE_START_OR_RESTART_DETECT = (0x1ul << 8)
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VSF_I2C_IRQ_MASK_SLAVE_STOP_DETECT = (0x1ul << 9)
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VSF_I2C_IRQ_MASK_SLAVE_TX = (0x1ul << 10)
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VSF_I2C_IRQ_MASK_SLAVE_RX = (0x1ul << 11)
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VSF_I2C_IRQ_MASK_SLAVE_TRANSFER_COMPLETE = (0x1ul << 12)
} |
| |
| enum | vsf_i2c_ctrl_t { __VSF_I2C_CTRL_DUMMP = 0
} |
| |
◆ __HAL_DRIVER_
| #define __HAL_DRIVER_ ${SERIES/I2C_IP}_I2C_H__ |
◆ VSF_
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_MODE
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_MODE ENABLED |
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_STATUS
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_STATUS ENABLED |
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_IRQ_MASK
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_IRQ_MASK ENABLED |
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_CMD
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_CMD ENABLED |
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_CTRL
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_CTRL ENABLED |
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_CFG
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_CFG ENABLED |
◆ VSF_I2C_CFG_REIMPLEMENT_TYPE_CAPABILITY
| #define VSF_I2C_CFG_REIMPLEMENT_TYPE_CAPABILITY ENABLED |
◆ vsf_i2c_mode_t
◆ vsf_i2c_cmd_t
◆ vsf_i2c_irq_mask_t
◆ vsf_i2c_status_t
◆ vsf_i2c_ctrl_t
◆ vsf_i2c_t
◆ vsf_i2c_isr_handler_t
◆ vsf_i2c_isr_t
◆ vsf_i2c_cfg_t
◆ vsf_i2c_capability_t
◆ vsf_i2c_mode_t
| Enumerator |
|---|
| VSF_I2C_MODE_MASTER | |
| VSF_I2C_MODE_SLAVE | |
| VSF_I2C_SPEED_STANDARD_MODE | |
| VSF_I2C_SPEED_FAST_MODE | |
| VSF_I2C_SPEED_FAST_MODE_PLUS | |
| VSF_I2C_SPEED_HIGH_SPEED_MODE | |
| VSF_I2C_ADDR_7_BITS | |
| VSF_I2C_ADDR_10_BITS | |
◆ vsf_i2c_cmd_t
| Enumerator |
|---|
| VSF_I2C_CMD_WRITE | |
| VSF_I2C_CMD_READ | |
| VSF_I2C_CMD_START | |
| VSF_I2C_CMD_NO_START | |
| VSF_I2C_CMD_STOP | |
| VSF_I2C_CMD_RESTART | |
| VSF_I2C_CMD_NO_STOP_RESTART | |
| VSF_I2C_CMD_7_BITS | |
| VSF_I2C_CMD_10_BITS | |
◆ vsf_i2c_irq_mask_t
| Enumerator |
|---|
| VSF_I2C_IRQ_MASK_MASTER_TX | |
| VSF_I2C_IRQ_MASK_MASTER_RX | |
| VSF_I2C_IRQ_MASK_MASTER_TRANSFER_COMPLETE | |
| VSF_I2C_IRQ_MASK_MASTER_ARBITRATION_LOST | |
| VSF_I2C_IRQ_MASK_MASTER_ADDRESS_NACK | |
| VSF_I2C_IRQ_MASK_MASTER_TX_NACK_DETECT | |
| VSF_I2C_IRQ_MASK_MASTER_START_OR_RESTART_DETECT | |
| VSF_I2C_IRQ_MASK_MASTER_STOP_DETECT | |
| VSF_I2C_IRQ_MASK_SLAVE_START_OR_RESTART_DETECT | |
| VSF_I2C_IRQ_MASK_SLAVE_STOP_DETECT | |
| VSF_I2C_IRQ_MASK_SLAVE_TX | |
| VSF_I2C_IRQ_MASK_SLAVE_RX | |
| VSF_I2C_IRQ_MASK_SLAVE_TRANSFER_COMPLETE | |
◆ vsf_i2c_ctrl_t
| Enumerator |
|---|
| __VSF_I2C_CTRL_DUMMP | |
◆ reg
◆ isr