dwcotg_core_global_regs_t Struct Reference

#include <dwcotg_regs.h>

Data Fields
volatile uint32_t	gotgctl
volatile uint32_t	gotgint
volatile uint32_t	gahbcfg
volatile uint32_t	gusbcfg
volatile uint32_t	grstctl
volatile uint32_t	gintsts
volatile uint32_t	gintmsk
volatile uint32_t	grxstsr
volatile uint32_t	grxstsp
volatile uint32_t	grxfsiz
volatile uint32_t	gnptxfsiz
volatile uint32_t	gnptxsts
volatile uint32_t	gi2cctl
volatile uint32_t	gpvndctl
volatile uint32_t	gccfg
volatile uint32_t	guid
volatile uint32_t	gsnpsid
volatile uint32_t	ghwcfg1
volatile uint32_t	ghwcfg2
volatile uint32_t	ghwcfg3
volatile uint32_t	ghwcfg4
volatile uint32_t	glpmcfg
volatile uint32_t	gpwrdn
volatile uint32_t	gdfifocfg
volatile uint32_t	adpctl
volatile uint32_t	reserved39 [39]
volatile uint32_t	hptxfsiz
volatile uint32_t	dtxfsiz [15]

Detailed Description

DWC_otg Core registers . The dwcotg_core_global_regs structure defines the size and relative field offsets for the Core Global registers.

Field Documentation

gotgctl

volatile uint32_t dwcotg_core_global_regs_t::gotgctl

OTG Control and Status Register. Offset: 000h

gotgint

volatile uint32_t dwcotg_core_global_regs_t::gotgint

OTG Interrupt Register. Offset: 004h

gahbcfg

volatile uint32_t dwcotg_core_global_regs_t::gahbcfg

Core AHB Configuration Register. Offset: 008h

gusbcfg

volatile uint32_t dwcotg_core_global_regs_t::gusbcfg

Core USB Configuration Register. Offset: 00Ch

grstctl

volatile uint32_t dwcotg_core_global_regs_t::grstctl

Core Reset Register. Offset: 010h

gintsts

volatile uint32_t dwcotg_core_global_regs_t::gintsts

Core Interrupt Register. Offset: 014h

gintmsk

volatile uint32_t dwcotg_core_global_regs_t::gintmsk

Core Interrupt Mask Register. Offset: 018h

grxstsr

volatile uint32_t dwcotg_core_global_regs_t::grxstsr

Receive Status Queue Read Register (Read Only). Offset: 01Ch

grxstsp

volatile uint32_t dwcotg_core_global_regs_t::grxstsp

Receive Status Queue Read & POP Register (Read Only). Offset: 020h

grxfsiz

volatile uint32_t dwcotg_core_global_regs_t::grxfsiz

Receive FIFO Size Register. Offset: 024h

gnptxfsiz

volatile uint32_t dwcotg_core_global_regs_t::gnptxfsiz

Non Periodic Transmit FIFO Size Register. Offset: 028h

gnptxsts

volatile uint32_t dwcotg_core_global_regs_t::gnptxsts

Non Periodic Transmit FIFO/Queue Status Register (Read Only). Offset: 02Ch

gi2cctl

volatile uint32_t dwcotg_core_global_regs_t::gi2cctl

I2C Access Register. Offset: 030h

gpvndctl

volatile uint32_t dwcotg_core_global_regs_t::gpvndctl

PHY Vendor Control Register. Offset: 034h

gccfg

volatile uint32_t dwcotg_core_global_regs_t::gccfg

General Purpose Input/Output Register. Offset: 038h

guid

volatile uint32_t dwcotg_core_global_regs_t::guid

User ID Register. Offset: 03Ch

gsnpsid

volatile uint32_t dwcotg_core_global_regs_t::gsnpsid

Synopsys ID Register (Read Only). Offset: 040h

ghwcfg1

volatile uint32_t dwcotg_core_global_regs_t::ghwcfg1

User HW Config1 Register (Read Only). Offset: 044h

ghwcfg2

volatile uint32_t dwcotg_core_global_regs_t::ghwcfg2

User HW Config2 Register (Read Only). Offset: 048h

ghwcfg3

volatile uint32_t dwcotg_core_global_regs_t::ghwcfg3

User HW Config3 Register (Read Only). Offset: 04Ch

ghwcfg4

volatile uint32_t dwcotg_core_global_regs_t::ghwcfg4

User HW Config4 Register (Read Only). Offset: 050h

glpmcfg

volatile uint32_t dwcotg_core_global_regs_t::glpmcfg

Core LPM Configuration register Offset: 054h

gpwrdn

volatile uint32_t dwcotg_core_global_regs_t::gpwrdn

Global PowerDn Register Offset: 058h

gdfifocfg

volatile uint32_t dwcotg_core_global_regs_t::gdfifocfg

Global DFIFO SW Config Register Offset: 05Ch

adpctl

volatile uint32_t dwcotg_core_global_regs_t::adpctl

ADP Control Register Offset: 060h

reserved39

volatile uint32_t dwcotg_core_global_regs_t::reserved39[39]

Reserved Offset: 064h-0FFh

hptxfsiz

volatile uint32_t dwcotg_core_global_regs_t::hptxfsiz

Host Periodic Transmit FIFO Size Register. Offset: 100h

dtxfsiz

volatile uint32_t dwcotg_core_global_regs_t::dtxfsiz[15]

Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register. Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).