intc_reg_t Struct Reference

#include <i_reg_inc.h>

Data Fields
reg32_t	VECTOR
	interrupt vector register
union {
reg32_t   BASE_ADDR
	vector table base address More...
reg32_t   VTOR
	alias as NVIC.VTOR More...
};
REG_RSVD_U32 DEF_REG reg32_t	NMI_SRC_TYPE: 2
	< NMI interrupt control
reg32_t	: 30
union {
reg32_t   PEND [2]
	Interrupt Pending Register 0/1. More...
reg32_t   PENDING [2]
	Alias as interrupt Pending Status Register. More...
};
union {
reg32_t   EN [2]
	Interrupt Enable Register 0/1. More...
reg32_t   SRC_MASK [2]
	Interrupt Source Mask Register 0/1 More...
};
union {
reg32_t   MASK [2]
	Interrupt Mask Register 0/1. More...
reg32_t   DISABLE [2]
	Alias as interrupt Disable register. More...
};
REG_RSVD_U32 REG_RSVD_U32 reg32_t	RESP [2]
	Interrupt Response Register 0/1.
union {
reg32_t   FF [2]
	Interrupt Fast Forcing Register 0/1. More...
reg32_t   STIR [2]
	Alias as NVIC.STIR Software Trigger Interrupt Register. More...
};
union {
struct {
DEF_REG reg32_t   IRQ00_PRIO: 2
	< Interrupt Source Priority Register 0 More...
reg32_t   IRQ01_PRIO: 2
reg32_t   IRQ02_PRIO: 2
reg32_t   IRQ03_PRIO: 2
reg32_t   IRQ04_PRIO: 2
reg32_t   IRQ05_PRIO: 2
reg32_t   IRQ06_PRIO: 2
reg32_t   IRQ07_PRIO: 2
reg32_t   IRQ08_PRIO: 2
reg32_t   IRQ09_PRIO: 2
reg32_t   IRQ10_PRIO: 2
reg32_t   IRQ11_PRIO: 2
reg32_t   IRQ12_PRIO: 2
reg32_t   IRQ13_PRIO: 2
reg32_t   IRQ14_PRIO: 2
reg32_t   IRQ15_PRIO: 2
DEF_REG reg32_t   IRQ16_PRIO: 2
	< Interrupt Source Priority Register 1 More...
reg32_t   IRQ17_PRIO: 2
reg32_t   IRQ18_PRIO: 2
reg32_t   IRQ19_PRIO: 2
reg32_t   IRQ20_PRIO: 2
reg32_t   IRQ21_PRIO: 2
reg32_t   IRQ22_PRIO: 2
reg32_t   IRQ23_PRIO: 2
reg32_t   IRQ24_PRIO: 2
reg32_t   IRQ25_PRIO: 2
reg32_t   IRQ26_PRIO: 2
reg32_t   IRQ27_PRIO: 2
reg32_t   IRQ28_PRIO: 2
reg32_t   IRQ29_PRIO: 2
reg32_t   IRQ30_PRIO: 2
reg32_t   IRQ31_PRIO: 2
DEF_REG reg32_t   IRQ32_PRIO: 2
	< Interrupt Source Priority Register 2 More...
reg32_t   IRQ33_PRIO: 2
reg32_t   IRQ34_PRIO: 2
reg32_t   IRQ35_PRIO: 2
reg32_t   IRQ36_PRIO: 2
reg32_t   IRQ37_PRIO: 2
reg32_t   IRQ38_PRIO: 2
reg32_t   IRQ39_PRIO: 2
reg32_t   IRQ40_PRIO: 2
reg32_t   IRQ41_PRIO: 2
reg32_t   IRQ42_PRIO: 2
reg32_t   IRQ43_PRIO: 2
reg32_t   IRQ44_PRIO: 2
reg32_t   IRQ45_PRIO: 2
reg32_t   IRQ46_PRIO: 2
reg32_t   IRQ47_PRIO: 2
DEF_REG reg32_t   IRQ48_PRIO: 2
	< Interrupt Source Priority Register 3 More...
reg32_t   IRQ49_PRIO: 2
reg32_t   IRQ50_PRIO: 2
reg32_t   IRQ51_PRIO: 2
reg32_t   IRQ52_PRIO: 2
reg32_t   IRQ53_PRIO: 2
reg32_t   IRQ54_PRIO: 2
reg32_t   IRQ55_PRIO: 2
reg32_t   IRQ56_PRIO: 2
reg32_t   IRQ57_PRIO: 2
reg32_t   IRQ58_PRIO: 2
reg32_t   IRQ59_PRIO: 2
reg32_t   IRQ60_PRIO: 2
reg32_t   IRQ61_PRIO: 2
reg32_t   IRQ62_PRIO: 2
reg32_t   IRQ63_PRIO: 2
}
reg32_t   PRIO [4]
};

Field Documentation

VECTOR

reg32_t intc_reg_t::VECTOR

interrupt vector register

BASE_ADDR

reg32_t intc_reg_t::BASE_ADDR

vector table base address

VTOR

reg32_t intc_reg_t::VTOR

alias as NVIC.VTOR

[union]

union { ... } intc_reg_t

NMI_SRC_TYPE

REG_RSVD_U32 DEF_REG reg32_t intc_reg_t::NMI_SRC_TYPE

< NMI interrupt control

External NMI Interrupt Source Type

__pad0__

reg32_t intc_reg_t::__pad0__

PEND

reg32_t intc_reg_t::PEND[2]

Interrupt Pending Register 0/1.

PENDING

reg32_t intc_reg_t::PENDING[2]

Alias as interrupt Pending Status Register.

[union]

union { ... } intc_reg_t

EN

reg32_t intc_reg_t::EN[2]

Interrupt Enable Register 0/1.

SRC_MASK

reg32_t intc_reg_t::SRC_MASK[2]

Interrupt Source Mask Register 0/1

[union]

REG_RSVD_U32 REG_RSVD_U32 union { ... } intc_reg_t

MASK

reg32_t intc_reg_t::MASK[2]

Interrupt Mask Register 0/1.

DISABLE

reg32_t intc_reg_t::DISABLE[2]

Alias as interrupt Disable register.

[union]

REG_RSVD_U32 REG_RSVD_U32 union { ... } intc_reg_t

RESP

REG_RSVD_U32 REG_RSVD_U32 reg32_t intc_reg_t::RESP[2]

Interrupt Response Register 0/1.

FF

reg32_t intc_reg_t::FF[2]

Interrupt Fast Forcing Register 0/1.

STIR

reg32_t intc_reg_t::STIR[2]

Alias as NVIC.STIR Software Trigger Interrupt Register.

[union]

REG_RSVD_U32 REG_RSVD_U32 union { ... } intc_reg_t

IRQ00_PRIO

DEF_REG reg32_t intc_reg_t::IRQ00_PRIO

< Interrupt Source Priority Register 0

IRQ01_PRIO

reg32_t intc_reg_t::IRQ01_PRIO

IRQ02_PRIO

reg32_t intc_reg_t::IRQ02_PRIO

IRQ03_PRIO

reg32_t intc_reg_t::IRQ03_PRIO

IRQ04_PRIO

reg32_t intc_reg_t::IRQ04_PRIO

IRQ05_PRIO

reg32_t intc_reg_t::IRQ05_PRIO

IRQ06_PRIO

reg32_t intc_reg_t::IRQ06_PRIO

IRQ07_PRIO

reg32_t intc_reg_t::IRQ07_PRIO

IRQ08_PRIO

reg32_t intc_reg_t::IRQ08_PRIO

IRQ09_PRIO

reg32_t intc_reg_t::IRQ09_PRIO

IRQ10_PRIO

reg32_t intc_reg_t::IRQ10_PRIO

IRQ11_PRIO

reg32_t intc_reg_t::IRQ11_PRIO

IRQ12_PRIO

reg32_t intc_reg_t::IRQ12_PRIO

IRQ13_PRIO

reg32_t intc_reg_t::IRQ13_PRIO

IRQ14_PRIO

reg32_t intc_reg_t::IRQ14_PRIO

IRQ15_PRIO

reg32_t intc_reg_t::IRQ15_PRIO

IRQ16_PRIO

DEF_REG reg32_t intc_reg_t::IRQ16_PRIO

< Interrupt Source Priority Register 1

IRQ17_PRIO

reg32_t intc_reg_t::IRQ17_PRIO

IRQ18_PRIO

reg32_t intc_reg_t::IRQ18_PRIO

IRQ19_PRIO

reg32_t intc_reg_t::IRQ19_PRIO

IRQ20_PRIO

reg32_t intc_reg_t::IRQ20_PRIO

IRQ21_PRIO

reg32_t intc_reg_t::IRQ21_PRIO

IRQ22_PRIO

reg32_t intc_reg_t::IRQ22_PRIO

IRQ23_PRIO

reg32_t intc_reg_t::IRQ23_PRIO

IRQ24_PRIO

reg32_t intc_reg_t::IRQ24_PRIO

IRQ25_PRIO

reg32_t intc_reg_t::IRQ25_PRIO

IRQ26_PRIO

reg32_t intc_reg_t::IRQ26_PRIO

IRQ27_PRIO

reg32_t intc_reg_t::IRQ27_PRIO

IRQ28_PRIO

reg32_t intc_reg_t::IRQ28_PRIO

IRQ29_PRIO

reg32_t intc_reg_t::IRQ29_PRIO

IRQ30_PRIO

reg32_t intc_reg_t::IRQ30_PRIO

IRQ31_PRIO

reg32_t intc_reg_t::IRQ31_PRIO

IRQ32_PRIO

DEF_REG reg32_t intc_reg_t::IRQ32_PRIO

< Interrupt Source Priority Register 2

IRQ33_PRIO

reg32_t intc_reg_t::IRQ33_PRIO

IRQ34_PRIO

reg32_t intc_reg_t::IRQ34_PRIO

IRQ35_PRIO

reg32_t intc_reg_t::IRQ35_PRIO

IRQ36_PRIO

reg32_t intc_reg_t::IRQ36_PRIO

IRQ37_PRIO

reg32_t intc_reg_t::IRQ37_PRIO

IRQ38_PRIO

reg32_t intc_reg_t::IRQ38_PRIO

IRQ39_PRIO

reg32_t intc_reg_t::IRQ39_PRIO

IRQ40_PRIO

reg32_t intc_reg_t::IRQ40_PRIO

IRQ41_PRIO

reg32_t intc_reg_t::IRQ41_PRIO

IRQ42_PRIO

reg32_t intc_reg_t::IRQ42_PRIO

IRQ43_PRIO

reg32_t intc_reg_t::IRQ43_PRIO

IRQ44_PRIO

reg32_t intc_reg_t::IRQ44_PRIO

IRQ45_PRIO

reg32_t intc_reg_t::IRQ45_PRIO

IRQ46_PRIO

reg32_t intc_reg_t::IRQ46_PRIO

IRQ47_PRIO

reg32_t intc_reg_t::IRQ47_PRIO

IRQ48_PRIO

DEF_REG reg32_t intc_reg_t::IRQ48_PRIO

< Interrupt Source Priority Register 3

IRQ49_PRIO

reg32_t intc_reg_t::IRQ49_PRIO

IRQ50_PRIO

reg32_t intc_reg_t::IRQ50_PRIO

IRQ51_PRIO

reg32_t intc_reg_t::IRQ51_PRIO

IRQ52_PRIO

reg32_t intc_reg_t::IRQ52_PRIO

IRQ53_PRIO

reg32_t intc_reg_t::IRQ53_PRIO

IRQ54_PRIO

reg32_t intc_reg_t::IRQ54_PRIO

IRQ55_PRIO

reg32_t intc_reg_t::IRQ55_PRIO

IRQ56_PRIO

reg32_t intc_reg_t::IRQ56_PRIO

IRQ57_PRIO

reg32_t intc_reg_t::IRQ57_PRIO

IRQ58_PRIO

reg32_t intc_reg_t::IRQ58_PRIO

IRQ59_PRIO

reg32_t intc_reg_t::IRQ59_PRIO

IRQ60_PRIO

reg32_t intc_reg_t::IRQ60_PRIO

IRQ61_PRIO

reg32_t intc_reg_t::IRQ61_PRIO

IRQ62_PRIO

reg32_t intc_reg_t::IRQ62_PRIO

IRQ63_PRIO

reg32_t intc_reg_t::IRQ63_PRIO

PRIO

reg32_t intc_reg_t::PRIO[4]

[union]

REG_RSVD_U32 REG_RSVD_U32 union { ... } intc_reg_t