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vsf_template_spi.h
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1/*****************************************************************************
2 * Copyright(C)2009-2022 by VSF Team *
3 * *
4 * Licensed under the Apache License, Version 2.0 (the "License"); *
5 * you may not use this file except in compliance with the License. *
6 * You may obtain a copy of the License at *
7 * *
8 * http://www.apache.org/licenses/LICENSE-2.0 *
9 * *
10 * Unless required by applicable law or agreed to in writing, software *
11 * distributed under the License is distributed on an "AS IS" BASIS, *
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
13 * See the License for the specific language governing permissions and *
14 * limitations under the License. *
15 * *
16 ****************************************************************************/
17
18#ifndef __VSF_TEMPLATE_SPI_H__
19#define __VSF_TEMPLATE_SPI_H__
20
21/*============================ INCLUDES ======================================*/
22
23#include "./vsf_template_hal_driver.h"
24#include "hal/arch/vsf_arch.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/*============================ MACROS ========================================*/
31
39#ifndef VSF_SPI_CFG_MULTI_CLASS
40# define VSF_SPI_CFG_MULTI_CLASS ENABLED
41#endif
42
50#if defined(VSF_HW_SPI_COUNT) && !defined(VSF_HW_SPI_MASK)
51# define VSF_HW_SPI_MASK VSF_HAL_COUNT_TO_MASK(VSF_HW_SPI_COUNT)
52#endif
53
61#if defined(VSF_HW_SPI_MASK) && !defined(VSF_HW_SPI_COUNT)
62# define VSF_HW_SPI_COUNT VSF_HAL_MASK_TO_COUNT(VSF_HW_SPI_MASK)
63#endif
64
73#ifndef VSF_SPI_CFG_PREFIX
74# if VSF_SPI_CFG_MULTI_CLASS == ENABLED
75# define VSF_SPI_CFG_PREFIX vsf
76# elif defined(VSF_HW_SPI_COUNT) && (VSF_HW_SPI_COUNT != 0)
77# define VSF_SPI_CFG_PREFIX vsf_hw
78# else
79# define VSF_SPI_CFG_PREFIX vsf
80# endif
81#endif
82
91#ifndef VSF_SPI_CFG_FUNCTION_RENAME
92# define VSF_SPI_CFG_FUNCTION_RENAME ENABLED
93#endif
94
103#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE
104# define VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE DISABLED
105#endif
106
116#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK
117# define VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK DISABLED
118#endif
119
129#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS
130# define VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS DISABLED
131#endif
132
145#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG
146# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG DISABLED
147#endif
148
158#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL
159# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL DISABLED
160#endif
161
172#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY
173# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY DISABLED
174#endif
175
185#ifndef VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS
186# define VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS DISABLED
187#endif
188
198#ifndef VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE
199# define VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE DISABLED
200#endif
201
211#ifndef VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES
212# define VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES DISABLED
213#endif
214
224#ifndef VSF_SPI_CFG_INHERIT_HAL_CAPABILITY
225# define VSF_SPI_CFG_INHERIT_HAL_CAPABILITY ENABLED
226#endif
227
228/*============================ MACROFIED FUNCTIONS ===========================*/
229
238#define VSF_SPI_APIS(__prefix_name) \
239 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, init, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_cfg_t *cfg_ptr) \
240 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, fini, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
241 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, get_configuration, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_cfg_t *cfg_ptr) \
242 __VSF_HAL_TEMPLATE_API(__prefix_name, fsm_rt_t, spi, enable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
243 __VSF_HAL_TEMPLATE_API(__prefix_name, fsm_rt_t, spi, disable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
244 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, irq_enable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
245 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, irq_disable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
246 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_irq_mask_t, spi, irq_clear, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
247 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_status_t, spi, status, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
248 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_capability_t, spi, capability, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
249 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cs_active, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast8_t index) \
250 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cs_inactive, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast8_t index) \
251 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, fifo_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, void *out_buffer_ptr, uint_fast32_t *out_offset_ptr, void *in_buffer_ptr, uint_fast32_t *in_offset_ptr, uint_fast32_t cnt) \
252 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, request_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, void *out_buffer_ptr, void *in_buffer_ptr, uint_fast32_t count) \
253 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cancel_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
254 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, get_transferred_count, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast32_t * sent_count, uint_fast32_t *received_count) \
255 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, ctrl, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_ctrl_t ctrl, void* param)
256
257
258/*============================ TYPES =========================================*/
259
260#if VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE == DISABLED
296typedef enum vsf_spi_mode_t {
297 // Direction control (bit 0)
298 VSF_SPI_MASTER = 0x00ul << 0,
299 VSF_SPI_SLAVE = 0x01ul << 0,
300
301 // Bit order control (bit 1)
302 VSF_SPI_MSB_FIRST = 0x00ul << 1,
303 VSF_SPI_LSB_FIRST = 0x01ul << 1,
304
305 // Clock polarity control (bit 2)
306 VSF_SPI_CPOL_LOW = 0x00ul << 2,
307 VSF_SPI_CPOL_HIGH = 0x01ul << 2,
308
309 // Clock phase control (bit 3)
310 VSF_SPI_CPHA_LOW = 0x00ul << 3,
311 VSF_SPI_CPHA_HIGH = 0x01ul << 3,
312
313 VSF_SPI_MODE_0 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_LOW,
314 VSF_SPI_MODE_1 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_HIGH,
315 VSF_SPI_MODE_2 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_LOW,
316 VSF_SPI_MODE_3 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_HIGH,
317
318 // Chip select control (bit 4)
319 // \~english Software controlled chip select. The user must manually call vsf_spi_cs_active() and vsf_spi_cs_inactive() to control the CS line.
320 // \~chinese 软件控制片选。用户必须手动调用 vsf_spi_cs_active() 和 vsf_spi_cs_inactive() 来控制片选线。
321 VSF_SPI_CS_SOFTWARE_MODE = 0x00ul << 4,
322 // \~english Hardware controlled chip select. The hardware automatically controls the CS line specified by `auto_cs_index` during a transfer.
323 // \~chinese 硬件控制片选。硬件在传输期间自动控制由 `auto_cs_index` 指定的片选线。
324 VSF_SPI_CS_HARDWARE_MODE = 0x01ul << 4,
325
326 // Data size control (bits 8-15)
327 // \~english Buffer size requirements: 4-8 bits = 1 byte, 9-16 bits = 2 bytes, 17-32 bits = 4 bytes
328 // \~chinese 缓冲区大小要求：4-8 位 = 1 字节，9-16 位 = 2 字节，17-32 位 = 4 字节
329 VSF_SPI_DATASIZE_8 = 0x00ul << 8,
330 VSF_SPI_DATASIZE_16 = 0x01ul << 8,
331 VSF_SPI_DATASIZE_32 = 0x02ul << 8,
332 /*
337 VSF_SPI_DATASIZE_VALUE_OFFSET = 1,
338 VSF_SPI_DATASIZE_BIT_OFFSET = 8,
339 VSF_SPI_DATASIZE_4 = ( 4ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 4-bit data (1-byte buffer) \~chinese 4 位数据（1 字节缓冲区）
340 VSF_SPI_DATASIZE_5 = ( 5ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 5-bit data (1-byte buffer) \~chinese 5 位数据（1 字节缓冲区）
341 VSF_SPI_DATASIZE_6 = ( 6ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 6-bit data (1-byte buffer) \~chinese 6 位数据（1 字节缓冲区）
342 VSF_SPI_DATASIZE_7 = ( 7ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 7-bit data (1-byte buffer) \~chinese 7 位数据（1 字节缓冲区）
343 VSF_SPI_DATASIZE_8 = ( 8ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 8-bit data (1-byte buffer) \~chinese 8 位数据（1 字节缓冲区）
344 VSF_SPI_DATASIZE_9 = ( 9ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 9-bit data (2-byte buffer) \~chinese 9 位数据（2 字节缓冲区）
345 VSF_SPI_DATASIZE_10 = (10ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 10-bit data (2-byte buffer) \~chinese 10 位数据（2 字节缓冲区）
346 VSF_SPI_DATASIZE_11 = (11ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 11-bit data (2-byte buffer) \~chinese 11 位数据（2 字节缓冲区）
347 VSF_SPI_DATASIZE_12 = (12ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 12-bit data (2-byte buffer) \~chinese 12 位数据（2 字节缓冲区）
348 VSF_SPI_DATASIZE_13 = (13ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 13-bit data (2-byte buffer) \~chinese 13 位数据（2 字节缓冲区）
349 VSF_SPI_DATASIZE_14 = (14ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 14-bit data (2-byte buffer) \~chinese 14 位数据（2 字节缓冲区）
350 VSF_SPI_DATASIZE_15 = (15ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 15-bit data (2-byte buffer) \~chinese 15 位数据（2 字节缓冲区）
351 VSF_SPI_DATASIZE_16 = (16ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 16-bit data (2-byte buffer) \~chinese 16 位数据（2 字节缓冲区）
352 VSF_SPI_DATASIZE_17 = (17ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 17-bit data (4-byte buffer) \~chinese 17 位数据（4 字节缓冲区）
353 VSF_SPI_DATASIZE_18 = (18ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 18-bit data (4-byte buffer) \~chinese 18 位数据（4 字节缓冲区）
354 VSF_SPI_DATASIZE_19 = (19ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 19-bit data (4-byte buffer) \~chinese 19 位数据（4 字节缓冲区）
355 VSF_SPI_DATASIZE_20 = (20ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 20-bit data (4-byte buffer) \~chinese 20 位数据（4 字节缓冲区）
356 VSF_SPI_DATASIZE_21 = (21ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 21-bit data (4-byte buffer) \~chinese 21 位数据（4 字节缓冲区）
357 VSF_SPI_DATASIZE_22 = (22ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 22-bit data (4-byte buffer) \~chinese 22 位数据（4 字节缓冲区）
358 VSF_SPI_DATASIZE_23 = (23ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 23-bit data (4-byte buffer) \~chinese 23 位数据（4 字节缓冲区）
359 VSF_SPI_DATASIZE_24 = (24ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 24-bit data (4-byte buffer) \~chinese 24 位数据（4 字节缓冲区）
360 VSF_SPI_DATASIZE_25 = (25ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 25-bit data (4-byte buffer) \~chinese 25 位数据（4 字节缓冲区）
361 VSF_SPI_DATASIZE_26 = (26ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 26-bit data (4-byte buffer) \~chinese 26 位数据（4 字节缓冲区）
362 VSF_SPI_DATASIZE_27 = (27ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 27-bit data (4-byte buffer) \~chinese 27 位数据（4 字节缓冲区）
363 VSF_SPI_DATASIZE_28 = (28ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 28-bit data (4-byte buffer) \~chinese 28 位数据（4 字节缓冲区）
364 VSF_SPI_DATASIZE_29 = (29ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 29-bit data (4-byte buffer) \~chinese 29 位数据（4 字节缓冲区）
365 VSF_SPI_DATASIZE_30 = (30ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 30-bit data (4-byte buffer) \~chinese 30 位数据（4 字节缓冲区）
366 VSF_SPI_DATASIZE_31 = (31ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 31-bit data (4-byte buffer) \~chinese 31 位数据（4 字节缓冲区）
367 VSF_SPI_DATASIZE_32 = (32ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET, //! \~english 32-bit data (4-byte buffer) \~chinese 32 位数据（4 字节缓冲区）
368 #define VSF_SPI_DATASIZE_BIT_OFFSET VSF_SPI_DATASIZE_BIT_OFFSET
369 #define VSF_SPI_DATASIZE_VALUE_OFFSET VSF_SPI_DATASIZE_VALUE_OFFSET
370 #define VSF_SPI_DATASIZE_4 VSF_SPI_DATASIZE_4
371 #define VSF_SPI_DATASIZE_5 VSF_SPI_DATASIZE_5
372 #define VSF_SPI_DATASIZE_6 VSF_SPI_DATASIZE_6
373 #define VSF_SPI_DATASIZE_7 VSF_SPI_DATASIZE_7
374 #define VSF_SPI_DATASIZE_8 VSF_SPI_DATASIZE_8
375 #define VSF_SPI_DATASIZE_9 VSF_SPI_DATASIZE_9
376 #define VSF_SPI_DATASIZE_10 VSF_SPI_DATASIZE_10
377 #define VSF_SPI_DATASIZE_11 VSF_SPI_DATASIZE_11
378 #define VSF_SPI_DATASIZE_12 VSF_SPI_DATASIZE_12
379 #define VSF_SPI_DATASIZE_13 VSF_SPI_DATASIZE_13
380 #define VSF_SPI_DATASIZE_14 VSF_SPI_DATASIZE_14
381 #define VSF_SPI_DATASIZE_15 VSF_SPI_DATASIZE_15
382 #define VSF_SPI_DATASIZE_16 VSF_SPI_DATASIZE_16
383 #define VSF_SPI_DATASIZE_17 VSF_SPI_DATASIZE_17
384 #define VSF_SPI_DATASIZE_18 VSF_SPI_DATASIZE_18
385 #define VSF_SPI_DATASIZE_19 VSF_SPI_DATASIZE_19
386 #define VSF_SPI_DATASIZE_20 VSF_SPI_DATASIZE_20
387 #define VSF_SPI_DATASIZE_21 VSF_SPI_DATASIZE_21
388 #define VSF_SPI_DATASIZE_22 VSF_SPI_DATASIZE_22
389 #define VSF_SPI_DATASIZE_23 VSF_SPI_DATASIZE_23
390 #define VSF_SPI_DATASIZE_24 VSF_SPI_DATASIZE_24
391 #define VSF_SPI_DATASIZE_25 VSF_SPI_DATASIZE_25
392 #define VSF_SPI_DATASIZE_26 VSF_SPI_DATASIZE_26
393 #define VSF_SPI_DATASIZE_27 VSF_SPI_DATASIZE_27
394 #define VSF_SPI_DATASIZE_28 VSF_SPI_DATASIZE_28
395 #define VSF_SPI_DATASIZE_29 VSF_SPI_DATASIZE_29
396 #define VSF_SPI_DATASIZE_30 VSF_SPI_DATASIZE_30
397 #define VSF_SPI_DATASIZE_31 VSF_SPI_DATASIZE_31
398 #define VSF_SPI_DATASIZE_32 VSF_SPI_DATASIZE_32
399 #define VSF_SPI_DATASIZE_MASK ( VSF_SPI_DATASIZE_4 \
400 | VSF_SPI_DATASIZE_5 \
401 | VSF_SPI_DATASIZE_6 \
402 | VSF_SPI_DATASIZE_7 \
403 | VSF_SPI_DATASIZE_8 \
404 | VSF_SPI_DATASIZE_9 \
405 | VSF_SPI_DATASIZE_10 \
406 | VSF_SPI_DATASIZE_11 \
407 | VSF_SPI_DATASIZE_12 \
408 | VSF_SPI_DATASIZE_13 \
409 | VSF_SPI_DATASIZE_14 \
410 | VSF_SPI_DATASIZE_15 \
411 | VSF_SPI_DATASIZE_16 \
412 | VSF_SPI_DATASIZE_17 \
413 | VSF_SPI_DATASIZE_18 \
414 | VSF_SPI_DATASIZE_19 \
415 | VSF_SPI_DATASIZE_20 \
416 | VSF_SPI_DATASIZE_21 \
417 | VSF_SPI_DATASIZE_22 \
418 | VSF_SPI_DATASIZE_23 \
419 | VSF_SPI_DATASIZE_24 \
420 | VSF_SPI_DATASIZE_25 \
421 | VSF_SPI_DATASIZE_26 \
422 | VSF_SPI_DATASIZE_27 \
423 | VSF_SPI_DATASIZE_28 \
424 | VSF_SPI_DATASIZE_29 \
425 | VSF_SPI_DATASIZE_30 \
426 | VSF_SPI_DATASIZE_31 \
427 | VSF_SPI_DATASIZE_32 )
428 */
429
430 /*
433 VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX = (0x00ul << 16), // MOSI+MISO, full-duplex, standard spi
434 VSF_SPI_DATALINE_2_LINE_RX_ONLY = (0x01ul << 16), // MOSI+MISO, but rx only (MISO)
435 VSF_SPI_DATALINE_2_LINE_TX_ONLY = (0x02ul << 16), // MOSI+MISO, but tx only (MOSI)
436 VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX = (0x03ul << 16), // 1 line (MOSI or MISO), half-duplex
437 VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX = (0x04ul << 16), // 2 line (MOSI+MISO), half-duplex, dual spi
438 VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX = (0x05ul << 16), // 4 line (IO0+IO1+IO2+IO3), half-duplex, quad spi
439 VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX = (0x06ul << 16), // 8 line (IO0+IO1+IO2+IO3+IO4+IO5+IO6+IO7), half-duplex, octal spi
440 VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX = (0x07ul << 16), // 16 line (IO0+IO1+IO2+IO3+IO4+IO5+IO6+IO7+IO8+IO9+IO10+IO11+IO12+IO13+IO14+IO15), half-duplex, hexadeca spi
441 #define VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX
442 #define VSF_SPI_DATALINE_2_LINE_RX_ONLY VSF_SPI_DATALINE_2_LINE_RX_ONLY
443 #define VSF_SPI_DATALINE_2_LINE_TX_ONLY VSF_SPI_DATALINE_2_LINE_TX_ONLY
444 #define VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX
445 #define VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX
446 #define VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX
447 #define VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX
448 #define VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX
449 #define VSF_SPI_DATALINE_MASK ( VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX \
450 | VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX \
451 | VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX \
452 | VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX \
453 | VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX \
454 | VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX)
455 */
456
457 /*
460 VSF_SPI_MOTOROLA_MODE = (0x00ul << 20), //! \~english Motorola SPI: Standard 4-wire SPI protocol \~chinese 摩托罗拉 SPI：标准 4 线 SPI 协议
461 VSF_SPI_TI_MODE = (0x01ul << 20), //! \~english TI SSI: Chip select timing differs from Motorola SPI \~chinese TI SSI：片选时序与摩托罗拉 SPI 不同
462 #define VSF_SPI_MOTOROLA_MODE VSF_SPI_MOTOROLA_MODE
463 #define VSF_SPI_TI_MODE VSF_SPI_TI_MODE
464 #define VSF_SPI_MOTOROLA_TI_MASK (VSF_SPI_MOTOROLA_MODE | VSF_SPI_TI_MODE)
465 */
466
467 /*
469 // @brief Optional CRC calculation support for data integrity
470 // @note Hardware CRC calculation is platform-dependent
471 // @note When enabled, CRC is automatically calculated and verified
473 // @brief 可选的 CRC 数据完整性校验支持
474 // @note 硬件 CRC 计算依赖于平台
475 // @note 当使能时，CRC 将自动计算和验证
476 VSF_SPI_CRC_DISABLED = (0x00ul << 21), //! \~english CRC calculation disabled (no integrity check) \~chinese CRC 计算禁用（无完整性检查）
477 VSF_SPI_CRC_ENABLED = (0x01ul << 21), //! \~english CRC calculation enabled (hardware computes and verifies) \~chinese CRC 计算使能（硬件计算和验证）
478 #define VSF_SPI_CRC_DISABLED VSF_SPI_CRC_DISABLED
479 #define VSF_SPI_CRC_ENABLED VSF_SPI_CRC_ENABLED
480 #define VSF_SPI_CRC_MASK (VSF_SPI_CRC_DISABLED | VSF_SPI_CRC_ENABLED)
481 */
482
483 /*
486 VSF_SPI_CLOCK_PRESCALER_2 = (0x00ul << 22), //! \~english Divide system clock by 2 (highest frequency) \~chinese 系统时钟除以 2（最高频率）
487 VSF_SPI_CLOCK_PRESCALER_4 = (0x01ul << 22), //! \~english Divide system clock by 4 \~chinese 系统时钟除以 4
488 VSF_SPI_CLOCK_PRESCALER_8 = (0x02ul << 22), //! \~english Divide system clock by 8 \~chinese 系统时钟除以 8
489 VSF_SPI_CLOCK_PRESCALER_16 = (0x03ul << 22), //! \~english Divide system clock by 16 \~chinese 系统时钟除以 16
490 VSF_SPI_CLOCK_PRESCALER_32 = (0x04ul << 22), //! \~english Divide system clock by 32 \~chinese 系统时钟除以 32
491 VSF_SPI_CLOCK_PRESCALER_64 = (0x05ul << 22), //! \~english Divide system clock by 64 \~chinese 系统时钟除以 64
492 VSF_SPI_CLOCK_PRESCALER_128 = (0x06ul << 22), //! \~english Divide system clock by 128 \~chinese 系统时钟除以 128
493 VSF_SPI_CLOCK_PRESCALER_256 = (0x07ul << 22), //! \~english Divide system clock by 256 (lowest frequency) \~chinese 系统时钟除以 256（最低频率）
494 #define VSF_SPI_CLOCK_PRESCALER_2 VSF_SPI_CLOCK_PRESCALER_2
495 #define VSF_SPI_CLOCK_PRESCALER_4 VSF_SPI_CLOCK_PRESCALER_4
496 #define VSF_SPI_CLOCK_PRESCALER_8 VSF_SPI_CLOCK_PRESCALER_8
497 #define VSF_SPI_CLOCK_PRESCALER_16 VSF_SPI_CLOCK_PRESCALER_16
498 #define VSF_SPI_CLOCK_PRESCALER_32 VSF_SPI_CLOCK_PRESCALER_32
499 #define VSF_SPI_CLOCK_PRESCALER_64 VSF_SPI_CLOCK_PRESCALER_64
500 #define VSF_SPI_CLOCK_PRESCALER_128 VSF_SPI_CLOCK_PRESCALER_128
501 #define VSF_SPI_CLOCK_PRESCALER_256 VSF_SPI_CLOCK_PRESCALER_256
502 #define VSF_SPI_CLOCK_PRESCALER_MASK ( VSF_SPI_CLOCK_PRESCALER_2 \
503 | VSF_SPI_CLOCK_PRESCALER_4 \
504 | VSF_SPI_CLOCK_PRESCALER_8 \
505 | VSF_SPI_CLOCK_PRESCALER_16 \
506 | VSF_SPI_CLOCK_PRESCALER_32 \
507 | VSF_SPI_CLOCK_PRESCALER_64 \
508 | VSF_SPI_CLOCK_PRESCALER_128 \
509 | VSF_SPI_CLOCK_PRESCALER_256)
510 */
511} vsf_spi_mode_t;
512#endif
513
520enum {
529 VSF_SPI_DIR_MODE_MASK = VSF_SPI_MASTER
530 | VSF_SPI_SLAVE,
531
540 VSF_SPI_BIT_ORDER_MASK = VSF_SPI_MSB_FIRST
541 | VSF_SPI_LSB_FIRST,
542
551 VSF_SPI_MODE_MASK = VSF_SPI_MODE_0
552 | VSF_SPI_MODE_1
553 | VSF_SPI_MODE_2
554 | VSF_SPI_MODE_3,
555
560#ifndef VSF_SPI_CS_MODE_MASK
561 VSF_SPI_CS_MODE_MASK = VSF_SPI_CS_SOFTWARE_MODE
562 | VSF_SPI_CS_HARDWARE_MODE
567#ifdef VSF_SPI_CS_HARDWARE_INPUT_MODE
568 | VSF_SPI_CS_HARDWARE_INPUT_MODE
569#endif
570 ,
571#endif
572
577#ifndef VSF_SPI_DATASIZE_MASK
578 VSF_SPI_DATASIZE_MASK = VSF_SPI_DATASIZE_8
579 | VSF_SPI_DATASIZE_16
580 | VSF_SPI_DATASIZE_32,
581#endif
582
583#ifndef VSF_SPI_MODE_ALL_BITS_MASK
588 VSF_SPI_MODE_ALL_BITS_MASK = VSF_SPI_DIR_MODE_MASK
589 | VSF_SPI_BIT_ORDER_MASK
590 | VSF_SPI_MODE_MASK
591 | VSF_SPI_CS_MODE_MASK
592 | VSF_SPI_DATASIZE_MASK
593#ifdef VSF_SPI_DATALINE_MASK
594 | VSF_SPI_DATALINE_MASK
595#endif
596#ifdef VSF_SPI_MOTOROLA_TI_MASK
597 | VSF_SPI_MOTOROLA_TI_MASK
598#endif
599#ifdef VSF_SPI_CRC_MASK
600 | VSF_SPI_CRC_MASK
601#endif
602#ifdef VSF_SPI_CLOCK_PRESCALER_MASK
603 | VSF_SPI_CLOCK_PRESCALER_MASK
604#endif
605#endif
606};
607
608#if VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK == DISABLED
620typedef enum vsf_spi_irq_mask_t {
621 VSF_SPI_IRQ_MASK_TX = 0x01ul << 0,
622 VSF_SPI_IRQ_MASK_RX = 0x01ul << 1,
623 VSF_SPI_IRQ_MASK_TX_CPL = 0x01ul << 2,
624 VSF_SPI_IRQ_MASK_RX_CPL = 0x01ul << 3,
625 VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR = 0x01ul << 4,
626
640 // VSF_SPI_IRQ_MASK_CRC_ERR = 0x01ul << 5, //! \~english CRC error interrupt \~chinese CRC 错误中断
641
655 // VSF_SPI_IRQ_MASK_FRAME_ERR = 0x01ul << 6, //! \~english Frame error interrupt \~chinese 帧错误中断
656} vsf_spi_irq_mask_t;
657#endif
658
663enum {
664 VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD = VSF_SPI_IRQ_MASK_TX,
665 VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD = VSF_SPI_IRQ_MASK_RX,
666
671 VSF_SPI_IRQ_MASK_CPL = VSF_SPI_IRQ_MASK_RX_CPL,
672
673#ifndef VSF_SPI_IRQ_MASK_ERR
678 VSF_SPI_IRQ_MASK_ERR = VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR,
679#endif
680
681
682#ifndef VSF_SPI_IRQ_ALL_BITS_MASK
687 VSF_SPI_IRQ_ALL_BITS_MASK = VSF_SPI_IRQ_MASK_TX
688 | VSF_SPI_IRQ_MASK_RX
689 | VSF_SPI_IRQ_MASK_TX_CPL
690 | VSF_SPI_IRQ_MASK_RX_CPL
691 | VSF_SPI_IRQ_MASK_ERR,
692#endif
693};
694
695#if VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS == DISABLED
706typedef struct vsf_spi_status_t {
707 union {
708 inherit(vsf_peripheral_status_t)
709 struct {
710 uint32_t is_busy : 1;
712 };
713 };
714} vsf_spi_status_t;
715#endif
716
717#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY == DISABLED
726typedef struct vsf_spi_capability_t {
727#if VSF_SPI_CFG_INHERIT_HAL_CAPABILITY == ENABLED
728 inherit(vsf_peripheral_capability_t)
729#endif
730 vsf_spi_irq_mask_t irq_mask;
731
732 uint8_t support_hardware_cs : 1;
733 uint8_t support_software_cs : 1;
734 uint8_t cs_count : 6;
735
736 uint32_t max_clock_hz;
737 uint32_t min_clock_hz;
738} vsf_spi_capability_t;
739#endif
740
741#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG == DISABLED
748typedef struct vsf_spi_t vsf_spi_t;
761typedef void vsf_spi_isr_handler_t(void *target_ptr,
762 vsf_spi_t *spi_ptr,
763 vsf_spi_irq_mask_t irq_mask);
772typedef struct vsf_spi_isr_t {
773 vsf_spi_isr_handler_t *handler_fn;
774 void *target_ptr;
775 vsf_arch_prio_t prio;
776} vsf_spi_isr_t;
777
784typedef struct vsf_spi_cfg_t {
785 vsf_spi_mode_t mode;
786 uint32_t clock_hz;
787 vsf_spi_isr_t isr;
788 // \~english In hardware chip select mode (`VSF_SPI_CS_HARDWARE_MODE`), this specifies the hardware CS pin index (0 to cs_count-1) to be used for automatic chip select.
789 // \~chinese 在硬件片选模式 (`VSF_SPI_CS_HARDWARE_MODE`) 下，此成员指定用于自动片选的硬件 CS 引脚索引（0 到 cs_count-1）。在软件模式下，此成员被忽略。
790 uint8_t auto_cs_index;
791} vsf_spi_cfg_t;
792#endif
793
794
795#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL == DISABLED
816typedef enum vsf_spi_ctrl_t {
817 __VSF_SPI_CTRL_DUMMY = 0,
818
819 /*
822 VSF_SPI_CTRL_REQUEST_PAUSE = (0x1ul << 0), //! \~english Request to pause SPI transfer \~chinese 请求暂停 SPI 传输
823 VSF_SPI_CTRL_REQUEST_RESUME = (0x1ul << 1), //! \~english Request to resume SPI transfer \~chinese 请求恢复 SPI 传输
824 #define VSF_SPI_CTRL_REQUEST_PAUSE VSF_SPI_CTRL_REQUEST_PAUSE
825 #define VSF_SPI_CTRL_REQUEST_RESUME VSF_SPI_CTRL_REQUEST_RESUME
826 */
827
828 /*
843
848 VSF_SPI_CTRL_QSPI_ENABLE = 0x00ul,
853 VSF_SPI_CTRL_QSPI_DISABLE = 0x01ul,
854 #define VSF_SPI_CTRL_QSPI_ENABLE VSF_SPI_CTRL_QSPI_ENABLE
855 #define VSF_SPI_CTRL_QSPI_DISABLE VSF_SPI_CTRL_QSPI_DISABLE
856
871
874 VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE = 0x02ul,
877 VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE = 0x03ul,
880 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE = 0x04ul,
883 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE = 0x05ul,
890 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE = 0x06ul,
897 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE = 0x07ul,
900 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE = 0x08ul,
903 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE = 0x09ul,
904 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE
905 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE
906 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE
907 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE
908 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE
909 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE
910 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE
911 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE
912
921
924 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE = 0x0Aul,
927 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE = 0x0Bul,
930 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE = 0x0Cul,
933 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE = 0x0Dul,
940 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE = 0x0Eul,
941
946 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE = 0x0Ful,
949 VSF_SPI_CTRL_QSPI_ADDRESS_SET = 0x10ul,
952 VSF_SPI_CTRL_QSPI_ADDRESS_GET = 0x11ul,
953 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE
954 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE
955 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE
956 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE
957 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE
958 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE
959 #define VSF_SPI_CTRL_QSPI_ADDRESS_SET VSF_SPI_CTRL_QSPI_ADDRESS_SET
960 #define VSF_SPI_CTRL_QSPI_ADDRESS_GET VSF_SPI_CTRL_QSPI_ADDRESS_GET
961
970
973 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE = 0x18ul,
976 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE = 0x19ul,
979 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES = 0x1Aul,
982 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES = 0x1Bul,
983 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE
984 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE
985 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES
986 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES
987
1000
1003 VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE = 0x12ul,
1006 VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE = 0x13ul,
1009 VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE = 0x14ul,
1012 VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE = 0x15ul,
1013
1020 VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE = 0x16ul,
1021
1028 VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE = 0x17ul,
1029 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE
1030 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE
1031 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE
1032 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE
1033 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE
1034 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE
1035
1040 VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE = 0x1Cul,
1043 VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE = 0x1Dul,
1044 #define VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE
1045 #define VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE
1046 */
1047} vsf_spi_ctrl_t;
1048#endif
1049
1056typedef struct vsf_spi_op_t {
1058# undef __VSF_HAL_TEMPLATE_API
1059# define __VSF_HAL_TEMPLATE_API VSF_HAL_TEMPLATE_API_FP
1061
1062 VSF_SPI_APIS(vsf_spi)
1063} vsf_spi_op_t;
1064
1065#if VSF_SPI_CFG_MULTI_CLASS == ENABLED
1072struct vsf_spi_t {
1073 const vsf_spi_op_t * op;
1074};
1075#endif
1076
1077/*============================ PROTOTYPES ====================================*/
1078
1095extern vsf_err_t vsf_spi_init(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr);
1096
1109extern void vsf_spi_fini(vsf_spi_t *spi_ptr);
1110
1128extern vsf_err_t vsf_spi_get_configuration(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr);
1129
1142extern fsm_rt_t vsf_spi_enable(vsf_spi_t *spi_ptr);
1143
1156extern fsm_rt_t vsf_spi_disable(vsf_spi_t *spi_ptr);
1157
1172extern void vsf_spi_irq_enable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1173
1186extern void vsf_spi_irq_disable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1187
1213extern vsf_spi_irq_mask_t vsf_spi_irq_clear(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1214
1230extern vsf_err_t vsf_spi_cs_active(vsf_spi_t *spi_ptr, uint_fast8_t index);
1231
1247extern vsf_err_t vsf_spi_cs_inactive(vsf_spi_t *spi_ptr, uint_fast8_t index);
1248
1261extern vsf_spi_status_t vsf_spi_status(vsf_spi_t *spi_ptr);
1262
1275extern vsf_spi_capability_t vsf_spi_capability(vsf_spi_t *spi_ptr);
1276
1318extern void vsf_spi_fifo_transfer(vsf_spi_t *spi_ptr,
1319 void *out_buffer_ptr, uint_fast32_t* out_offset_ptr,
1320 void *in_buffer_ptr, uint_fast32_t* in_offset_ptr,
1321 uint_fast32_t count);
1322
1360extern vsf_err_t vsf_spi_request_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr,
1361 void *in_buffer_ptr, uint_fast32_t count);
1362
1375extern vsf_err_t vsf_spi_cancel_transfer(vsf_spi_t *spi_ptr);
1376
1395extern void vsf_spi_get_transferred_count(vsf_spi_t *spi_ptr, uint_fast32_t *sent_count, uint_fast32_t *received_count);
1396
1419extern vsf_err_t vsf_spi_ctrl(vsf_spi_t *spi_ptr, vsf_spi_ctrl_t ctrl, void *param);
1420
1421
1422/*============================ INLINE FUNCTIONS ==============================*/
1423
1424#if VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS == DISABLED
1439# if defined(VSF_SPI_DATASIZE_BIT_OFFSET) && defined(VSF_SPI_DATASIZE_VALUE_OFFSET)
1440static inline uint8_t vsf_spi_mode_to_data_bits(vsf_spi_mode_t mode)
1441{
1442 int bits = (mode & VSF_SPI_DATASIZE_MASK) >> VSF_SPI_DATASIZE_BIT_OFFSET;
1443 return bits + VSF_SPI_DATASIZE_VALUE_OFFSET;
1444}
1445# else
1446static inline uint8_t vsf_spi_mode_to_data_bits(vsf_spi_mode_t mode)
1447{
1448 uint32_t m = mode & VSF_SPI_DATASIZE_MASK;
1449 switch(m) {
1450#ifdef VSF_SPI_DATASIZE_4
1451 case VSF_SPI_DATASIZE_4:
1452 return 4;
1453#endif
1454#ifdef VSF_SPI_DATASIZE_5
1455 case VSF_SPI_DATASIZE_5:
1456 return 5;
1457#endif
1458#ifdef VSF_SPI_DATASIZE_6
1459 case VSF_SPI_DATASIZE_6:
1460 return 6;
1461#endif
1462#ifdef VSF_SPI_DATASIZE_7
1463 case VSF_SPI_DATASIZE_7:
1464 return 7;
1465#endif
1466 case VSF_SPI_DATASIZE_8:
1467 return 8;
1468#ifdef VSF_SPI_DATASIZE_9
1469 case VSF_SPI_DATASIZE_9:
1470 return 9;
1471#endif
1472#ifdef VSF_SPI_DATASIZE_10
1473 case VSF_SPI_DATASIZE_10:
1474 return 10;
1475#endif
1476#ifdef VSF_SPI_DATASIZE_11
1477 case VSF_SPI_DATASIZE_11:
1478 return 11;
1479#endif
1480#ifdef VSF_SPI_DATASIZE_12
1481 case VSF_SPI_DATASIZE_12:
1482 return 12;
1483#endif
1484#ifdef VSF_SPI_DATASIZE_13
1485 case VSF_SPI_DATASIZE_13:
1486 return 13;
1487#endif
1488#ifdef VSF_SPI_DATASIZE_14
1489 case VSF_SPI_DATASIZE_14:
1490 return 14;
1491#endif
1492#ifdef VSF_SPI_DATASIZE_15
1493 case VSF_SPI_DATASIZE_15:
1494 return 15;
1495#endif
1496#ifdef VSF_SPI_DATASIZE_16
1497 case VSF_SPI_DATASIZE_16:
1498 return 16;
1499#endif
1500#ifdef VSF_SPI_DATASIZE_17
1501 case VSF_SPI_DATASIZE_17:
1502 return 17;
1503#endif
1504#ifdef VSF_SPI_DATASIZE_18
1505 case VSF_SPI_DATASIZE_18:
1506 return 18;
1507#endif
1508#ifdef VSF_SPI_DATASIZE_19
1509 case VSF_SPI_DATASIZE_19:
1510 return 19;
1511#endif
1512#ifdef VSF_SPI_DATASIZE_20
1513 case VSF_SPI_DATASIZE_20:
1514 return 20;
1515#endif
1516#ifdef VSF_SPI_DATASIZE_21
1517 case VSF_SPI_DATASIZE_21:
1518 return 21;
1519#endif
1520#ifdef VSF_SPI_DATASIZE_22
1521 case VSF_SPI_DATASIZE_22:
1522 return 22;
1523#endif
1524#ifdef VSF_SPI_DATASIZE_23
1525 case VSF_SPI_DATASIZE_23:
1526 return 23;
1527#endif
1528#ifdef VSF_SPI_DATASIZE_24
1529 case VSF_SPI_DATASIZE_24:
1530 return 24;
1531#endif
1532#ifdef VSF_SPI_DATASIZE_25
1533 case VSF_SPI_DATASIZE_25:
1534 return 25;
1535#endif
1536#ifdef VSF_SPI_DATASIZE_26
1537 case VSF_SPI_DATASIZE_26:
1538 return 26;
1539#endif
1540#ifdef VSF_SPI_DATASIZE_27
1541 case VSF_SPI_DATASIZE_27:
1542 return 27;
1543#endif
1544#ifdef VSF_SPI_DATASIZE_28
1545 case VSF_SPI_DATASIZE_28:
1546 return 28;
1547#endif
1548#ifdef VSF_SPI_DATASIZE_29
1549 case VSF_SPI_DATASIZE_29:
1550 return 29;
1551#endif
1552#ifdef VSF_SPI_DATASIZE_30
1553 case VSF_SPI_DATASIZE_30:
1554 return 30;
1555#endif
1556#ifdef VSF_SPI_DATASIZE_31
1557 case VSF_SPI_DATASIZE_31:
1558 return 31;
1559#endif
1560#ifdef VSF_SPI_DATASIZE_32
1561 case VSF_SPI_DATASIZE_32:
1562 return 32;
1563#endif
1564 default:
1565 return 0;
1566 }
1567}
1568# endif
1569#endif
1570
1571#if VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE == DISABLED
1586# if defined(VSF_SPI_DATASIZE_BIT_OFFSET) && defined(VSF_SPI_DATASIZE_VALUE_OFFSET)
1587static inline vsf_spi_mode_t vsf_spi_data_bits_to_mode(uint8_t data_bits)
1588{
1589 return (vsf_spi_mode_t)((data_bits - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET);
1590}
1591# else
1592static inline vsf_spi_mode_t vsf_spi_data_bits_to_mode(uint8_t data_bits)
1593{
1594 switch (data_bits) {
1595#ifdef VSF_SPI_DATASIZE_4
1596 case 4:
1597 return VSF_SPI_DATASIZE_4;
1598#endif
1599#ifdef VSF_SPI_DATASIZE_5
1600 case 5:
1601 return VSF_SPI_DATASIZE_5;
1602#endif
1603#ifdef VSF_SPI_DATASIZE_6
1604 case 6:
1605 return VSF_SPI_DATASIZE_6;
1606#endif
1607#ifdef VSF_SPI_DATASIZE_7
1608 case 7:
1609 return VSF_SPI_DATASIZE_7;
1610#endif
1611 case 8:
1612 return VSF_SPI_DATASIZE_8;
1613#ifdef VSF_SPI_DATASIZE_9
1614 case 9:
1615 return VSF_SPI_DATASIZE_9;
1616#endif
1617#ifdef VSF_SPI_DATASIZE_10
1618 case 10:
1619 return VSF_SPI_DATASIZE_10;
1620#endif
1621#ifdef VSF_SPI_DATASIZE_11
1622 case 11:
1623 return VSF_SPI_DATASIZE_11;
1624#endif
1625#ifdef VSF_SPI_DATASIZE_12
1626 case 12:
1627 return VSF_SPI_DATASIZE_12;
1628#endif
1629#ifdef VSF_SPI_DATASIZE_13
1630 case 13:
1631 return VSF_SPI_DATASIZE_13;
1632#endif
1633#ifdef VSF_SPI_DATASIZE_14
1634 case 14:
1635 return VSF_SPI_DATASIZE_14;
1636#endif
1637#ifdef VSF_SPI_DATASIZE_15
1638 case 15:
1639 return VSF_SPI_DATASIZE_15;
1640#endif
1641#ifdef VSF_SPI_DATASIZE_16
1642 case 16:
1643 return VSF_SPI_DATASIZE_16;
1644#endif
1645#ifdef VSF_SPI_DATASIZE_17
1646 case 17:
1647 return VSF_SPI_DATASIZE_17;
1648#endif
1649#ifdef VSF_SPI_DATASIZE_18
1650 case 18:
1651 return VSF_SPI_DATASIZE_18;
1652#endif
1653#ifdef VSF_SPI_DATASIZE_19
1654 case 19:
1655 return VSF_SPI_DATASIZE_19;
1656#endif
1657#ifdef VSF_SPI_DATASIZE_20
1658 case 20:
1659 return VSF_SPI_DATASIZE_20;
1660#endif
1661#ifdef VSF_SPI_DATASIZE_21
1662 case 21:
1663 return VSF_SPI_DATASIZE_21;
1664#endif
1665#ifdef VSF_SPI_DATASIZE_22
1666 case 22:
1667 return VSF_SPI_DATASIZE_22;
1668#endif
1669#ifdef VSF_SPI_DATASIZE_23
1670 case 23:
1671 return VSF_SPI_DATASIZE_23;
1672#endif
1673#ifdef VSF_SPI_DATASIZE_24
1674 case 24:
1675 return VSF_SPI_DATASIZE_24;
1676#endif
1677#ifdef VSF_SPI_DATASIZE_25
1678 case 25:
1679 return VSF_SPI_DATASIZE_25;
1680#endif
1681#ifdef VSF_SPI_DATASIZE_26
1682 case 26:
1683 return VSF_SPI_DATASIZE_26;
1684#endif
1685#ifdef VSF_SPI_DATASIZE_27
1686 case 27:
1687 return VSF_SPI_DATASIZE_27;
1688#endif
1689#ifdef VSF_SPI_DATASIZE_28
1690 case 28:
1691 return VSF_SPI_DATASIZE_28;
1692#endif
1693#ifdef VSF_SPI_DATASIZE_29
1694 case 29:
1695 return VSF_SPI_DATASIZE_29;
1696#endif
1697#ifdef VSF_SPI_DATASIZE_30
1698 case 30:
1699 return VSF_SPI_DATASIZE_30;
1700#endif
1701#ifdef VSF_SPI_DATASIZE_31
1702 case 31:
1703 return VSF_SPI_DATASIZE_31;
1704#endif
1705#ifdef VSF_SPI_DATASIZE_32
1706 case 32:
1707 return VSF_SPI_DATASIZE_32;
1708#endif
1709 default:
1710 return (vsf_spi_mode_t)0;
1711 }
1712}
1713# endif
1714#endif
1715
1716#if VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES == DISABLED
1731static inline uint8_t vsf_spi_mode_to_data_bytes(vsf_spi_mode_t mode)
1732{
1733 uint8_t bits = vsf_spi_mode_to_data_bits(mode);
1734 if (bits == 0) {
1735 return 0; // Error: invalid data bits
1736 } else if (bits <= 8) {
1737 return 1;
1738 } else if (bits <= 16) {
1739 return 2;
1740 } else {
1741 return 4;
1742 }
1743}
1744#endif
1745
1746/*============================ MACROFIED FUNCTIONS ===========================*/
1747
1749#if VSF_SPI_CFG_FUNCTION_RENAME == ENABLED
1750# define __vsf_spi_t VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_t)
1751# define vsf_spi_init(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_init) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1752# define vsf_spi_fini(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_fini) ((__vsf_spi_t *)(__SPI))
1753# define vsf_spi_get_configuration(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_get_configuration) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1754# define vsf_spi_enable(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_enable) ((__vsf_spi_t *)(__SPI))
1755# define vsf_spi_disable(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_disable) ((__vsf_spi_t *)(__SPI))
1756# define vsf_spi_irq_enable(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_enable) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1757# define vsf_spi_irq_disable(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_disable) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1758# define vsf_spi_irq_clear(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_clear) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1759# define vsf_spi_status(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_status) ((__vsf_spi_t *)(__SPI))
1760# define vsf_spi_capability(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_capability) ((__vsf_spi_t *)(__SPI))
1761# define vsf_spi_cs_active(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cs_active) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1762# define vsf_spi_cs_inactive(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cs_inactive) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1763# define vsf_spi_fifo_transfer(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_fifo_transfer) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1764# define vsf_spi_request_transfer(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_request_transfer) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1765# define vsf_spi_cancel_transfer(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cancel_transfer) ((__vsf_spi_t *)(__SPI))
1766# define vsf_spi_get_transferred_count(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_get_transferred_count)((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1767# define vsf_spi_ctrl(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_ctrl) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1768
1769# define vsf_qspi_t vsf_spi_t
1770# define vsf_qspi_mode_t vsf_spi_mode_t
1771# define vsf_qspi_irq_mask_t vsf_spi_irq_mask_t
1772# define vsf_qspi_status_t vsf_spi_status_t
1773# define vsf_qspi_capability_t vsf_spi_capability_t
1774# define vsf_qspi_isr_handler_t vsf_spi_isr_handler_t
1775# define vsf_qspi_isr_t vsf_spi_isr_t
1776# define vsf_qspi_cfg_t vsf_spi_cfg_t
1777# define vsf_qspi_ctrl_t vsf_spi_ctrl_t
1778
1793# define vsf_qspi_init(__SPI, __CFG_PTR) vsf_spi_init((__vsf_spi_t *)(__SPI), (__CFG_PTR))
1794
1807# define vsf_qspi_fini(__SPI) vsf_spi_fini((__vsf_spi_t *)(__SPI))
1808
1821# define vsf_qspi_enable(__SPI) vsf_spi_enable((__vsf_spi_t *)(__SPI))
1822
1835# define vsf_qspi_disable(__SPI) vsf_spi_disable((__vsf_spi_t *)(__SPI))
1836
1851# define vsf_qspi_irq_enable(__SPI, __IRQ_MASK) vsf_spi_irq_enable((__vsf_spi_t *)(__SPI), (__IRQ_MASK))
1852
1867# define vsf_qspi_irq_disable(__SPI, __IRQ_MASK) vsf_spi_irq_disable((__vsf_spi_t *)(__SPI), (__IRQ_MASK))
1868
1881# define vsf_qspi_status(__SPI) vsf_spi_status((__vsf_spi_t *)(__SPI))
1882
1895# define vsf_qspi_capability(__SPI) vsf_spi_capability((__vsf_spi_t *)(__SPI))
1896
1917# define vsf_qspi_fifo_write(__SPI, __OUT_BUFFER_PTR, __OUT_OFFSET_PTR, __COUNT) \
1918 vsf_spi_fifo_transfer((__vsf_spi_t *)(__SPI), (__OUT_BUFFER_PTR), (__OUT_OFFSET_PTR), NULL, NULL, (__COUNT))
1919
1940# define vsf_qspi_fifo_read(__SPI, __IN_BUFFER_PTR, __IN_OFFSET_PTR, __COUNT) \
1941 vsf_spi_fifo_transfer((__vsf_spi_t *)(__SPI), NULL, NULL, (__IN_BUFFER_PTR), (__IN_OFFSET_PTR), (__COUNT))
1942
1961# define vsf_qspi_request_tx(__SPI, __OUT_BUF, __CNT) vsf_spi_request_transfer((__vsf_spi_t *)(__SPI), (__OUT_BUF), NULL, (__CNT))
1962
1981# define vsf_qspi_request_rx(__SPI, __IN_BUF, __CNT) vsf_spi_request_transfer((__vsf_spi_t *)(__SPI), NULL, (__IN_BUF), (__CNT))
1982
2006# define vsf_qspi_cancel_transfer(__SPI) vsf_spi_cancel_transfer((__vsf_spi_t *)(__SPI))
2007
2024# define vsf_qspi_get_transferred_count(__SPI, __TX_CNT, __RX_CNT) \
2025 vsf_spi_get_transferred_count((__vsf_spi_t *)(__SPI), (__TX_CNT), (__RX_CNT))
2026
2043# define vsf_qspi_ctrl(__SPI, __CTRL, __PARAM) vsf_spi_ctrl((__vsf_spi_t *)(__SPI), (__CTRL), (__PARAM))
2044#endif
2046
2047#ifdef __cplusplus
2048}
2049#endif
2050
2051#endif /*__VSF_TEMPLATE_SPI_H__*/
2052
vsf_err_t
vsf_err_t
Definition __type.h:42
vsf_spi_mode_t
vsf_spi_mode_t
Definition spi.h:33
VSF_SPI_DATASIZE_31
@ VSF_SPI_DATASIZE_31
Definition spi.h:67
VSF_SPI_DATASIZE_28
@ VSF_SPI_DATASIZE_28
Definition spi.h:64
VSF_SPI_DATASIZE_6
@ VSF_SPI_DATASIZE_6
Definition spi.h:98
VSF_SPI_DATASIZE_17
@ VSF_SPI_DATASIZE_17
Definition spi.h:53
VSF_SPI_DATASIZE_9
@ VSF_SPI_DATASIZE_9
Definition spi.h:45
VSF_SPI_DATASIZE_18
@ VSF_SPI_DATASIZE_18
Definition spi.h:54
VSF_SPI_DATASIZE_11
@ VSF_SPI_DATASIZE_11
Definition spi.h:47
VSF_SPI_DATASIZE_20
@ VSF_SPI_DATASIZE_20
Definition spi.h:56
VSF_SPI_DATASIZE_21
@ VSF_SPI_DATASIZE_21
Definition spi.h:57
VSF_SPI_DATASIZE_27
@ VSF_SPI_DATASIZE_27
Definition spi.h:63
VSF_SPI_DATASIZE_14
@ VSF_SPI_DATASIZE_14
Definition spi.h:50
VSF_SPI_DATASIZE_BIT_OFFSET
@ VSF_SPI_DATASIZE_BIT_OFFSET
Definition spi.h:42
VSF_SPI_DATASIZE_26
@ VSF_SPI_DATASIZE_26
Definition spi.h:62
VSF_SPI_DATASIZE_13
@ VSF_SPI_DATASIZE_13
Definition spi.h:49
VSF_SPI_DATASIZE_7
@ VSF_SPI_DATASIZE_7
Definition spi.h:99
VSF_SPI_DATASIZE_5
@ VSF_SPI_DATASIZE_5
Definition spi.h:97
VSF_SPI_DATASIZE_12
@ VSF_SPI_DATASIZE_12
Definition spi.h:48
VSF_SPI_DATASIZE_22
@ VSF_SPI_DATASIZE_22
Definition spi.h:58
VSF_SPI_DATASIZE_24
@ VSF_SPI_DATASIZE_24
Definition spi.h:60
VSF_SPI_DATASIZE_4
@ VSF_SPI_DATASIZE_4
datasize is 8 bits
Definition spi.h:96
VSF_SPI_DATASIZE_29
@ VSF_SPI_DATASIZE_29
Definition spi.h:65
VSF_SPI_DATASIZE_25
@ VSF_SPI_DATASIZE_25
Definition spi.h:61
VSF_SPI_DATASIZE_30
@ VSF_SPI_DATASIZE_30
Definition spi.h:66
VSF_SPI_DATASIZE_19
@ VSF_SPI_DATASIZE_19
Definition spi.h:55
VSF_SPI_DATASIZE_23
@ VSF_SPI_DATASIZE_23
Definition spi.h:59
VSF_SPI_DATASIZE_10
@ VSF_SPI_DATASIZE_10
Definition spi.h:46
VSF_SPI_DATASIZE_15
@ VSF_SPI_DATASIZE_15
Definition spi.h:51
vsf_arch_prio_t
vsf_arch_prio_t
Definition cortex_a_generic.h:88
irq_mask
const i_spi_t vsf_spi_irq_mask_t irq_mask
Definition spi_interface.h:38
uint_fast8_t
unsigned char uint_fast8_t
Definition stdint.h:23
uint32_t
unsigned uint32_t
Definition stdint.h:9
uint_fast32_t
unsigned int uint_fast32_t
Definition stdint.h:27
uint8_t
unsigned char uint8_t
Definition stdint.h:5
vsf_peripheral_capability_t
Definition vsf_template_hal_driver.h:203
vsf_peripheral_status_t
Definition vsf_template_hal_driver.h:196
vsf_spi_capability_t
Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware...
Definition vsf_template_spi.h:726
vsf_spi_capability_t::support_software_cs
uint8_t support_software_cs
Hardware chip select support (1: supported, 0: not supported)
Definition vsf_template_spi.h:733
vsf_spi_capability_t::max_clock_hz
uint32_t max_clock_hz
Number of available chip select lines (0-63)
Definition vsf_template_spi.h:736
vsf_spi_capability_t::cs_count
uint8_t cs_count
Software chip select support (1: supported, 0: not supported)
Definition vsf_template_spi.h:734
vsf_spi_capability_t::irq_mask
vsf_spi_irq_mask_t irq_mask
Definition spi.h:128
vsf_spi_capability_t::support_hardware_cs
uint8_t support_hardware_cs
Supported interrupt masks for SPI operations.
Definition vsf_template_spi.h:732
vsf_spi_capability_t::min_clock_hz
uint32_t min_clock_hz
Maximum supported SPI clock frequency in Hz.
Definition vsf_template_spi.h:737
vsf_spi_capability_t::inherit
inherit(vsf_peripheral_capability_t) vsf_spi_irq_mask_t irq_mask
Inherit peripheral capabilities.
vsf_spi_cfg_t
Configuration structure for SPI.
Definition vsf_template_spi.h:784
vsf_spi_cfg_t::clock_hz
uint32_t clock_hz
SPI operating mode (master/slave, CPOL/CPHA, bit order, data size)
Definition vsf_template_spi.h:786
vsf_spi_cfg_t::isr
vsf_spi_isr_t isr
SPI clock frequency in Hz (must be between min_clock_hz and max_clock_hz)
Definition vsf_template_spi.h:787
vsf_spi_cfg_t::mode
vsf_spi_mode_t mode
Definition vsf_template_spi.h:785
vsf_spi_cfg_t::auto_cs_index
uint8_t auto_cs_index
Interrupt configuration (handler, target pointer, priority)
Definition vsf_template_spi.h:790
vsf_spi_isr_t
SPI interrupt service routine configuration structure.
Definition vsf_template_spi.h:772
vsf_spi_isr_t::handler_fn
vsf_spi_isr_handler_t * handler_fn
Definition vsf_template_spi.h:773
vsf_spi_isr_t::target_ptr
void * target_ptr
Interrupt handler function (NULL to disable interrupts)
Definition vsf_template_spi.h:774
vsf_spi_isr_t::prio
vsf_arch_prio_t prio
User context pointer passed to handler.
Definition vsf_template_spi.h:775
vsf_spi_op_t
SPI operation function pointer type, used for SPI Multi Class support.
Definition vsf_template_spi.h:1056
vsf_spi_status_t
Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doe...
Definition vsf_template_spi.h:706
vsf_spi_status_t::is_busy
uint32_t is_busy
Definition spi.h:118
vsf_spi_t
SPI instance structure, used for SPI Multi Class support, not needed in non Multi Class mode.
Definition vsf_template_spi.h:1072
vsf_spi_t::op
const vsf_spi_op_t * op
Definition vsf_template_spi.h:1073
vsf_spi_isr_handler_t
void vsf_spi_isr_handler_t(void *target_ptr, vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Definition spi.h:180
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Definition spi.h:139
vsf_spi_mode_t
vsf_spi_mode_t
Definition spi.h:115
vsf_arch.h
fsm_rt_t
fsm_rt_t
Definition vsf_fsm.h:315
vsf_spi
vsf_spi_t vsf_spi[SPI_COUNT]
Definition vsf_spi.c:3
vsf_template_hal_driver.h
VSF_SPI_IRQ_MASK_CPL
@ VSF_SPI_IRQ_MASK_CPL
Alias for VSF_SPI_IRQ_MASK_RX.
Definition vsf_template_spi.h:671
VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD
@ VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD
Definition vsf_template_spi.h:664
VSF_SPI_IRQ_ALL_BITS_MASK
@ VSF_SPI_IRQ_ALL_BITS_MASK
Definition vsf_template_spi.h:687
VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD
@ VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD
Alias for VSF_SPI_IRQ_MASK_TX.
Definition vsf_template_spi.h:665
VSF_SPI_IRQ_MASK_ERR
@ VSF_SPI_IRQ_MASK_ERR
Definition vsf_template_spi.h:678
vsf_spi_fifo_transfer
void vsf_spi_fifo_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr, uint_fast32_t *out_offset_ptr, void *in_buffer_ptr, uint_fast32_t *in_offset_ptr, uint_fast32_t count)
Perform FIFO-based data transfer on a SPI instance.
Definition spi_common.c:137
vsf_spi_isr_t
struct vsf_spi_isr_t vsf_spi_isr_t
SPI interrupt service routine configuration structure.
vsf_spi_isr_handler_t
void vsf_spi_isr_handler_t(void *target_ptr, vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
SPI interrupt handler type declaration.
Definition vsf_template_spi.h:761
vsf_spi_status
vsf_spi_status_t vsf_spi_status(vsf_spi_t *spi_ptr)
Get the current status of a SPI instance.
Definition spi_common.c:110
vsf_spi_request_transfer
vsf_err_t vsf_spi_request_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr, void *in_buffer_ptr, uint_fast32_t count)
Request a SPI data transfer operation.
Definition spi_common.c:149
vsf_spi_cfg_t
struct vsf_spi_cfg_t vsf_spi_cfg_t
Configuration structure for SPI.
vsf_spi_capability_t
struct vsf_spi_capability_t vsf_spi_capability_t
Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware...
VSF_SPI_APIS
#define VSF_SPI_APIS(__prefix_name)
SPI API template, used to generate SPI type, specific prefix function declarations,...
Definition vsf_template_spi.h:238
VSF_SPI_MODE_MASK
@ VSF_SPI_MODE_MASK
SPI mode mask for clock polarity and phase configuration.
Definition vsf_template_spi.h:551
VSF_SPI_BIT_ORDER_MASK
@ VSF_SPI_BIT_ORDER_MASK
SPI bit order mask for MSB/LSB first selection.
Definition vsf_template_spi.h:540
VSF_SPI_DIR_MODE_MASK
@ VSF_SPI_DIR_MODE_MASK
SPI direction mode mask for master/slave selection.
Definition vsf_template_spi.h:529
VSF_SPI_CS_MODE_MASK
@ VSF_SPI_CS_MODE_MASK
Definition vsf_template_spi.h:561
VSF_SPI_MODE_ALL_BITS_MASK
@ VSF_SPI_MODE_ALL_BITS_MASK
Definition vsf_template_spi.h:588
VSF_SPI_DATASIZE_MASK
@ VSF_SPI_DATASIZE_MASK
Definition vsf_template_spi.h:578
vsf_spi_get_configuration
vsf_err_t vsf_spi_get_configuration(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr)
Get current configuration of a SPI instance.
Definition spi_common.c:55
vsf_spi_get_transferred_count
void vsf_spi_get_transferred_count(vsf_spi_t *spi_ptr, uint_fast32_t *sent_count, uint_fast32_t *received_count)
Get the number of data units transferred in the current or last SPI operation.
Definition spi_common.c:169
vsf_spi_cs_active
vsf_err_t vsf_spi_cs_active(vsf_spi_t *spi_ptr, uint_fast8_t index)
Activate (assert) a SPI chip select line.
Definition spi_common.c:119
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Predefined VSF SPI interrupt masks that can be reimplemented in specific HAL drivers....
Definition vsf_template_spi.h:620
VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR
@ VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR
RX complete interrupt (triggers when RX transfer is complete)
Definition vsf_template_spi.h:625
VSF_SPI_IRQ_MASK_RX_CPL
@ VSF_SPI_IRQ_MASK_RX_CPL
TX complete interrupt (triggers when all TX data has been sent)
Definition vsf_template_spi.h:624
VSF_SPI_IRQ_MASK_RX
@ VSF_SPI_IRQ_MASK_RX
TX FIFO threshold interrupt (triggers when TX FIFO level is below threshold)
Definition vsf_template_spi.h:622
VSF_SPI_IRQ_MASK_TX
@ VSF_SPI_IRQ_MASK_TX
Definition vsf_template_spi.h:621
VSF_SPI_IRQ_MASK_TX_CPL
@ VSF_SPI_IRQ_MASK_TX_CPL
RX FIFO threshold interrupt (triggers when RX FIFO level is above threshold)
Definition vsf_template_spi.h:623
vsf_spi_ctrl
vsf_err_t vsf_spi_ctrl(vsf_spi_t *spi_ptr, vsf_spi_ctrl_t ctrl, void *param)
Execute a control command on the SPI instance.
Definition spi_common.c:188
vsf_spi_enable
fsm_rt_t vsf_spi_enable(vsf_spi_t *spi_ptr)
Enable a SPI instance for operation.
Definition spi_common.c:65
vsf_spi_irq_clear
vsf_spi_irq_mask_t vsf_spi_irq_clear(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Clear interrupt flags of SPI instance and return previous state.
Definition spi_common.c:101
vsf_spi_disable
fsm_rt_t vsf_spi_disable(vsf_spi_t *spi_ptr)
Disable a SPI instance from operation.
Definition spi_common.c:74
vsf_spi_status_t
struct vsf_spi_status_t vsf_spi_status_t
Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doe...
vsf_spi_mode_t
vsf_spi_mode_t
Predefined VSF SPI modes that can be reimplemented in specific HAL drivers.
Definition vsf_template_spi.h:296
VSF_SPI_CPHA_LOW
@ VSF_SPI_CPHA_LOW
Clock polarity: idle state is high.
Definition vsf_template_spi.h:310
VSF_SPI_SLAVE
@ VSF_SPI_SLAVE
Master mode (controller)
Definition vsf_template_spi.h:299
VSF_SPI_DATASIZE_16
@ VSF_SPI_DATASIZE_16
8-bit data transfer size (requires 1-byte buffer)
Definition vsf_template_spi.h:330
VSF_SPI_LSB_FIRST
@ VSF_SPI_LSB_FIRST
Most Significant Bit (MSB) first.
Definition vsf_template_spi.h:303
VSF_SPI_CPOL_HIGH
@ VSF_SPI_CPOL_HIGH
Clock polarity: idle state is low.
Definition vsf_template_spi.h:307
VSF_SPI_MODE_1
@ VSF_SPI_MODE_1
Mode 0: CPOL=0 (idle low), CPHA=0 (sample on first edge)
Definition vsf_template_spi.h:314
VSF_SPI_DATASIZE_8
@ VSF_SPI_DATASIZE_8
Definition vsf_template_spi.h:329
VSF_SPI_MASTER
@ VSF_SPI_MASTER
Definition vsf_template_spi.h:298
VSF_SPI_CPHA_HIGH
@ VSF_SPI_CPHA_HIGH
Clock phase: sample on first edge.
Definition vsf_template_spi.h:311
VSF_SPI_MSB_FIRST
@ VSF_SPI_MSB_FIRST
Slave mode (peripheral)
Definition vsf_template_spi.h:302
VSF_SPI_DATASIZE_32
@ VSF_SPI_DATASIZE_32
16-bit data transfer size (requires 2-byte buffer)
Definition vsf_template_spi.h:331
VSF_SPI_CS_SOFTWARE_MODE
@ VSF_SPI_CS_SOFTWARE_MODE
Mode 3: CPOL=1 (idle high), CPHA=1 (sample on second edge)
Definition vsf_template_spi.h:321
VSF_SPI_MODE_0
@ VSF_SPI_MODE_0
Clock phase: sample on second edge.
Definition vsf_template_spi.h:313
VSF_SPI_CS_HARDWARE_MODE
@ VSF_SPI_CS_HARDWARE_MODE
Definition vsf_template_spi.h:324
VSF_SPI_MODE_3
@ VSF_SPI_MODE_3
Mode 2: CPOL=1 (idle high), CPHA=0 (sample on first edge)
Definition vsf_template_spi.h:316
VSF_SPI_CPOL_LOW
@ VSF_SPI_CPOL_LOW
Least Significant Bit (LSB) first.
Definition vsf_template_spi.h:306
VSF_SPI_MODE_2
@ VSF_SPI_MODE_2
Mode 1: CPOL=0 (idle low), CPHA=1 (sample on second edge)
Definition vsf_template_spi.h:315
vsf_spi_irq_disable
void vsf_spi_irq_disable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Disable specific interrupts for a SPI instance.
Definition spi_common.c:92
vsf_spi_ctrl_t
vsf_spi_ctrl_t
Predefined VSF SPI control commands that can be reimplemented in specific HAL drivers.
Definition vsf_template_spi.h:816
__VSF_SPI_CTRL_DUMMY
@ __VSF_SPI_CTRL_DUMMY
Definition vsf_template_spi.h:817
vsf_spi_init
vsf_err_t vsf_spi_init(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr)
Initialize a SPI instance.
Definition spi_common.c:37
vsf_spi_irq_enable
void vsf_spi_irq_enable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Enable specific interrupts for a SPI instance.
Definition spi_common.c:83
vsf_spi_fini
void vsf_spi_fini(vsf_spi_t *spi_ptr)
Finalize (deinitialize) a SPI instance.
Definition spi_common.c:46
vsf_spi_cs_inactive
vsf_err_t vsf_spi_cs_inactive(vsf_spi_t *spi_ptr, uint_fast8_t index)
Deactivate (deassert) a SPI chip select line.
Definition spi_common.c:128
vsf_spi_cancel_transfer
vsf_err_t vsf_spi_cancel_transfer(vsf_spi_t *spi_ptr)
Cancel an ongoing SPI transfer operation.
Definition spi_common.c:160
vsf_spi_capability
vsf_spi_capability_t vsf_spi_capability(vsf_spi_t *spi_ptr)
Get the capabilities of a SPI instance.
Definition spi_common.c:179
Generated from commit: vsfteam/vsf@3f091ef