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vsf_template_spi.h
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1/*****************************************************************************
2 * Copyright(C)2009-2022 by VSF Team *
3 * *
4 * Licensed under the Apache License, Version 2.0 (the "License"); *
5 * you may not use this file except in compliance with the License. *
6 * You may obtain a copy of the License at *
7 * *
8 * http://www.apache.org/licenses/LICENSE-2.0 *
9 * *
10 * Unless required by applicable law or agreed to in writing, software *
11 * distributed under the License is distributed on an "AS IS" BASIS, *
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
13 * See the License for the specific language governing permissions and *
14 * limitations under the License. *
15 * *
16 ****************************************************************************/
17
18#ifndef __VSF_TEMPLATE_SPI_H__
19#define __VSF_TEMPLATE_SPI_H__
20
21/*============================ INCLUDES ======================================*/
22
23#include "./vsf_template_hal_driver.h"
24#include "hal/arch/vsf_arch.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/*============================ MACROS ========================================*/
31
39#ifndef VSF_SPI_CFG_MULTI_CLASS
40# define VSF_SPI_CFG_MULTI_CLASS ENABLED
41#endif
42
50#if defined(VSF_HW_SPI_COUNT) && !defined(VSF_HW_SPI_MASK)
51# define VSF_HW_SPI_MASK VSF_HAL_COUNT_TO_MASK(VSF_HW_SPI_COUNT)
52#endif
53
61#if defined(VSF_HW_SPI_MASK) && !defined(VSF_HW_SPI_COUNT)
62# define VSF_HW_SPI_COUNT VSF_HAL_MASK_TO_COUNT(VSF_HW_SPI_MASK)
63#endif
64
73#ifndef VSF_SPI_CFG_PREFIX
74# if (VSF_SPI_CFG_MULTI_CLASS == DISABLED) && defined(VSF_HW_SPI_COUNT) && (VSF_HW_SPI_COUNT != 0)
75# define VSF_SPI_CFG_PREFIX vsf_hw
76# else
77# define VSF_SPI_CFG_PREFIX vsf
78# endif
79#endif
80
89#ifndef VSF_SPI_CFG_FUNCTION_RENAME
90# define VSF_SPI_CFG_FUNCTION_RENAME ENABLED
91#endif
92
101#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE
102# define VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE DISABLED
103#endif
104
114#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK
115# define VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK DISABLED
116#endif
117
127#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS
128# define VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS DISABLED
129#endif
130
143#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG
144# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG DISABLED
145#endif
146
156#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL
157# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL DISABLED
158#endif
159
170#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY
171# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY DISABLED
172#endif
173
183#ifndef VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS
184# define VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS DISABLED
185#endif
186
196#ifndef VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE
197# define VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE DISABLED
198#endif
199
209#ifndef VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES
210# define VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES DISABLED
211#endif
212
222#ifndef VSF_SPI_CFG_INHERIT_HAL_CAPABILITY
223# define VSF_SPI_CFG_INHERIT_HAL_CAPABILITY ENABLED
224#endif
225
226/*============================ MACROFIED FUNCTIONS ===========================*/
227
236#define VSF_SPI_APIS(__prefix_name) \
237 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, init, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_cfg_t *cfg_ptr) \
238 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, fini, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
239 __VSF_HAL_TEMPLATE_API(__prefix_name, fsm_rt_t, spi, enable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
240 __VSF_HAL_TEMPLATE_API(__prefix_name, fsm_rt_t, spi, disable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
241 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, irq_enable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
242 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, irq_disable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
243 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_status_t, spi, status, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
244 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_capability_t, spi, capability, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
245 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cs_active, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast8_t index) \
246 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cs_inactive, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast8_t index) \
247 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, fifo_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, void *out_buffer_ptr, uint_fast32_t *out_offset_ptr, void *in_buffer_ptr, uint_fast32_t *in_offset_ptr, uint_fast32_t cnt) \
248 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, request_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, void *out_buffer_ptr, void *in_buffer_ptr, uint_fast32_t count) \
249 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cancel_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
250 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, get_transferred_count, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast32_t * tx_count, uint_fast32_t *rx_count) \
251 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, ctrl, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_ctrl_t ctrl, void* param)
252
253
254/*============================ TYPES =========================================*/
255
256#if VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE == DISABLED
273typedef enum vsf_spi_mode_t {
274 VSF_SPI_MASTER = 0x00ul << 0,
275 VSF_SPI_SLAVE = 0x01ul << 0,
276 VSF_SPI_MSB_FIRST = 0x00ul << 1,
277 VSF_SPI_LSB_FIRST = 0x01ul << 1,
278
279 VSF_SPI_CPOL_LOW = 0x00ul << 2,
280 VSF_SPI_CPOL_HIGH = 0x01ul << 2,
281 VSF_SPI_CPHA_LOW = 0x00ul << 2,
282 VSF_SPI_CPHA_HIGH = 0x01ul << 2,
283
284 VSF_SPI_MODE_0 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_LOW,
285 VSF_SPI_MODE_1 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_HIGH,
286 VSF_SPI_MODE_2 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_LOW,
287 VSF_SPI_MODE_3 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_HIGH,
288
289 VSF_SPI_CS_SOFTWARE_MODE = 0x00ul << 4,
290 VSF_SPI_CS_HARDWARE_MODE = 0x01ul << 4,
291
292 VSF_SPI_DATASIZE_8 = 0x00ul << 8,
293 VSF_SPI_DATASIZE_16 = 0x01ul << 8,
294 VSF_SPI_DATASIZE_32 = 0x02ul << 8,
295 /*
298 VSF_SPI_DATASIZE_VALUE_OFFSET = 1,
299 VSF_SPI_DATASIZE_BIT_OFFSET = 8,
300 VSF_SPI_DATASIZE_4 = ( 4ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
301 VSF_SPI_DATASIZE_5 = ( 5ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
302 VSF_SPI_DATASIZE_6 = ( 6ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
303 VSF_SPI_DATASIZE_7 = ( 7ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
304 VSF_SPI_DATASIZE_8 = ( 8ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
305 VSF_SPI_DATASIZE_9 = ( 9ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
306 VSF_SPI_DATASIZE_10 = (10ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
307 VSF_SPI_DATASIZE_11 = (11ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
308 VSF_SPI_DATASIZE_12 = (12ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
309 VSF_SPI_DATASIZE_13 = (13ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
310 VSF_SPI_DATASIZE_14 = (14ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
311 VSF_SPI_DATASIZE_15 = (15ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
312 VSF_SPI_DATASIZE_16 = (16ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
313 VSF_SPI_DATASIZE_17 = (17ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
314 VSF_SPI_DATASIZE_18 = (18ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
315 VSF_SPI_DATASIZE_19 = (19ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
316 VSF_SPI_DATASIZE_20 = (20ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
317 VSF_SPI_DATASIZE_21 = (21ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
318 VSF_SPI_DATASIZE_22 = (22ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
319 VSF_SPI_DATASIZE_23 = (23ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
320 VSF_SPI_DATASIZE_24 = (24ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
321 VSF_SPI_DATASIZE_25 = (25ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
322 VSF_SPI_DATASIZE_26 = (26ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
323 VSF_SPI_DATASIZE_27 = (27ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
324 VSF_SPI_DATASIZE_28 = (28ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
325 VSF_SPI_DATASIZE_29 = (29ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
326 VSF_SPI_DATASIZE_30 = (30ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
327 VSF_SPI_DATASIZE_31 = (31ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
328 VSF_SPI_DATASIZE_32 = (32ul - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET,
329 #define VSF_SPI_DATASIZE_BIT_OFFSET VSF_SPI_DATASIZE_BIT_OFFSET
330 #define VSF_SPI_DATASIZE_VALUE_OFFSET VSF_SPI_DATASIZE_VALUE_OFFSET
331 #define VSF_SPI_DATASIZE_4 VSF_SPI_DATASIZE_4
332 #define VSF_SPI_DATASIZE_5 VSF_SPI_DATASIZE_5
333 #define VSF_SPI_DATASIZE_6 VSF_SPI_DATASIZE_6
334 #define VSF_SPI_DATASIZE_7 VSF_SPI_DATASIZE_7
335 #define VSF_SPI_DATASIZE_8 VSF_SPI_DATASIZE_8
336 #define VSF_SPI_DATASIZE_9 VSF_SPI_DATASIZE_9
337 #define VSF_SPI_DATASIZE_10 VSF_SPI_DATASIZE_10
338 #define VSF_SPI_DATASIZE_11 VSF_SPI_DATASIZE_11
339 #define VSF_SPI_DATASIZE_12 VSF_SPI_DATASIZE_12
340 #define VSF_SPI_DATASIZE_13 VSF_SPI_DATASIZE_13
341 #define VSF_SPI_DATASIZE_14 VSF_SPI_DATASIZE_14
342 #define VSF_SPI_DATASIZE_15 VSF_SPI_DATASIZE_15
343 #define VSF_SPI_DATASIZE_16 VSF_SPI_DATASIZE_16
344 #define VSF_SPI_DATASIZE_17 VSF_SPI_DATASIZE_17
345 #define VSF_SPI_DATASIZE_18 VSF_SPI_DATASIZE_18
346 #define VSF_SPI_DATASIZE_19 VSF_SPI_DATASIZE_19
347 #define VSF_SPI_DATASIZE_20 VSF_SPI_DATASIZE_20
348 #define VSF_SPI_DATASIZE_21 VSF_SPI_DATASIZE_21
349 #define VSF_SPI_DATASIZE_22 VSF_SPI_DATASIZE_22
350 #define VSF_SPI_DATASIZE_23 VSF_SPI_DATASIZE_23
351 #define VSF_SPI_DATASIZE_24 VSF_SPI_DATASIZE_24
352 #define VSF_SPI_DATASIZE_25 VSF_SPI_DATASIZE_25
353 #define VSF_SPI_DATASIZE_26 VSF_SPI_DATASIZE_26
354 #define VSF_SPI_DATASIZE_27 VSF_SPI_DATASIZE_27
355 #define VSF_SPI_DATASIZE_28 VSF_SPI_DATASIZE_28
356 #define VSF_SPI_DATASIZE_29 VSF_SPI_DATASIZE_29
357 #define VSF_SPI_DATASIZE_30 VSF_SPI_DATASIZE_30
358 #define VSF_SPI_DATASIZE_31 VSF_SPI_DATASIZE_31
359 #define VSF_SPI_DATASIZE_32 VSF_SPI_DATASIZE_32
360 #define VSF_SPI_DATASIZE_MASK ( VSF_SPI_DATASIZE_4 \
361 | VSF_SPI_DATASIZE_5 \
362 | VSF_SPI_DATASIZE_6 \
363 | VSF_SPI_DATASIZE_7 \
364 | VSF_SPI_DATASIZE_8 \
365 | VSF_SPI_DATASIZE_9 \
366 | VSF_SPI_DATASIZE_10 \
367 | VSF_SPI_DATASIZE_11 \
368 | VSF_SPI_DATASIZE_12 \
369 | VSF_SPI_DATASIZE_13 \
370 | VSF_SPI_DATASIZE_14 \
371 | VSF_SPI_DATASIZE_15 \
372 | VSF_SPI_DATASIZE_16 \
373 | VSF_SPI_DATASIZE_17 \
374 | VSF_SPI_DATASIZE_18 \
375 | VSF_SPI_DATASIZE_19 \
376 | VSF_SPI_DATASIZE_20 \
377 | VSF_SPI_DATASIZE_21 \
378 | VSF_SPI_DATASIZE_22 \
379 | VSF_SPI_DATASIZE_23 \
380 | VSF_SPI_DATASIZE_24 \
381 | VSF_SPI_DATASIZE_25 \
382 | VSF_SPI_DATASIZE_26 \
383 | VSF_SPI_DATASIZE_27 \
384 | VSF_SPI_DATASIZE_28 \
385 | VSF_SPI_DATASIZE_29 \
386 | VSF_SPI_DATASIZE_30 \
387 | VSF_SPI_DATASIZE_31 \
388 | VSF_SPI_DATASIZE_32 )
389 */
390
391 /*
394 VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX = (0x00ul << 16), // 2 line, full-duplex, standard spi
395 VSF_SPI_DATALINE_2_LINE_RX_ONLY = (0x01ul << 16), // 2 line, but rx only
396 VSF_SPI_DATALINE_2_LINE_TX_ONLY = (0x02ul << 16), // 2 line, but tx only
397 VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX = (0x03ul << 16), // 1 line, half-duplex
398 VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX = (0x04ul << 16), // 2 line, half-duplex, dual spi
399 VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX = (0x05ul << 16), // 4 line, half-duplex, qual spi
400 VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX = (0x06ul << 16), // 8 line, half-duplex, octal spi
401 #define VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX
402 #define VSF_SPI_DATALINE_2_LINE_RX_ONLY VSF_SPI_DATALINE_2_LINE_RX_ONLY
403 #define VSF_SPI_DATALINE_2_LINE_TX_ONLY VSF_SPI_DATALINE_2_LINE_TX_ONLY
404 #define VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX
405 #define VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX
406 #define VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX
407 #define VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX
408 #define VSF_SPI_DATALINE_MASK ( VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX \
409 | VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX \
410 | VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX \
411 | VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX \
412 | VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX)
413 */
414
415 /*
418 VSF_SPI_MOTOROLA_MODE = (0x00ul << 20), //! \~english Motorola SPI: Standard 4-wire SPI protocol \~chinese 摩托罗拉 SPI：标准 4 线 SPI 协议
419 VSF_SPI_TI_MODE = (0x01ul << 20), //! \~english TI SSI: Chip select timing differs from Motorola SPI \~chinese TI SSI：片选时序与摩托罗拉 SPI 不同
420 #define VSF_SPI_MOTOROLA_MODE VSF_SPI_MOTOROLA_MODE
421 #define VSF_SPI_TI_MODE VSF_SPI_TI_MODE
422 #define VSF_SPI_MOTOROLA_TI_MASK (VSF_SPI_MOTOROLA_MODE | VSF_SPI_TI_MODE)
423 */
424
425 /*
427 // @brief Optional CRC calculation support for data integrity
428 // @note Hardware CRC calculation is platform-dependent
429 // @note When enabled, CRC is automatically calculated and verified
431 // @brief 可选的 CRC 数据完整性校验支持
432 // @note 硬件 CRC 计算依赖于平台
433 // @note 当使能时，CRC 将自动计算和验证
434 VSF_SPI_CRC_DISABLED = (0x00ul << 21), //! \~english CRC calculation disabled (no integrity check) \~chinese CRC 计算禁用（无完整性检查）
435 VSF_SPI_CRC_ENABLED = (0x01ul << 21), //! \~english CRC calculation enabled (hardware computes and verifies) \~chinese CRC 计算使能（硬件计算和验证）
436 #define VSF_SPI_CRC_DISABLED VSF_SPI_CRC_DISABLED
437 #define VSF_SPI_CRC_ENABLED VSF_SPI_CRC_ENABLED
438 #define VSF_SPI_CRC_MASK (VSF_SPI_CRC_DISABLED | VSF_SPI_CRC_ENABLED)
439 */
440
441 /*
444 VSF_SPI_CLOCK_PRESCALER_2 = (0x00ul << 22), //! \~english Divide system clock by 2 (highest frequency) \~chinese 系统时钟除以 2（最高频率）
445 VSF_SPI_CLOCK_PRESCALER_4 = (0x01ul << 22), //! \~english Divide system clock by 4 \~chinese 系统时钟除以 4
446 VSF_SPI_CLOCK_PRESCALER_8 = (0x02ul << 22), //! \~english Divide system clock by 8 \~chinese 系统时钟除以 8
447 VSF_SPI_CLOCK_PRESCALER_16 = (0x03ul << 22), //! \~english Divide system clock by 16 \~chinese 系统时钟除以 16
448 VSF_SPI_CLOCK_PRESCALER_32 = (0x04ul << 22), //! \~english Divide system clock by 32 \~chinese 系统时钟除以 32
449 VSF_SPI_CLOCK_PRESCALER_64 = (0x05ul << 22), //! \~english Divide system clock by 64 \~chinese 系统时钟除以 64
450 VSF_SPI_CLOCK_PRESCALER_128 = (0x06ul << 22), //! \~english Divide system clock by 128 \~chinese 系统时钟除以 128
451 VSF_SPI_CLOCK_PRESCALER_256 = (0x07ul << 22), //! \~english Divide system clock by 256 (lowest frequency) \~chinese 系统时钟除以 256（最低频率）
452 #define VSF_SPI_CLOCK_PRESCALER_2 VSF_SPI_CLOCK_PRESCALER_2
453 #define VSF_SPI_CLOCK_PRESCALER_4 VSF_SPI_CLOCK_PRESCALER_4
454 #define VSF_SPI_CLOCK_PRESCALER_8 VSF_SPI_CLOCK_PRESCALER_8
455 #define VSF_SPI_CLOCK_PRESCALER_16 VSF_SPI_CLOCK_PRESCALER_16
456 #define VSF_SPI_CLOCK_PRESCALER_32 VSF_SPI_CLOCK_PRESCALER_32
457 #define VSF_SPI_CLOCK_PRESCALER_64 VSF_SPI_CLOCK_PRESCALER_64
458 #define VSF_SPI_CLOCK_PRESCALER_128 VSF_SPI_CLOCK_PRESCALER_128
459 #define VSF_SPI_CLOCK_PRESCALER_256 VSF_SPI_CLOCK_PRESCALER_256
460 #define VSF_SPI_CLOCK_PRESCALER_MASK ( VSF_SPI_CLOCK_PRESCALER_2 \
461 | VSF_SPI_CLOCK_PRESCALER_4 \
462 | VSF_SPI_CLOCK_PRESCALER_8 \
463 | VSF_SPI_CLOCK_PRESCALER_16 \
464 | VSF_SPI_CLOCK_PRESCALER_32 \
465 | VSF_SPI_CLOCK_PRESCALER_64 \
466 | VSF_SPI_CLOCK_PRESCALER_128 \
467 | VSF_SPI_CLOCK_PRESCALER_256)
468 */
469} vsf_spi_mode_t;
470#endif
471
478enum {
487 VSF_SPI_DIR_MODE_MASK = VSF_SPI_MASTER
488 | VSF_SPI_SLAVE,
489
498 VSF_SPI_BIT_ORDER_MASK = VSF_SPI_MSB_FIRST
499 | VSF_SPI_LSB_FIRST,
500
509 VSF_SPI_MODE_MASK = VSF_SPI_MODE_0
510 | VSF_SPI_MODE_1
511 | VSF_SPI_MODE_2
512 | VSF_SPI_MODE_3,
513
518#ifndef VSF_SPI_CS_MODE_MASK
519 VSF_SPI_CS_MODE_MASK = VSF_SPI_CS_SOFTWARE_MODE
520 | VSF_SPI_CS_HARDWARE_MODE
525#ifdef VSF_SPI_CS_HARDWARE_INPUT_MODE
526 | VSF_SPI_CS_HARDWARE_INPUT_MODE
527#endif
528 ,
529#endif
530
535#ifndef VSF_SPI_DATASIZE_MASK
536 VSF_SPI_DATASIZE_MASK = VSF_SPI_DATASIZE_8
537 | VSF_SPI_DATASIZE_16
538 | VSF_SPI_DATASIZE_32,
539#endif
540
541#ifndef VSF_SPI_MODE_ALL_BITS_MASK
546 VSF_SPI_MODE_ALL_BITS_MASK = VSF_SPI_DIR_MODE_MASK
547 | VSF_SPI_BIT_ORDER_MASK
548 | VSF_SPI_MODE_MASK
549 | VSF_SPI_DIR_MODE_MASK
550 | VSF_SPI_CS_MODE_MASK
551 | VSF_SPI_DATASIZE_MASK
552#ifdef VSF_SPI_DATALINE_MASK
553 | VSF_SPI_DATALINE_MASK
554#endif
555#ifdef VSF_SPI_MOTOROLA_TI_MASK
556 | VSF_SPI_MOTOROLA_TI_MASK
557#endif
558#ifdef VSF_SPI_CRC_MASK
559 | VSF_SPI_CRC_MASK
560#endif
561#ifdef VSF_SPI_CLOCK_PRESCLER_MASK
562 | VSF_SPI_CLOCK_PRESCLER_MASK
563#endif
564#endif
565};
566
567#if VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK == DISABLED
579typedef enum vsf_spi_irq_mask_t {
580 VSF_SPI_IRQ_MASK_TX = 0x01ul << 0,
581 VSF_SPI_IRQ_MASK_RX = 0x01ul << 1,
582 VSF_SPI_IRQ_MASK_TX_CPL = 0x01ul << 2,
583 VSF_SPI_IRQ_MASK_CPL = 0x01ul << 3,
584 VSF_SPI_IRQ_MASK_OVERFLOW_ERR = 0x01ul << 4,
585} vsf_spi_irq_mask_t;
586#endif
587
592enum {
593 VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD = VSF_SPI_IRQ_MASK_TX,
594 VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD = VSF_SPI_IRQ_MASK_RX,
595
600 VSF_SPI_IRQ_MASK_RX_CPL = VSF_SPI_IRQ_MASK_CPL,
601
602#ifndef VSF_SPI_IRQ_MASK_ERR
607 VSF_SPI_IRQ_MASK_ERR = VSF_SPI_IRQ_MASK_OVERFLOW_ERR,
608#endif
609
610
611#ifndef VSF_SPI_IRQ_ALL_BITS_MASK
616 VSF_SPI_IRQ_ALL_BITS_MASK = VSF_SPI_IRQ_MASK_TX
617 | VSF_SPI_IRQ_MASK_RX
618 | VSF_SPI_IRQ_MASK_TX_CPL
619 | VSF_SPI_IRQ_MASK_CPL
620 | VSF_SPI_IRQ_MASK_ERR,
621#endif
622};
623
624#if VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS == DISABLED
635typedef struct vsf_spi_status_t {
636 union {
637 inherit(vsf_peripheral_status_t)
638 struct {
639 uint32_t is_busy : 1;
641 };
642 };
643} vsf_spi_status_t;
644#endif
645
646#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY == DISABLED
655typedef struct vsf_spi_capability_t {
656#if VSF_SPI_CFG_INHERIT_HAL_CAPABILITY == ENABLED
657 inherit(vsf_peripheral_capability_t)
658#endif
659 vsf_spi_irq_mask_t irq_mask;
660
661 uint8_t support_hardware_cs : 1;
662 uint8_t support_software_cs : 1;
663 uint8_t cs_count : 6;
664
665 uint32_t max_clock_hz;
666 uint32_t min_clock_hz;
667} vsf_spi_capability_t;
668#endif
669
670#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG == DISABLED
675typedef struct vsf_spi_t vsf_spi_t;
686typedef void vsf_spi_isr_handler_t(void *target_ptr,
687 vsf_spi_t *spi_ptr,
688 vsf_spi_irq_mask_t irq_mask);
696typedef struct vsf_spi_isr_t {
697 vsf_spi_isr_handler_t *handler_fn;
698 void *target_ptr;
699 vsf_arch_prio_t prio;
700} vsf_spi_isr_t;
701
708typedef struct vsf_spi_cfg_t {
709 vsf_spi_mode_t mode;
710 uint32_t clock_hz;
711 vsf_spi_isr_t isr;
712 uint8_t auto_cs_index;
713} vsf_spi_cfg_t;
714#endif
715
716
717#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL == DISABLED
738typedef enum vsf_spi_ctrl_t {
739 __VSF_SPI_CTRL_DUMMY = 0,
740
741 /*
744 VSF_SPI_CTRL_REQUEST_PAUSE = (0x1ul << 0), //! \~english Request to pause SPI transfer \~chinese 请求暂停 SPI 传输
745 VSF_SPI_CTRL_REQUEST_RESUME = (0x1ul << 1), //! \~english Request to resume SPI transfer \~chinese 请求恢复 SPI 传输
746 #define VSF_SPI_CTRL_REQUEST_PAUSE VSF_SPI_CTRL_REQUEST_PAUSE
747 #define VSF_SPI_CTRL_REQUEST_RESUME VSF_SPI_CTRL_REQUEST_RESUME
748 */
749
750 /*
765
770 VSF_SPI_CTRL_QSPI_ENABLE = 0x00ul,
775 VSF_SPI_CTRL_QSPI_DISABLE = 0x01ul,
776 #define VSF_SPI_CTRL_QSPI_ENABLE VSF_SPI_CTRL_QSPI_ENABLE
777 #define VSF_SPI_CTRL_QSPI_DISABLE VSF_SPI_CTRL_QSPI_DISABLE
778
793
796 VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE = 0x02ul,
799 VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE = 0x03ul,
802 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE = 0x04ul,
805 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE = 0x05ul,
812 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE = 0x06ul,
819 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE = 0x07ul,
822 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE = 0x08ul,
825 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE = 0x09ul,
826 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE
827 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE
828 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE
829 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE
830 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE
831 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE
832 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE
833 #define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE
834
843
846 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE = 0x0Aul,
849 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE = 0x0Bul,
852 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE = 0x0Cul,
855 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE = 0x0Dul,
862 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE = 0x0Eul,
863
868 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE = 0x0Ful,
871 VSF_SPI_CTRL_QSPI_ADDRESS_SET = 0x10ul,
874 VSF_SPI_CTRL_QSPI_ADDRESS_GET = 0x11ul,
875 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE
876 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE
877 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE
878 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE
879 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE
880 #define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE
881 #define VSF_SPI_CTRL_QSPI_ADDRESS_SET VSF_SPI_CTRL_QSPI_ADDRESS_SET
882 #define VSF_SPI_CTRL_QSPI_ADDRESS_GET VSF_SPI_CTRL_QSPI_ADDRESS_GET
883
892
895 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE = 0x18ul,
898 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE = 0x19ul,
901 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES = 0x1Aul,
904 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES = 0x1Bul,
905 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE
906 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE
907 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES
908 #define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES
909
922
925 VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE = 0x12ul,
928 VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE = 0x13ul,
931 VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE = 0x14ul,
934 VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE = 0x15ul,
935
942 VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE = 0x16ul,
943
950 VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE = 0x17ul,
951 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE
952 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE
953 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE
954 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE
955 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE
956 #define VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE
957
962 VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE = 0x1Cul,
965 VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE = 0x1Dul,
966 #define VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE
967 #define VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE
968 */
969} vsf_spi_ctrl_t;
970#endif
971
976typedef struct vsf_spi_op_t {
978# undef __VSF_HAL_TEMPLATE_API
979# define __VSF_HAL_TEMPLATE_API VSF_HAL_TEMPLATE_API_FP
981
982 VSF_SPI_APIS(vsf_spi)
983} vsf_spi_op_t;
984
985#if VSF_SPI_CFG_MULTI_CLASS == ENABLED
990struct vsf_spi_t {
991 const vsf_spi_op_t * op;
992};
993#endif
994
995/*============================ PROTOTYPES ====================================*/
996
1013extern vsf_err_t vsf_spi_init(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr);
1014
1027extern void vsf_spi_fini(vsf_spi_t *spi_ptr);
1028
1041extern fsm_rt_t vsf_spi_enable(vsf_spi_t *spi_ptr);
1042
1055extern fsm_rt_t vsf_spi_disable(vsf_spi_t *spi_ptr);
1056
1071extern void vsf_spi_irq_enable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1072
1085extern void vsf_spi_irq_disable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1086
1102extern vsf_err_t vsf_spi_cs_active(vsf_spi_t *spi_ptr, uint_fast8_t index);
1103
1119extern vsf_err_t vsf_spi_cs_inactive(vsf_spi_t *spi_ptr, uint_fast8_t index);
1120
1133extern vsf_spi_status_t vsf_spi_status(vsf_spi_t *spi_ptr);
1134
1147extern vsf_spi_capability_t vsf_spi_capability(vsf_spi_t *spi_ptr);
1148
1175extern void vsf_spi_fifo_transfer(vsf_spi_t *spi_ptr,
1176 void *out_buffer_ptr, uint_fast32_t* out_offset_ptr,
1177 void *in_buffer_ptr, uint_fast32_t* in_offset_ptr,
1178 uint_fast32_t count);
1179
1208extern vsf_err_t vsf_spi_request_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr,
1209 void *in_buffer_ptr, uint_fast32_t count);
1210
1223extern vsf_err_t vsf_spi_cancel_transfer(vsf_spi_t *spi_ptr);
1224
1241extern void vsf_spi_get_transferred_count(vsf_spi_t *spi_ptr, uint_fast32_t *sent_count, uint_fast32_t *received_count);
1242
1265extern vsf_err_t vsf_spi_ctrl(vsf_spi_t *spi_ptr, vsf_spi_ctrl_t ctrl, void *param);
1266
1267
1268/*============================ INLINE FUNCTIONS ==============================*/
1269
1270#if VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS == DISABLED
1285# if defined(VSF_SPI_DATASIZE_BIT_OFFSET) && defined(VSF_SPI_DATASIZE_VALUE_OFFSET)
1286static inline uint8_t vsf_spi_mode_to_data_bits(vsf_spi_mode_t mode)
1287{
1288 int bits = (mode & VSF_SPI_DATASIZE_MASK) >> VSF_SPI_DATASIZE_BIT_OFFSET;
1289 return bits + VSF_SPI_DATASIZE_VALUE_OFFSET;
1290}
1291# else
1292static inline uint8_t vsf_spi_mode_to_data_bits(vsf_spi_mode_t mode)
1293{
1294 uint32_t m = mode & VSF_SPI_DATASIZE_MASK;
1295 switch(m) {
1296#ifdef VSF_SPI_DATASIZE_4
1297 case VSF_SPI_DATASIZE_4:
1298 return 4;
1299#endif
1300#ifdef VSF_SPI_DATASIZE_5
1301 case VSF_SPI_DATASIZE_5:
1302 return 5;
1303#endif
1304#ifdef VSF_SPI_DATASIZE_6
1305 case VSF_SPI_DATASIZE_6:
1306 return 6;
1307#endif
1308#ifdef VSF_SPI_DATASIZE_7
1309 case VSF_SPI_DATASIZE_7:
1310 return 7;
1311#endif
1312 case VSF_SPI_DATASIZE_8:
1313 return 8;
1314#ifdef VSF_SPI_DATASIZE_9
1315 case VSF_SPI_DATASIZE_9:
1316 return 9;
1317#endif
1318#ifdef VSF_SPI_DATASIZE_10
1319 case VSF_SPI_DATASIZE_10:
1320 return 10;
1321#endif
1322#ifdef VSF_SPI_DATASIZE_11
1323 case VSF_SPI_DATASIZE_11:
1324 return 11;
1325#endif
1326#ifdef VSF_SPI_DATASIZE_12
1327 case VSF_SPI_DATASIZE_12:
1328 return 12;
1329#endif
1330#ifdef VSF_SPI_DATASIZE_13
1331 case VSF_SPI_DATASIZE_13:
1332 return 13;
1333#endif
1334#ifdef VSF_SPI_DATASIZE_14
1335 case VSF_SPI_DATASIZE_14:
1336 return 14;
1337#endif
1338#ifdef VSF_SPI_DATASIZE_15
1339 case VSF_SPI_DATASIZE_15:
1340 return 15;
1341#endif
1342#ifdef VSF_SPI_DATASIZE_16
1343 case VSF_SPI_DATASIZE_16:
1344 return 16;
1345#endif
1346#ifdef VSF_SPI_DATASIZE_17
1347 case VSF_SPI_DATASIZE_17:
1348 return 17;
1349#endif
1350#ifdef VSF_SPI_DATASIZE_18
1351 case VSF_SPI_DATASIZE_18:
1352 return 18;
1353#endif
1354#ifdef VSF_SPI_DATASIZE_19
1355 case VSF_SPI_DATASIZE_19:
1356 return 19;
1357#endif
1358#ifdef VSF_SPI_DATASIZE_20
1359 case VSF_SPI_DATASIZE_20:
1360 return 20;
1361#endif
1362#ifdef VSF_SPI_DATASIZE_21
1363 case VSF_SPI_DATASIZE_21:
1364 return 21;
1365#endif
1366#ifdef VSF_SPI_DATASIZE_22
1367 case VSF_SPI_DATASIZE_22:
1368 return 22;
1369#endif
1370#ifdef VSF_SPI_DATASIZE_23
1371 case VSF_SPI_DATASIZE_23:
1372 return 23;
1373#endif
1374#ifdef VSF_SPI_DATASIZE_24
1375 case VSF_SPI_DATASIZE_24:
1376 return 24;
1377#endif
1378#ifdef VSF_SPI_DATASIZE_25
1379 case VSF_SPI_DATASIZE_25:
1380 return 25;
1381#endif
1382#ifdef VSF_SPI_DATASIZE_26
1383 case VSF_SPI_DATASIZE_26:
1384 return 26;
1385#endif
1386#ifdef VSF_SPI_DATASIZE_27
1387 case VSF_SPI_DATASIZE_27:
1388 return 27;
1389#endif
1390#ifdef VSF_SPI_DATASIZE_28
1391 case VSF_SPI_DATASIZE_28:
1392 return 28;
1393#endif
1394#ifdef VSF_SPI_DATASIZE_29
1395 case VSF_SPI_DATASIZE_29:
1396 return 29;
1397#endif
1398#ifdef VSF_SPI_DATASIZE_30
1399 case VSF_SPI_DATASIZE_30:
1400 return 30;
1401#endif
1402#ifdef VSF_SPI_DATASIZE_31
1403 case VSF_SPI_DATASIZE_31:
1404 return 31;
1405#endif
1406#ifdef VSF_SPI_DATASIZE_32
1407 case VSF_SPI_DATASIZE_32:
1408 return 32;
1409#endif
1410 default:
1411 return 0;
1412 }
1413}
1414# endif
1415#endif
1416
1417#if VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE == DISABLED
1432# if defined(VSF_SPI_DATASIZE_BIT_OFFSET) && defined(VSF_SPI_DATASIZE_VALUE_OFFSET)
1433static inline vsf_spi_mode_t vsf_spi_data_bits_to_mode(uint8_t data_bits)
1434{
1435 return (vsf_spi_mode_t)((data_bits - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET);
1436}
1437# else
1438static inline vsf_spi_mode_t vsf_spi_data_bits_to_mode(uint8_t bit)
1439{
1440 switch (bit) {
1441#ifdef VSF_SPI_DATASIZE_4
1442 case 4:
1443 return VSF_SPI_DATASIZE_4;
1444#endif
1445#ifdef VSF_SPI_DATASIZE_5
1446 case 5:
1447 return VSF_SPI_DATASIZE_5;
1448#endif
1449#ifdef VSF_SPI_DATASIZE_6
1450 case 6:
1451 return VSF_SPI_DATASIZE_6;
1452#endif
1453#ifdef VSF_SPI_DATASIZE_7
1454 case 7:
1455 return VSF_SPI_DATASIZE_7;
1456#endif
1457 case 8:
1458 return VSF_SPI_DATASIZE_8;
1459#ifdef VSF_SPI_DATASIZE_9
1460 case 9:
1461 return VSF_SPI_DATASIZE_9;
1462#endif
1463#ifdef VSF_SPI_DATASIZE_10
1464 case 10:
1465 return VSF_SPI_DATASIZE_10;
1466#endif
1467#ifdef VSF_SPI_DATASIZE_11
1468 case 11:
1469 return VSF_SPI_DATASIZE_11;
1470#endif
1471#ifdef VSF_SPI_DATASIZE_12
1472 case 12:
1473 return VSF_SPI_DATASIZE_12;
1474#endif
1475#ifdef VSF_SPI_DATASIZE_13
1476 case 13:
1477 return VSF_SPI_DATASIZE_13;
1478#endif
1479#ifdef VSF_SPI_DATASIZE_14
1480 case 14:
1481 return VSF_SPI_DATASIZE_14;
1482#endif
1483#ifdef VSF_SPI_DATASIZE_15
1484 case 15:
1485 return VSF_SPI_DATASIZE_15;
1486#endif
1487#ifdef VSF_SPI_DATASIZE_16
1488 case 16:
1489 return VSF_SPI_DATASIZE_16;
1490#endif
1491#ifdef VSF_SPI_DATASIZE_17
1492 case 17:
1493 return VSF_SPI_DATASIZE_17;
1494#endif
1495#ifdef VSF_SPI_DATASIZE_18
1496 case 18:
1497 return VSF_SPI_DATASIZE_18;
1498#endif
1499#ifdef VSF_SPI_DATASIZE_19
1500 case 19:
1501 return VSF_SPI_DATASIZE_19;
1502#endif
1503#ifdef VSF_SPI_DATASIZE_20
1504 case 20:
1505 return VSF_SPI_DATASIZE_20;
1506#endif
1507#ifdef VSF_SPI_DATASIZE_21
1508 case 21:
1509 return VSF_SPI_DATASIZE_21;
1510#endif
1511#ifdef VSF_SPI_DATASIZE_22
1512 case 22:
1513 return VSF_SPI_DATASIZE_22;
1514#endif
1515#ifdef VSF_SPI_DATASIZE_23
1516 case 23:
1517 return VSF_SPI_DATASIZE_23;
1518#endif
1519#ifdef VSF_SPI_DATASIZE_24
1520 case 24:
1521 return VSF_SPI_DATASIZE_24;
1522#endif
1523#ifdef VSF_SPI_DATASIZE_25
1524 case 25:
1525 return VSF_SPI_DATASIZE_25;
1526#endif
1527#ifdef VSF_SPI_DATASIZE_26
1528 case 26:
1529 return VSF_SPI_DATASIZE_26;
1530#endif
1531#ifdef VSF_SPI_DATASIZE_27
1532 case 27:
1533 return VSF_SPI_DATASIZE_27;
1534#endif
1535#ifdef VSF_SPI_DATASIZE_28
1536 case 28:
1537 return VSF_SPI_DATASIZE_28;
1538#endif
1539#ifdef VSF_SPI_DATASIZE_29
1540 case 29:
1541 return VSF_SPI_DATASIZE_29;
1542#endif
1543#ifdef VSF_SPI_DATASIZE_30
1544 case 30:
1545 return VSF_SPI_DATASIZE_30;
1546#endif
1547#ifdef VSF_SPI_DATASIZE_31
1548 case 31:
1549 return VSF_SPI_DATASIZE_31;
1550#endif
1551#ifdef VSF_SPI_DATASIZE_32
1552 case 32:
1553 return VSF_SPI_DATASIZE_32;
1554#endif
1555 default:
1556 return (vsf_spi_mode_t)0;
1557 }
1558}
1559# endif
1560#endif
1561
1562#if VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES == DISABLED
1577static inline uint8_t vsf_spi_mode_to_data_bytes(vsf_spi_mode_t mode)
1578{
1579 int bits = (mode & VSF_SPI_DATASIZE_MASK);
1580 if (bits <= VSF_SPI_DATASIZE_8) {
1581 return 1;
1582 } else if (bits <= VSF_SPI_DATASIZE_16) {
1583 return 2;
1584 } else {
1585 return 4;
1586 }
1587}
1588#endif
1589
1590/*============================ MACROFIED FUNCTIONS ===========================*/
1591
1593#if VSF_SPI_CFG_FUNCTION_RENAME == ENABLED
1594# define __vsf_spi_t VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_t)
1595# define vsf_spi_init(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_init) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1596# define vsf_spi_fini(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_fini) ((__vsf_spi_t *)(__SPI))
1597# define vsf_spi_enable(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_enable) ((__vsf_spi_t *)(__SPI))
1598# define vsf_spi_disable(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_disable) ((__vsf_spi_t *)(__SPI))
1599# define vsf_spi_irq_enable(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_enable) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1600# define vsf_spi_irq_disable(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_disable) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1601# define vsf_spi_status(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_status) ((__vsf_spi_t *)(__SPI))
1602# define vsf_spi_capability(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_capability) ((__vsf_spi_t *)(__SPI))
1603# define vsf_spi_cs_active(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cs_active) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1604# define vsf_spi_cs_inactive(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cs_inactive) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1605# define vsf_spi_fifo_transfer(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_fifo_transfer) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1606# define vsf_spi_request_transfer(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_request_transfer) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1607# define vsf_spi_cancel_transfer(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cancel_transfer) ((__vsf_spi_t *)(__SPI))
1608# define vsf_spi_get_transferred_count(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_get_transferred_count)((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1609# define vsf_spi_ctrl(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_ctrl) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1610
1611# define vsf_qspi_t vsf_spi_t
1612# define vsf_qspi_mode_t vsf_spi_mode_t
1613# define vsf_qspi_irq_mask_t vsf_spi_irq_mask_t
1614# define vsf_qspi_status_t vsf_spi_status_t
1615# define vsf_qspi_capability_t vsf_spi_capability_t
1616# define vsf_qspi_isr_handler_t vsf_spi_isr_handler_t
1617# define vsf_qspi_isr_t vsf_spi_isr_t
1618# define vsf_qspi_cfg_t vsf_spi_cfg_t
1619# define vsf_qspi_ctrl_t vsf_spi_ctrl_t
1620
1635# define vsf_qspi_init(__SPI, __CFG_PTR) vsf_spi_init((__vsf_spi_t *)(__SPI), (__CFG_PTR))
1636
1649# define vsf_qspi_fini(__SPI) vsf_spi_fini((__vsf_spi_t *)(__SPI))
1650
1663# define vsf_qspi_enable(__SPI) vsf_spi_enable((__vsf_spi_t *)(__SPI))
1664
1677# define vsf_qspi_disable(__SPI) vsf_spi_disable((__vsf_spi_t *)(__SPI))
1678
1693# define vsf_qspi_irq_enable(__SPI, __IRQ_MASK) vsf_spi_irq_enable((__vsf_spi_t *)(__SPI), (__IRQ_MASK))
1694
1709# define vsf_qspi_irq_disable(__SPI, __IRQ_MASK) vsf_spi_irq_disable((__vsf_spi_t *)(__SPI), (__IRQ_MASK))
1710
1723# define vsf_qspi_status(__SPI) vsf_spi_status((__vsf_spi_t *)(__SPI))
1724
1737# define vsf_qspi_capability(__SPI) vsf_spi_capability((__vsf_spi_t *)(__SPI))
1738
1759# define vsf_qspi_fifo_write(__SPI, __OUT_BUFFER_PTR, __OUT_OFFSET_PTR, __COUNT) \
1760 vsf_spi_fifo_transfer((__vsf_spi_t *)(__SPI), (__OUT_BUFFER_PTR), (__OUT_OFFSET_PTR), NULL, NULL, (__COUNT))
1761
1782# define vsf_qspi_fifo_read(__SPI, __IN_BUFFER_PTR, __IN_OFFSET_PTR, __COUNT) \
1783 vsf_spi_fifo_transfer((__vsf_spi_t *)(__SPI), NULL, NULL, (__IN_BUFFER_PTR), (__IN_OFFSET_PTR), (__COUNT))
1784
1803# define vsf_qspi_request_tx(__SPI, __OUT_BUF, __CNT) vsf_spi_request_transfer((__vsf_spi_t *)(__SPI), (__OUT_BUF), NULL, (__CNT))
1804
1823# define vsf_qspi_request_rx(__SPI, __IN_BUF, __CNT) vsf_spi_request_transfer((__vsf_spi_t *)(__SPI), NULL, (__IN_BUF), (__CNT))
1824
1837# define vsf_qspi_cancel_transfer(__SPI) vsf_spi_cancel_transfer((__vsf_spi_t *)(__SPI))
1838
1855# define vsf_qspi_get_transferred_count(__SPI, __TX_CNT, __RX_CNT) \
1856 vsf_spi_get_transferred_count((__vsf_spi_t *)(__SPI), (__TX_CNT), (__RX_CNT))
1857
1874# define vsf_qspi_ctrl(__SPI, __CTRL, __PARAM) vsf_spi_ctrl((__vsf_spi_t *)(__SPI), (__CTRL), (__PARAM))
1875#endif
1877
1878#ifdef __cplusplus
1879}
1880#endif
1881
1882#endif /*__VSF_TEMPLATE_SPI_H__*/
1883
vsf_err_t
vsf_err_t
Definition __type.h:42
vsf_spi_mode_t
vsf_spi_mode_t
Definition spi.h:33
VSF_SPI_DATASIZE_31
@ VSF_SPI_DATASIZE_31
Definition spi.h:67
VSF_SPI_DATASIZE_28
@ VSF_SPI_DATASIZE_28
Definition spi.h:64
VSF_SPI_DATASIZE_6
@ VSF_SPI_DATASIZE_6
Definition spi.h:98
VSF_SPI_DATASIZE_17
@ VSF_SPI_DATASIZE_17
Definition spi.h:53
VSF_SPI_DATASIZE_9
@ VSF_SPI_DATASIZE_9
Definition spi.h:45
VSF_SPI_DATASIZE_18
@ VSF_SPI_DATASIZE_18
Definition spi.h:54
VSF_SPI_DATASIZE_11
@ VSF_SPI_DATASIZE_11
Definition spi.h:47
VSF_SPI_DATASIZE_20
@ VSF_SPI_DATASIZE_20
Definition spi.h:56
VSF_SPI_DATASIZE_21
@ VSF_SPI_DATASIZE_21
Definition spi.h:57
VSF_SPI_DATASIZE_27
@ VSF_SPI_DATASIZE_27
Definition spi.h:63
VSF_SPI_DATASIZE_14
@ VSF_SPI_DATASIZE_14
Definition spi.h:50
VSF_SPI_DATASIZE_BIT_OFFSET
@ VSF_SPI_DATASIZE_BIT_OFFSET
Definition spi.h:42
VSF_SPI_DATASIZE_26
@ VSF_SPI_DATASIZE_26
Definition spi.h:62
VSF_SPI_DATASIZE_13
@ VSF_SPI_DATASIZE_13
Definition spi.h:49
VSF_SPI_DATASIZE_7
@ VSF_SPI_DATASIZE_7
Definition spi.h:99
VSF_SPI_DATASIZE_5
@ VSF_SPI_DATASIZE_5
Definition spi.h:97
VSF_SPI_DATASIZE_12
@ VSF_SPI_DATASIZE_12
Definition spi.h:48
VSF_SPI_DATASIZE_22
@ VSF_SPI_DATASIZE_22
Definition spi.h:58
VSF_SPI_DATASIZE_24
@ VSF_SPI_DATASIZE_24
Definition spi.h:60
VSF_SPI_DATASIZE_4
@ VSF_SPI_DATASIZE_4
datasize is 8 bits
Definition spi.h:96
VSF_SPI_DATASIZE_29
@ VSF_SPI_DATASIZE_29
Definition spi.h:65
VSF_SPI_DATASIZE_25
@ VSF_SPI_DATASIZE_25
Definition spi.h:61
VSF_SPI_DATASIZE_30
@ VSF_SPI_DATASIZE_30
Definition spi.h:66
VSF_SPI_DATASIZE_19
@ VSF_SPI_DATASIZE_19
Definition spi.h:55
VSF_SPI_DATASIZE_23
@ VSF_SPI_DATASIZE_23
Definition spi.h:59
VSF_SPI_DATASIZE_10
@ VSF_SPI_DATASIZE_10
Definition spi.h:46
VSF_SPI_DATASIZE_15
@ VSF_SPI_DATASIZE_15
Definition spi.h:51
vsf_arch_prio_t
vsf_arch_prio_t
Definition cortex_a_generic.h:88
irq_mask
const i_spi_t vsf_spi_irq_mask_t irq_mask
Definition spi_interface.h:38
uint_fast8_t
unsigned char uint_fast8_t
Definition stdint.h:23
uint32_t
unsigned uint32_t
Definition stdint.h:9
uint_fast32_t
unsigned int uint_fast32_t
Definition stdint.h:27
uint8_t
unsigned char uint8_t
Definition stdint.h:5
vsf_peripheral_capability_t
Definition vsf_template_hal_driver.h:203
vsf_peripheral_status_t
Definition vsf_template_hal_driver.h:196
vsf_spi_capability_t
Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware...
Definition vsf_template_spi.h:655
vsf_spi_capability_t::support_software_cs
uint8_t support_software_cs
Hardware chip select support (1: supported, 0: not supported)
Definition vsf_template_spi.h:662
vsf_spi_capability_t::max_clock_hz
uint32_t max_clock_hz
Number of available chip select lines (0-63)
Definition vsf_template_spi.h:665
vsf_spi_capability_t::cs_count
uint8_t cs_count
Software chip select support (1: supported, 0: not supported)
Definition vsf_template_spi.h:663
vsf_spi_capability_t::irq_mask
vsf_spi_irq_mask_t irq_mask
Definition spi.h:165
vsf_spi_capability_t::support_hardware_cs
uint8_t support_hardware_cs
Supported interrupt masks for SPI operations.
Definition vsf_template_spi.h:661
vsf_spi_capability_t::min_clock_hz
uint32_t min_clock_hz
Maximum supported SPI clock frequency in Hz.
Definition vsf_template_spi.h:666
vsf_spi_capability_t::inherit
inherit(vsf_peripheral_capability_t) vsf_spi_irq_mask_t irq_mask
Inherit peripheral capabilities.
vsf_spi_cfg_t
Configuration structure for SPI.
Definition vsf_template_spi.h:708
vsf_spi_cfg_t::clock_hz
uint32_t clock_hz
SPI operating mode (master/slave, CPOL/CPHA, bit order, data size)
Definition vsf_template_spi.h:710
vsf_spi_cfg_t::isr
vsf_spi_isr_t isr
SPI clock frequency in Hz (must be between min_clock_hz and max_clock_hz)
Definition vsf_template_spi.h:711
vsf_spi_cfg_t::mode
vsf_spi_mode_t mode
Definition vsf_template_spi.h:709
vsf_spi_cfg_t::auto_cs_index
uint8_t auto_cs_index
Interrupt configuration (handler, target pointer, priority)
Definition vsf_template_spi.h:712
vsf_spi_isr_t
SPI interrupt service routine configuration structure.
Definition vsf_template_spi.h:696
vsf_spi_isr_t::handler_fn
vsf_spi_isr_handler_t * handler_fn
Definition vsf_template_spi.h:697
vsf_spi_isr_t::target_ptr
void * target_ptr
Interrupt handler function (NULL to disable interrupts)
Definition vsf_template_spi.h:698
vsf_spi_isr_t::prio
vsf_arch_prio_t prio
User context pointer passed to handler.
Definition vsf_template_spi.h:699
vsf_spi_op_t
SPI operation function pointer type, used for SPI Multi Class support.
Definition vsf_template_spi.h:976
vsf_spi_status_t
Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doe...
Definition vsf_template_spi.h:635
vsf_spi_status_t::is_busy
uint32_t is_busy
Definition spi.h:155
vsf_spi_t
SPI instance structure, used for SPI Multi Class support, not needed in non Multi Class mode.
Definition vsf_template_spi.h:990
vsf_spi_t::op
const vsf_spi_op_t * op
Definition vsf_template_spi.h:991
vsf_spi_isr_handler_t
void vsf_spi_isr_handler_t(void *target_ptr, vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Definition spi.h:181
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Definition spi.h:140
vsf_spi_mode_t
vsf_spi_mode_t
Definition spi.h:116
vsf_arch.h
fsm_rt_t
fsm_rt_t
Definition vsf_fsm.h:315
vsf_spi
vsf_spi_t vsf_spi[SPI_COUNT]
Definition vsf_spi.c:3
vsf_template_hal_driver.h
vsf_spi_fifo_transfer
void vsf_spi_fifo_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr, uint_fast32_t *out_offset_ptr, void *in_buffer_ptr, uint_fast32_t *in_offset_ptr, uint_fast32_t count)
Perform FIFO-based data transfer on a SPI instance.
Definition spi_common.c:118
VSF_SPI_IRQ_MASK_RX_CPL
@ VSF_SPI_IRQ_MASK_RX_CPL
VSF_SPI_IRQ_MASK_RX 的别名
Definition vsf_template_spi.h:600
VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD
@ VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD
Definition vsf_template_spi.h:593
VSF_SPI_IRQ_ALL_BITS_MASK
@ VSF_SPI_IRQ_ALL_BITS_MASK
Definition vsf_template_spi.h:616
VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD
@ VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD
VSF_SPI_IRQ_MASK_TX 的别名
Definition vsf_template_spi.h:594
VSF_SPI_IRQ_MASK_ERR
@ VSF_SPI_IRQ_MASK_ERR
Definition vsf_template_spi.h:607
vsf_spi_isr_t
struct vsf_spi_isr_t vsf_spi_isr_t
SPI interrupt service routine configuration structure.
vsf_spi_isr_handler_t
void vsf_spi_isr_handler_t(void *target_ptr, vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
SPI interrupt handler type declaration.
Definition vsf_template_spi.h:686
vsf_spi_status
vsf_spi_status_t vsf_spi_status(vsf_spi_t *spi_ptr)
Get the current status of a SPI instance.
Definition spi_common.c:91
vsf_spi_request_transfer
vsf_err_t vsf_spi_request_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr, void *in_buffer_ptr, uint_fast32_t count)
Request a SPI data transfer operation.
Definition spi_common.c:130
vsf_spi_cfg_t
struct vsf_spi_cfg_t vsf_spi_cfg_t
Configuration structure for SPI.
vsf_spi_capability_t
struct vsf_spi_capability_t vsf_spi_capability_t
Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware...
VSF_SPI_APIS
#define VSF_SPI_APIS(__prefix_name)
SPI API template, used to generate SPI type, specific prefix function declarations,...
Definition vsf_template_spi.h:236
VSF_SPI_MODE_MASK
@ VSF_SPI_MODE_MASK
SPI mode mask for clock polarity and phase configuration.
Definition vsf_template_spi.h:509
VSF_SPI_BIT_ORDER_MASK
@ VSF_SPI_BIT_ORDER_MASK
SPI bit order mask for MSB/LSB first selection.
Definition vsf_template_spi.h:498
VSF_SPI_DIR_MODE_MASK
@ VSF_SPI_DIR_MODE_MASK
SPI direction mode mask for master/slave selection.
Definition vsf_template_spi.h:487
VSF_SPI_CS_MODE_MASK
@ VSF_SPI_CS_MODE_MASK
Definition vsf_template_spi.h:519
VSF_SPI_MODE_ALL_BITS_MASK
@ VSF_SPI_MODE_ALL_BITS_MASK
Definition vsf_template_spi.h:546
VSF_SPI_DATASIZE_MASK
@ VSF_SPI_DATASIZE_MASK
Definition vsf_template_spi.h:536
vsf_spi_get_transferred_count
void vsf_spi_get_transferred_count(vsf_spi_t *spi_ptr, uint_fast32_t *sent_count, uint_fast32_t *received_count)
Get the number of data units transferred in the current or last SPI operation.
Definition spi_common.c:150
vsf_spi_cs_active
vsf_err_t vsf_spi_cs_active(vsf_spi_t *spi_ptr, uint_fast8_t index)
Activate (assert) a SPI chip select line.
Definition spi_common.c:100
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Predefined VSF SPI interrupt masks that can be reimplemented in specific HAL drivers....
Definition vsf_template_spi.h:579
VSF_SPI_IRQ_MASK_OVERFLOW_ERR
@ VSF_SPI_IRQ_MASK_OVERFLOW_ERR
Transfer complete interrupt (triggers when both TX and RX are complete)
Definition vsf_template_spi.h:584
VSF_SPI_IRQ_MASK_CPL
@ VSF_SPI_IRQ_MASK_CPL
TX complete interrupt (triggers when all TX data has been sent)
Definition vsf_template_spi.h:583
VSF_SPI_IRQ_MASK_RX
@ VSF_SPI_IRQ_MASK_RX
TX FIFO threshold interrupt (triggers when TX FIFO level is below threshold)
Definition vsf_template_spi.h:581
VSF_SPI_IRQ_MASK_TX
@ VSF_SPI_IRQ_MASK_TX
Definition vsf_template_spi.h:580
VSF_SPI_IRQ_MASK_TX_CPL
@ VSF_SPI_IRQ_MASK_TX_CPL
RX FIFO threshold interrupt (triggers when RX FIFO level is above threshold)
Definition vsf_template_spi.h:582
vsf_spi_ctrl
vsf_err_t vsf_spi_ctrl(vsf_spi_t *spi_ptr, vsf_spi_ctrl_t ctrl, void *param)
Execute a control command on the SPI instance.
Definition spi_common.c:169
vsf_spi_enable
fsm_rt_t vsf_spi_enable(vsf_spi_t *spi_ptr)
Enable a SPI instance for operation.
Definition spi_common.c:55
vsf_spi_disable
fsm_rt_t vsf_spi_disable(vsf_spi_t *spi_ptr)
Disable a SPI instance from operation.
Definition spi_common.c:64
vsf_spi_status_t
struct vsf_spi_status_t vsf_spi_status_t
Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doe...
vsf_spi_mode_t
vsf_spi_mode_t
Predefined VSF SPI modes that can be reimplemented in specific HAL drivers.If we want to add optional...
Definition vsf_template_spi.h:273
VSF_SPI_CPHA_LOW
@ VSF_SPI_CPHA_LOW
Clock polarity: idle state is high.
Definition vsf_template_spi.h:281
VSF_SPI_SLAVE
@ VSF_SPI_SLAVE
Master mode (controller)
Definition vsf_template_spi.h:275
VSF_SPI_DATASIZE_16
@ VSF_SPI_DATASIZE_16
8-bit data transfer size
Definition vsf_template_spi.h:293
VSF_SPI_LSB_FIRST
@ VSF_SPI_LSB_FIRST
Most Significant Bit (MSB) first.
Definition vsf_template_spi.h:277
VSF_SPI_CPOL_HIGH
@ VSF_SPI_CPOL_HIGH
Clock polarity: idle state is low.
Definition vsf_template_spi.h:280
VSF_SPI_MODE_1
@ VSF_SPI_MODE_1
Mode 0: CPOL=0 (idle low), CPHA=0 (sample on first edge)
Definition vsf_template_spi.h:285
VSF_SPI_DATASIZE_8
@ VSF_SPI_DATASIZE_8
Hardware controlled chip select.
Definition vsf_template_spi.h:292
VSF_SPI_MASTER
@ VSF_SPI_MASTER
Definition vsf_template_spi.h:274
VSF_SPI_CPHA_HIGH
@ VSF_SPI_CPHA_HIGH
Clock phase: sample on first edge.
Definition vsf_template_spi.h:282
VSF_SPI_MSB_FIRST
@ VSF_SPI_MSB_FIRST
Slave mode (peripheral)
Definition vsf_template_spi.h:276
VSF_SPI_DATASIZE_32
@ VSF_SPI_DATASIZE_32
16-bit data transfer size
Definition vsf_template_spi.h:294
VSF_SPI_CS_SOFTWARE_MODE
@ VSF_SPI_CS_SOFTWARE_MODE
Mode 3: CPOL=1 (idle high), CPHA=1 (sample on second edge)
Definition vsf_template_spi.h:289
VSF_SPI_MODE_0
@ VSF_SPI_MODE_0
Clock phase: sample on second edge.
Definition vsf_template_spi.h:284
VSF_SPI_CS_HARDWARE_MODE
@ VSF_SPI_CS_HARDWARE_MODE
Software controlled chip select.
Definition vsf_template_spi.h:290
VSF_SPI_MODE_3
@ VSF_SPI_MODE_3
Mode 2: CPOL=1 (idle high), CPHA=0 (sample on first edge)
Definition vsf_template_spi.h:287
VSF_SPI_CPOL_LOW
@ VSF_SPI_CPOL_LOW
Least Significant Bit (LSB) first.
Definition vsf_template_spi.h:279
VSF_SPI_MODE_2
@ VSF_SPI_MODE_2
Mode 1: CPOL=0 (idle low), CPHA=1 (sample on second edge)
Definition vsf_template_spi.h:286
vsf_spi_irq_disable
void vsf_spi_irq_disable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Disable specific interrupts for a SPI instance.
Definition spi_common.c:82
vsf_spi_ctrl_t
vsf_spi_ctrl_t
Predefined VSF SPI control commands that can be reimplemented in specific HAL drivers.
Definition vsf_template_spi.h:738
__VSF_SPI_CTRL_DUMMY
@ __VSF_SPI_CTRL_DUMMY
Definition vsf_template_spi.h:739
vsf_spi_init
vsf_err_t vsf_spi_init(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr)
Initialize a SPI instance.
Definition spi_common.c:37
vsf_spi_irq_enable
void vsf_spi_irq_enable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Enable specific interrupts for a SPI instance.
Definition spi_common.c:73
vsf_spi_fini
void vsf_spi_fini(vsf_spi_t *spi_ptr)
Finalize (deinitialize) a SPI instance.
Definition spi_common.c:46
vsf_spi_cs_inactive
vsf_err_t vsf_spi_cs_inactive(vsf_spi_t *spi_ptr, uint_fast8_t index)
Deactivate (deassert) a SPI chip select line.
Definition spi_common.c:109
vsf_spi_cancel_transfer
vsf_err_t vsf_spi_cancel_transfer(vsf_spi_t *spi_ptr)
Cancel an ongoing SPI transfer operation.
Definition spi_common.c:141
vsf_spi_capability
vsf_spi_capability_t vsf_spi_capability(vsf_spi_t *spi_ptr)
Get the capabilities of a SPI instance.
Definition spi_common.c:160
Generated from commit: vsfteam/vsf@3f519a5