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vsf_template_spi.h
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1/*****************************************************************************
2 * Copyright(C)2009-2022 by VSF Team *
3 * *
4 * Licensed under the Apache License, Version 2.0 (the "License"); *
5 * you may not use this file except in compliance with the License. *
6 * You may obtain a copy of the License at *
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9 * *
10 * Unless required by applicable law or agreed to in writing, software *
11 * distributed under the License is distributed on an "AS IS" BASIS, *
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
13 * See the License for the specific language governing permissions and *
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17
18#ifndef __VSF_TEMPLATE_SPI_H__
19#define __VSF_TEMPLATE_SPI_H__
20
21/*============================ INCLUDES ======================================*/
22
23#include "./vsf_template_hal_driver.h"
24#include "hal/arch/vsf_arch.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/*============================ MACROS ========================================*/
31
39#ifndef VSF_SPI_CFG_MULTI_CLASS
40# define VSF_SPI_CFG_MULTI_CLASS ENABLED
41#endif
42
50#if defined(VSF_HW_SPI_COUNT) && !defined(VSF_HW_SPI_MASK)
51# define VSF_HW_SPI_MASK VSF_HAL_COUNT_TO_MASK(VSF_HW_SPI_COUNT)
52#endif
53
61#if defined(VSF_HW_SPI_MASK) && !defined(VSF_HW_SPI_COUNT)
62# define VSF_HW_SPI_COUNT VSF_HAL_MASK_TO_COUNT(VSF_HW_SPI_MASK)
63#endif
64
73#ifndef VSF_SPI_CFG_PREFIX
74# if VSF_SPI_CFG_MULTI_CLASS == ENABLED
75# define VSF_SPI_CFG_PREFIX vsf
76# elif defined(VSF_HW_SPI_COUNT) && (VSF_HW_SPI_COUNT != 0)
77# define VSF_SPI_CFG_PREFIX vsf_hw
78# else
79# define VSF_SPI_CFG_PREFIX vsf
80# endif
81#endif
82
91#ifndef VSF_SPI_CFG_FUNCTION_RENAME
92# define VSF_SPI_CFG_FUNCTION_RENAME ENABLED
93#endif
94
103#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE
104# define VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE DISABLED
105#endif
106
116#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK
117# define VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK DISABLED
118#endif
119
129#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS
130# define VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS DISABLED
131#endif
132
145#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG
146# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG DISABLED
147#endif
148
158#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL
159# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL DISABLED
160#endif
161
172#ifndef VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY
173# define VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY DISABLED
174#endif
175
185#ifndef VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS
186# define VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS DISABLED
187#endif
188
198#ifndef VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE
199# define VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE DISABLED
200#endif
201
211#ifndef VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES
212# define VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES DISABLED
213#endif
214
224#ifndef VSF_SPI_CFG_INHERIT_HAL_CAPABILITY
225# define VSF_SPI_CFG_INHERIT_HAL_CAPABILITY ENABLED
226#endif
227
259#ifndef __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
260# define __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL DISABLED
261#endif
262
263/*============================ MACROFIED FUNCTIONS ===========================*/
264
273#define VSF_SPI_APIS(__prefix_name) \
274 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, init, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_cfg_t *cfg_ptr) \
275 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, fini, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
276 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, get_configuration, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_cfg_t *cfg_ptr) \
277 __VSF_HAL_TEMPLATE_API(__prefix_name, fsm_rt_t, spi, enable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
278 __VSF_HAL_TEMPLATE_API(__prefix_name, fsm_rt_t, spi, disable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
279 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, irq_enable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
280 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, irq_disable, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
281 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_irq_mask_t, spi, irq_clear, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_irq_mask_t irq_mask) \
282 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_status_t, spi, status, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
283 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_spi_capability_t, spi, capability, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
284 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cs_active, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast8_t index) \
285 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cs_inactive, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast8_t index) \
286 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, fifo_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, void *out_buffer_ptr, uint_fast32_t *out_offset_ptr, void *in_buffer_ptr, uint_fast32_t *in_offset_ptr, uint_fast32_t cnt) \
287 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, request_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, void *out_buffer_ptr, void *in_buffer_ptr, uint_fast32_t count) \
288 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, cancel_transfer, VSF_MCONNECT(__prefix_name, _t) *spi_ptr) \
289 __VSF_HAL_TEMPLATE_API(__prefix_name, void, spi, get_transferred_count, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, uint_fast32_t * sent_count, uint_fast32_t *received_count) \
290 __VSF_HAL_TEMPLATE_API(__prefix_name, vsf_err_t, spi, ctrl, VSF_MCONNECT(__prefix_name, _t) *spi_ptr, vsf_spi_ctrl_t ctrl, void* param)
291
292
293/*============================ TYPES =========================================*/
294
295#if VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE == DISABLED
359typedef enum vsf_spi_mode_t {
360 // Direction control (bit 0)
361 VSF_SPI_MASTER = 0x00ul << 0,
362 VSF_SPI_SLAVE = 0x01ul << 0,
363
364 // Bit order control (bit 1)
365 VSF_SPI_MSB_FIRST = 0x00ul << 1,
366 VSF_SPI_LSB_FIRST = 0x01ul << 1,
367
368 // SPI mode (bits 2-3: CPOL and CPHA)
369 VSF_SPI_MODE_0 = 0x00ul << 2,
370 VSF_SPI_MODE_1 = 0x01ul << 2,
371 VSF_SPI_MODE_2 = 0x02ul << 2,
372 VSF_SPI_MODE_3 = 0x03ul << 2,
373
374 // Chip select control (bit 4)
375 // \~english Software controlled chip select. The user must manually call vsf_spi_cs_active() and vsf_spi_cs_inactive() to control the CS line.
376 // \~chinese 软件控制片选。用户必须手动调用 vsf_spi_cs_active() 和 vsf_spi_cs_inactive() 来控制片选线。
377 VSF_SPI_CS_SOFTWARE_MODE = 0x00ul << 4,
378 // \~english Hardware controlled chip select. The hardware automatically controls the CS line specified by `auto_cs_index` during a transfer.
379 // \~chinese 硬件控制片选。硬件在传输期间自动控制由 `auto_cs_index` 指定的片选线。
380 VSF_SPI_CS_HARDWARE_MODE = 0x01ul << 4,
381
382 // Data size control (bits 8-15)
383 // \~english Buffer size requirements: 4-8 bits = 1 byte, 9-16 bits = 2 bytes, 17-32 bits = 4 bytes
384 // \~chinese 缓冲区大小要求：4-8 位 = 1 字节，9-16 位 = 2 字节，17-32 位 = 4 字节
385 VSF_SPI_DATASIZE_8 = 0x00ul << 8,
386 VSF_SPI_DATASIZE_16 = 0x01ul << 8,
387 VSF_SPI_DATASIZE_32 = 0x02ul << 8,
388
397#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
398 // Clock polarity control (bit 2)
399 VSF_SPI_CPOL_LOW = 0x00ul << 2,
400# define VSF_SPI_CPOL_LOW VSF_SPI_CPOL_LOW
401 VSF_SPI_CPOL_HIGH = 0x01ul << 2,
402# define VSF_SPI_CPOL_HIGH VSF_SPI_CPOL_HIGH
403
404 // Clock phase control (bit 3)
405 VSF_SPI_CPHA_LOW = 0x00ul << 3,
406# define VSF_SPI_CPHA_LOW VSF_SPI_CPHA_LOW
407 VSF_SPI_CPHA_HIGH = 0x01ul << 3,
408# define VSF_SPI_CPHA_HIGH VSF_SPI_CPHA_HIGH
409#endif
410
419#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
422 VSF_SPI_MOTOROLA_MODE = (0x00ul << 20),
423# define VSF_SPI_MOTOROLA_MODE VSF_SPI_MOTOROLA_MODE
424 VSF_SPI_TI_MODE = (0x01ul << 20),
425# define VSF_SPI_TI_MODE VSF_SPI_TI_MODE
426# define VSF_SPI_MOTOROLA_TI_MASK (VSF_SPI_MOTOROLA_MODE | VSF_SPI_TI_MODE)
427#endif
428
437#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
439 // @brief Optional CRC calculation support for data integrity
440 // @note Hardware CRC calculation is platform-dependent
441 // @note When enabled, CRC is automatically calculated and verified
443 // @brief 可选的 CRC 数据完整性校验支持
444 // @note 硬件 CRC 计算依赖于平台
445 // @note 当使能时，CRC 将自动计算和验证
446 VSF_SPI_CRC_DISABLED = (0x00ul << 21),
447# define VSF_SPI_CRC_DISABLED VSF_SPI_CRC_DISABLED
448 VSF_SPI_CRC_ENABLED = (0x01ul << 21),
449# define VSF_SPI_CRC_ENABLED VSF_SPI_CRC_ENABLED
450# define VSF_SPI_CRC_MASK (VSF_SPI_CRC_DISABLED | VSF_SPI_CRC_ENABLED)
451#endif
452
461#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
464 VSF_SPI_CLOCK_PRESCALER_2 = (0x00ul << 22),
465# define VSF_SPI_CLOCK_PRESCALER_2 VSF_SPI_CLOCK_PRESCALER_2
466 VSF_SPI_CLOCK_PRESCALER_4 = (0x01ul << 22),
467# define VSF_SPI_CLOCK_PRESCALER_4 VSF_SPI_CLOCK_PRESCALER_4
468 VSF_SPI_CLOCK_PRESCALER_8 = (0x02ul << 22),
469# define VSF_SPI_CLOCK_PRESCALER_8 VSF_SPI_CLOCK_PRESCALER_8
470 VSF_SPI_CLOCK_PRESCALER_16 = (0x03ul << 22),
471# define VSF_SPI_CLOCK_PRESCALER_16 VSF_SPI_CLOCK_PRESCALER_16
472 VSF_SPI_CLOCK_PRESCALER_32 = (0x04ul << 22),
473# define VSF_SPI_CLOCK_PRESCALER_32 VSF_SPI_CLOCK_PRESCALER_32
474 VSF_SPI_CLOCK_PRESCALER_64 = (0x05ul << 22),
475# define VSF_SPI_CLOCK_PRESCALER_64 VSF_SPI_CLOCK_PRESCALER_64
476 VSF_SPI_CLOCK_PRESCALER_128 = (0x06ul << 22),
477# define VSF_SPI_CLOCK_PRESCALER_128 VSF_SPI_CLOCK_PRESCALER_128
478 VSF_SPI_CLOCK_PRESCALER_256 = (0x07ul << 22),
479# define VSF_SPI_CLOCK_PRESCALER_256 VSF_SPI_CLOCK_PRESCALER_256
480# define VSF_SPI_CLOCK_PRESCALER_MASK ( VSF_SPI_CLOCK_PRESCALER_2 \
481 | VSF_SPI_CLOCK_PRESCALER_4 \
482 | VSF_SPI_CLOCK_PRESCALER_8 \
483 | VSF_SPI_CLOCK_PRESCALER_16 \
484 | VSF_SPI_CLOCK_PRESCALER_32 \
485 | VSF_SPI_CLOCK_PRESCALER_64 \
486 | VSF_SPI_CLOCK_PRESCALER_128 \
487 | VSF_SPI_CLOCK_PRESCALER_256)
488#endif
489
498#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
501 VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX = (0x00ul << 16), // MOSI+MISO, full-duplex, standard spi
502# define VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX
503 VSF_SPI_DATALINE_2_LINE_RX_ONLY = (0x01ul << 16), // MOSI+MISO, but rx only (MISO)
504# define VSF_SPI_DATALINE_2_LINE_RX_ONLY VSF_SPI_DATALINE_2_LINE_RX_ONLY
505 VSF_SPI_DATALINE_2_LINE_TX_ONLY = (0x02ul << 16), // MOSI+MISO, but tx only (MOSI)
506# define VSF_SPI_DATALINE_2_LINE_TX_ONLY VSF_SPI_DATALINE_2_LINE_TX_ONLY
507 VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX = (0x03ul << 16), // 1 line (MOSI or MISO), half-duplex
508# define VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX
509 VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX = (0x04ul << 16), // 2 line (MOSI+MISO), half-duplex, dual spi
510# define VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX
511 VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX = (0x05ul << 16), // 4 line (IO0+IO1+IO2+IO3), half-duplex, quad spi
512# define VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX
513 VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX = (0x06ul << 16), // 8 line (IO0+IO1+IO2+IO3+IO4+IO5+IO6+IO7), half-duplex, octal spi
514# define VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX
515 VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX = (0x07ul << 16), // 16 line (IO0+IO1+IO2+IO3+IO4+IO5+IO6+IO7+IO8+IO9+IO10+IO11+IO12+IO13+IO14+IO15), half-duplex, hexadeca spi
516# define VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX
517# define VSF_SPI_DATALINE_MASK ( VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX \
518 | VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX \
519 | VSF_SPI_DATALINE_2_LINE_HALF_DUPLEX \
520 | VSF_SPI_DATALINE_4_LINE_HALF_DUPLEX \
521 | VSF_SPI_DATALINE_8_LINE_HALF_DUPLEX \
522 | VSF_SPI_DATALINE_16_LINE_HALF_DUPLEX)
523#endif
524} vsf_spi_mode_t;
525#endif
526
533enum {
542 VSF_SPI_DIR_MODE_MASK = VSF_SPI_MASTER
543 | VSF_SPI_SLAVE,
544
553 VSF_SPI_BIT_ORDER_MASK = VSF_SPI_MSB_FIRST
554 | VSF_SPI_LSB_FIRST,
555
564 VSF_SPI_MODE_MASK = VSF_SPI_MODE_0
565 | VSF_SPI_MODE_1
566 | VSF_SPI_MODE_2
567 | VSF_SPI_MODE_3,
568
573#ifndef VSF_SPI_CS_MODE_MASK
574 VSF_SPI_CS_MODE_MASK = VSF_SPI_CS_SOFTWARE_MODE
575 | VSF_SPI_CS_HARDWARE_MODE
580#ifdef VSF_SPI_CS_HARDWARE_INPUT_MODE
581 | VSF_SPI_CS_HARDWARE_INPUT_MODE
582#endif
583 ,
584#endif
585
590#ifndef VSF_SPI_DATASIZE_MASK
591 VSF_SPI_DATASIZE_MASK = VSF_SPI_DATASIZE_8
592 | VSF_SPI_DATASIZE_16
593 | VSF_SPI_DATASIZE_32,
594#endif
595
596#ifndef VSF_SPI_MODE_ALL_BITS_MASK
601 VSF_SPI_MODE_ALL_BITS_MASK = VSF_SPI_DIR_MODE_MASK
602 | VSF_SPI_BIT_ORDER_MASK
603 | VSF_SPI_MODE_MASK
604 | VSF_SPI_CS_MODE_MASK
605 | VSF_SPI_DATASIZE_MASK
606#ifdef VSF_SPI_DATALINE_MASK
607 | VSF_SPI_DATALINE_MASK
608#endif
609#ifdef VSF_SPI_MOTOROLA_TI_MASK
610 | VSF_SPI_MOTOROLA_TI_MASK
611#endif
612#ifdef VSF_SPI_CRC_MASK
613 | VSF_SPI_CRC_MASK
614#endif
615#ifdef VSF_SPI_CLOCK_PRESCALER_MASK
616 | VSF_SPI_CLOCK_PRESCALER_MASK
617#endif
618#endif
619};
620
621#if VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK == DISABLED
633typedef enum vsf_spi_irq_mask_t {
634 VSF_SPI_IRQ_MASK_TX = 0x01ul << 0,
635 VSF_SPI_IRQ_MASK_RX = 0x01ul << 1,
636 VSF_SPI_IRQ_MASK_TX_CPL = 0x01ul << 2,
637 VSF_SPI_IRQ_MASK_RX_CPL = 0x01ul << 3,
638 VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR = 0x01ul << 4,
639
653 // VSF_SPI_IRQ_MASK_CRC_ERR = 0x01ul << 5, //! \~english CRC error interrupt \~chinese CRC 错误中断
654
668 // VSF_SPI_IRQ_MASK_FRAME_ERR = 0x01ul << 6, //! \~english Frame error interrupt \~chinese 帧错误中断
669} vsf_spi_irq_mask_t;
670#endif
671
676enum {
677 VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD = VSF_SPI_IRQ_MASK_TX,
678 VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD = VSF_SPI_IRQ_MASK_RX,
679
684 VSF_SPI_IRQ_MASK_CPL = VSF_SPI_IRQ_MASK_RX_CPL,
685
686#ifndef VSF_SPI_IRQ_MASK_ERR
691 VSF_SPI_IRQ_MASK_ERR = VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR,
692#endif
693
694
695#ifndef VSF_SPI_IRQ_ALL_BITS_MASK
700 VSF_SPI_IRQ_ALL_BITS_MASK = VSF_SPI_IRQ_MASK_TX
701 | VSF_SPI_IRQ_MASK_RX
702 | VSF_SPI_IRQ_MASK_TX_CPL
703 | VSF_SPI_IRQ_MASK_RX_CPL
704 | VSF_SPI_IRQ_MASK_ERR,
705#endif
706};
707
708#if VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS == DISABLED
719typedef struct vsf_spi_status_t {
720 union {
721 inherit(vsf_peripheral_status_t)
722 struct {
723 uint32_t is_busy : 1;
725 };
726 };
727} vsf_spi_status_t;
728#endif
729
730#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY == DISABLED
739typedef struct vsf_spi_capability_t {
740#if VSF_SPI_CFG_INHERIT_HAL_CAPABILITY == ENABLED
741 inherit(vsf_peripheral_capability_t)
742#endif
743 vsf_spi_irq_mask_t irq_mask;
744
745 uint8_t support_hardware_cs : 1;
746 uint8_t support_software_cs : 1;
747 uint8_t cs_count : 6;
748
749 uint32_t max_clock_hz;
750 uint32_t min_clock_hz;
751} vsf_spi_capability_t;
752#endif
753
754#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG == DISABLED
761typedef struct vsf_spi_t vsf_spi_t;
774typedef void vsf_spi_isr_handler_t(void *target_ptr,
775 vsf_spi_t *spi_ptr,
776 vsf_spi_irq_mask_t irq_mask);
785typedef struct vsf_spi_isr_t {
786 vsf_spi_isr_handler_t *handler_fn;
787 void *target_ptr;
788 vsf_arch_prio_t prio;
789} vsf_spi_isr_t;
790
797typedef struct vsf_spi_cfg_t {
798 vsf_spi_mode_t mode;
799 uint32_t clock_hz;
800 vsf_spi_isr_t isr;
801 // \~english In hardware chip select mode (`VSF_SPI_CS_HARDWARE_MODE`), this specifies the hardware CS pin index (0 to cs_count-1) to be used for automatic chip select.
802 // \~chinese 在硬件片选模式 (`VSF_SPI_CS_HARDWARE_MODE`) 下，此成员指定用于自动片选的硬件 CS 引脚索引（0 到 cs_count-1）。在软件模式下，此成员被忽略。
803 uint8_t auto_cs_index;
804} vsf_spi_cfg_t;
805#endif
806
807
808#if VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL == DISABLED
842typedef enum vsf_spi_ctrl_t {
860 __VSF_SPI_CTRL_DUMMY = 0,
861
870#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
873 VSF_SPI_CTRL_REQUEST_PAUSE = (0x1ul << 0),
874 VSF_SPI_CTRL_REQUEST_RESUME = (0x1ul << 1),
875# define VSF_SPI_CTRL_REQUEST_PAUSE VSF_SPI_CTRL_REQUEST_PAUSE
876# define VSF_SPI_CTRL_REQUEST_RESUME VSF_SPI_CTRL_REQUEST_RESUME
877#endif
878
887#if __VSF_SPI_CFG_SUPPORT_STANDARD_OPTIONAL
902
907 VSF_SPI_CTRL_QSPI_ENABLE = 0x00ul,
912 VSF_SPI_CTRL_QSPI_DISABLE = 0x01ul,
913# define VSF_SPI_CTRL_QSPI_ENABLE VSF_SPI_CTRL_QSPI_ENABLE
914# define VSF_SPI_CTRL_QSPI_DISABLE VSF_SPI_CTRL_QSPI_DISABLE
915
930
933 VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE = 0x02ul,
936 VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE = 0x03ul,
939 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE = 0x04ul,
942 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE = 0x05ul,
949 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE = 0x06ul,
956 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE = 0x07ul,
959 VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE = 0x08ul,
962 VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE = 0x09ul,
963# define VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE VSF_SPI_CTRL_QSPI_CMD_PHASE_ENABLE
964# define VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE VSF_SPI_CTRL_QSPI_CMD_PHASE_DISABLE
965# define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_SIZE
966# define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_SIZE
967# define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_LINE_MODE
968# define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_LINE_MODE
969# define VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE VSF_SPI_CTRL_QSPI_CMD_PHASE_SET_VALUE
970# define VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE VSF_SPI_CTRL_QSPI_CMD_PHASE_GET_VALUE
971
980
983 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE = 0x0Aul,
986 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE = 0x0Bul,
989 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE = 0x0Cul,
992 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE = 0x0Dul,
999 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE = 0x0Eul,
1000
1005 VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE = 0x0Ful,
1008 VSF_SPI_CTRL_QSPI_ADDRESS_SET = 0x10ul,
1011 VSF_SPI_CTRL_QSPI_ADDRESS_GET = 0x11ul,
1012# define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_ENABLE
1013# define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_DISABLE
1014# define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_SIZE
1015# define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_SIZE
1016# define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_SET_LINE_MODE
1017# define VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_ADDRESS_PHASE_GET_LINE_MODE
1018# define VSF_SPI_CTRL_QSPI_ADDRESS_SET VSF_SPI_CTRL_QSPI_ADDRESS_SET
1019# define VSF_SPI_CTRL_QSPI_ADDRESS_GET VSF_SPI_CTRL_QSPI_ADDRESS_GET
1020
1029
1032 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE = 0x18ul,
1035 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE = 0x19ul,
1038 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES = 0x1Aul,
1041 VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES = 0x1Bul,
1042# define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE VSF_SPI_CTRL_QSPI_DUMMY_PHASE_ENABLE
1043# define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE VSF_SPI_CTRL_QSPI_DUMMY_PHASE_DISABLE
1044# define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES VSF_SPI_CTRL_QSPI_DUMMY_PHASE_SET_CYCLES
1045# define VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES VSF_SPI_CTRL_QSPI_DUMMY_PHASE_GET_CYCLES
1046
1059
1062 VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE = 0x12ul,
1065 VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE = 0x13ul,
1068 VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE = 0x14ul,
1071 VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE = 0x15ul,
1072
1079 VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE = 0x16ul,
1080
1087 VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE = 0x17ul,
1088# define VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE VSF_SPI_CTRL_QSPI_DATA_PHASE_ENABLE
1089# define VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE VSF_SPI_CTRL_QSPI_DATA_PHASE_DISABLE
1090# define VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_SIZE
1091# define VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_SIZE
1092# define VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE VSF_SPI_CTRL_QSPI_DATA_PHASE_SET_LINE_MODE
1093# define VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE VSF_SPI_CTRL_QSPI_DATA_PHASE_GET_LINE_MODE
1094
1099 VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE = 0x1Cul,
1102 VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE = 0x1Dul,
1103# define VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE VSF_SPI_CTRL_QSPI_TRANSFER_SET_MODE
1104# define VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE VSF_SPI_CTRL_QSPI_TRANSFER_GET_MODE
1105#endif
1106} vsf_spi_ctrl_t;
1107#endif
1108
1115typedef struct vsf_spi_op_t {
1117# undef __VSF_HAL_TEMPLATE_API
1118# define __VSF_HAL_TEMPLATE_API VSF_HAL_TEMPLATE_API_FP
1120
1121 VSF_SPI_APIS(vsf_spi)
1122} vsf_spi_op_t;
1123
1124#if VSF_SPI_CFG_MULTI_CLASS == ENABLED
1131struct vsf_spi_t {
1132 const vsf_spi_op_t * op;
1133};
1134#endif
1135
1136/*============================ PROTOTYPES ====================================*/
1137
1154extern vsf_err_t vsf_spi_init(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr);
1155
1168extern void vsf_spi_fini(vsf_spi_t *spi_ptr);
1169
1187extern vsf_err_t vsf_spi_get_configuration(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr);
1188
1201extern fsm_rt_t vsf_spi_enable(vsf_spi_t *spi_ptr);
1202
1215extern fsm_rt_t vsf_spi_disable(vsf_spi_t *spi_ptr);
1216
1231extern void vsf_spi_irq_enable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1232
1245extern void vsf_spi_irq_disable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1246
1272extern vsf_spi_irq_mask_t vsf_spi_irq_clear(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask);
1273
1289extern vsf_err_t vsf_spi_cs_active(vsf_spi_t *spi_ptr, uint_fast8_t index);
1290
1306extern vsf_err_t vsf_spi_cs_inactive(vsf_spi_t *spi_ptr, uint_fast8_t index);
1307
1320extern vsf_spi_status_t vsf_spi_status(vsf_spi_t *spi_ptr);
1321
1334extern vsf_spi_capability_t vsf_spi_capability(vsf_spi_t *spi_ptr);
1335
1387extern void vsf_spi_fifo_transfer(vsf_spi_t *spi_ptr,
1388 void *out_buffer_ptr, uint_fast32_t* out_offset_ptr,
1389 void *in_buffer_ptr, uint_fast32_t* in_offset_ptr,
1390 uint_fast32_t count);
1391
1429extern vsf_err_t vsf_spi_request_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr,
1430 void *in_buffer_ptr, uint_fast32_t count);
1431
1444extern vsf_err_t vsf_spi_cancel_transfer(vsf_spi_t *spi_ptr);
1445
1464extern void vsf_spi_get_transferred_count(vsf_spi_t *spi_ptr, uint_fast32_t *sent_count, uint_fast32_t *received_count);
1465
1488extern vsf_err_t vsf_spi_ctrl(vsf_spi_t *spi_ptr, vsf_spi_ctrl_t ctrl, void *param);
1489
1490
1491/*============================ INLINE FUNCTIONS ==============================*/
1492
1493#if VSF_SPI_CFG_REIMPLEMENT_MODE_TO_DATA_BITS == DISABLED
1508# if defined(VSF_SPI_DATASIZE_BIT_OFFSET) && defined(VSF_SPI_DATASIZE_VALUE_OFFSET)
1509static inline uint8_t vsf_spi_mode_to_data_bits(vsf_spi_mode_t mode)
1510{
1511 int bits = (mode & VSF_SPI_DATASIZE_MASK) >> VSF_SPI_DATASIZE_BIT_OFFSET;
1512 return bits + VSF_SPI_DATASIZE_VALUE_OFFSET;
1513}
1514# else
1515static inline uint8_t vsf_spi_mode_to_data_bits(vsf_spi_mode_t mode)
1516{
1517 uint32_t m = mode & VSF_SPI_DATASIZE_MASK;
1518 switch(m) {
1519#ifdef VSF_SPI_DATASIZE_4
1520 case VSF_SPI_DATASIZE_4:
1521 return 4;
1522#endif
1523#ifdef VSF_SPI_DATASIZE_5
1524 case VSF_SPI_DATASIZE_5:
1525 return 5;
1526#endif
1527#ifdef VSF_SPI_DATASIZE_6
1528 case VSF_SPI_DATASIZE_6:
1529 return 6;
1530#endif
1531#ifdef VSF_SPI_DATASIZE_7
1532 case VSF_SPI_DATASIZE_7:
1533 return 7;
1534#endif
1535 case VSF_SPI_DATASIZE_8:
1536 return 8;
1537#ifdef VSF_SPI_DATASIZE_9
1538 case VSF_SPI_DATASIZE_9:
1539 return 9;
1540#endif
1541#ifdef VSF_SPI_DATASIZE_10
1542 case VSF_SPI_DATASIZE_10:
1543 return 10;
1544#endif
1545#ifdef VSF_SPI_DATASIZE_11
1546 case VSF_SPI_DATASIZE_11:
1547 return 11;
1548#endif
1549#ifdef VSF_SPI_DATASIZE_12
1550 case VSF_SPI_DATASIZE_12:
1551 return 12;
1552#endif
1553#ifdef VSF_SPI_DATASIZE_13
1554 case VSF_SPI_DATASIZE_13:
1555 return 13;
1556#endif
1557#ifdef VSF_SPI_DATASIZE_14
1558 case VSF_SPI_DATASIZE_14:
1559 return 14;
1560#endif
1561#ifdef VSF_SPI_DATASIZE_15
1562 case VSF_SPI_DATASIZE_15:
1563 return 15;
1564#endif
1565#ifdef VSF_SPI_DATASIZE_16
1566 case VSF_SPI_DATASIZE_16:
1567 return 16;
1568#endif
1569#ifdef VSF_SPI_DATASIZE_17
1570 case VSF_SPI_DATASIZE_17:
1571 return 17;
1572#endif
1573#ifdef VSF_SPI_DATASIZE_18
1574 case VSF_SPI_DATASIZE_18:
1575 return 18;
1576#endif
1577#ifdef VSF_SPI_DATASIZE_19
1578 case VSF_SPI_DATASIZE_19:
1579 return 19;
1580#endif
1581#ifdef VSF_SPI_DATASIZE_20
1582 case VSF_SPI_DATASIZE_20:
1583 return 20;
1584#endif
1585#ifdef VSF_SPI_DATASIZE_21
1586 case VSF_SPI_DATASIZE_21:
1587 return 21;
1588#endif
1589#ifdef VSF_SPI_DATASIZE_22
1590 case VSF_SPI_DATASIZE_22:
1591 return 22;
1592#endif
1593#ifdef VSF_SPI_DATASIZE_23
1594 case VSF_SPI_DATASIZE_23:
1595 return 23;
1596#endif
1597#ifdef VSF_SPI_DATASIZE_24
1598 case VSF_SPI_DATASIZE_24:
1599 return 24;
1600#endif
1601#ifdef VSF_SPI_DATASIZE_25
1602 case VSF_SPI_DATASIZE_25:
1603 return 25;
1604#endif
1605#ifdef VSF_SPI_DATASIZE_26
1606 case VSF_SPI_DATASIZE_26:
1607 return 26;
1608#endif
1609#ifdef VSF_SPI_DATASIZE_27
1610 case VSF_SPI_DATASIZE_27:
1611 return 27;
1612#endif
1613#ifdef VSF_SPI_DATASIZE_28
1614 case VSF_SPI_DATASIZE_28:
1615 return 28;
1616#endif
1617#ifdef VSF_SPI_DATASIZE_29
1618 case VSF_SPI_DATASIZE_29:
1619 return 29;
1620#endif
1621#ifdef VSF_SPI_DATASIZE_30
1622 case VSF_SPI_DATASIZE_30:
1623 return 30;
1624#endif
1625#ifdef VSF_SPI_DATASIZE_31
1626 case VSF_SPI_DATASIZE_31:
1627 return 31;
1628#endif
1629#ifdef VSF_SPI_DATASIZE_32
1630 case VSF_SPI_DATASIZE_32:
1631 return 32;
1632#endif
1633 default:
1634 return 0;
1635 }
1636}
1637# endif
1638#endif
1639
1640#if VSF_SPI_CFG_REIMPLEMENT_DATA_BITS_TO_MODE == DISABLED
1655# if defined(VSF_SPI_DATASIZE_BIT_OFFSET) && defined(VSF_SPI_DATASIZE_VALUE_OFFSET)
1656static inline vsf_spi_mode_t vsf_spi_data_bits_to_mode(uint8_t data_bits)
1657{
1658 return (vsf_spi_mode_t)((data_bits - VSF_SPI_DATASIZE_VALUE_OFFSET) << VSF_SPI_DATASIZE_BIT_OFFSET);
1659}
1660# else
1661static inline vsf_spi_mode_t vsf_spi_data_bits_to_mode(uint8_t data_bits)
1662{
1663 switch (data_bits) {
1664#ifdef VSF_SPI_DATASIZE_4
1665 case 4:
1666 return VSF_SPI_DATASIZE_4;
1667#endif
1668#ifdef VSF_SPI_DATASIZE_5
1669 case 5:
1670 return VSF_SPI_DATASIZE_5;
1671#endif
1672#ifdef VSF_SPI_DATASIZE_6
1673 case 6:
1674 return VSF_SPI_DATASIZE_6;
1675#endif
1676#ifdef VSF_SPI_DATASIZE_7
1677 case 7:
1678 return VSF_SPI_DATASIZE_7;
1679#endif
1680 case 8:
1681 return VSF_SPI_DATASIZE_8;
1682#ifdef VSF_SPI_DATASIZE_9
1683 case 9:
1684 return VSF_SPI_DATASIZE_9;
1685#endif
1686#ifdef VSF_SPI_DATASIZE_10
1687 case 10:
1688 return VSF_SPI_DATASIZE_10;
1689#endif
1690#ifdef VSF_SPI_DATASIZE_11
1691 case 11:
1692 return VSF_SPI_DATASIZE_11;
1693#endif
1694#ifdef VSF_SPI_DATASIZE_12
1695 case 12:
1696 return VSF_SPI_DATASIZE_12;
1697#endif
1698#ifdef VSF_SPI_DATASIZE_13
1699 case 13:
1700 return VSF_SPI_DATASIZE_13;
1701#endif
1702#ifdef VSF_SPI_DATASIZE_14
1703 case 14:
1704 return VSF_SPI_DATASIZE_14;
1705#endif
1706#ifdef VSF_SPI_DATASIZE_15
1707 case 15:
1708 return VSF_SPI_DATASIZE_15;
1709#endif
1710#ifdef VSF_SPI_DATASIZE_16
1711 case 16:
1712 return VSF_SPI_DATASIZE_16;
1713#endif
1714#ifdef VSF_SPI_DATASIZE_17
1715 case 17:
1716 return VSF_SPI_DATASIZE_17;
1717#endif
1718#ifdef VSF_SPI_DATASIZE_18
1719 case 18:
1720 return VSF_SPI_DATASIZE_18;
1721#endif
1722#ifdef VSF_SPI_DATASIZE_19
1723 case 19:
1724 return VSF_SPI_DATASIZE_19;
1725#endif
1726#ifdef VSF_SPI_DATASIZE_20
1727 case 20:
1728 return VSF_SPI_DATASIZE_20;
1729#endif
1730#ifdef VSF_SPI_DATASIZE_21
1731 case 21:
1732 return VSF_SPI_DATASIZE_21;
1733#endif
1734#ifdef VSF_SPI_DATASIZE_22
1735 case 22:
1736 return VSF_SPI_DATASIZE_22;
1737#endif
1738#ifdef VSF_SPI_DATASIZE_23
1739 case 23:
1740 return VSF_SPI_DATASIZE_23;
1741#endif
1742#ifdef VSF_SPI_DATASIZE_24
1743 case 24:
1744 return VSF_SPI_DATASIZE_24;
1745#endif
1746#ifdef VSF_SPI_DATASIZE_25
1747 case 25:
1748 return VSF_SPI_DATASIZE_25;
1749#endif
1750#ifdef VSF_SPI_DATASIZE_26
1751 case 26:
1752 return VSF_SPI_DATASIZE_26;
1753#endif
1754#ifdef VSF_SPI_DATASIZE_27
1755 case 27:
1756 return VSF_SPI_DATASIZE_27;
1757#endif
1758#ifdef VSF_SPI_DATASIZE_28
1759 case 28:
1760 return VSF_SPI_DATASIZE_28;
1761#endif
1762#ifdef VSF_SPI_DATASIZE_29
1763 case 29:
1764 return VSF_SPI_DATASIZE_29;
1765#endif
1766#ifdef VSF_SPI_DATASIZE_30
1767 case 30:
1768 return VSF_SPI_DATASIZE_30;
1769#endif
1770#ifdef VSF_SPI_DATASIZE_31
1771 case 31:
1772 return VSF_SPI_DATASIZE_31;
1773#endif
1774#ifdef VSF_SPI_DATASIZE_32
1775 case 32:
1776 return VSF_SPI_DATASIZE_32;
1777#endif
1778 default:
1779 return (vsf_spi_mode_t)0;
1780 }
1781}
1782# endif
1783#endif
1784
1785#if VSF_SPI_CFG_REIMPLEMENT_MODE_TO_BYTES == DISABLED
1800static inline uint8_t vsf_spi_mode_to_data_bytes(vsf_spi_mode_t mode)
1801{
1802 uint8_t bits = vsf_spi_mode_to_data_bits(mode);
1803 if (bits == 0) {
1804 return 0; // Error: invalid data bits
1805 } else if (bits <= 8) {
1806 return 1;
1807 } else if (bits <= 16) {
1808 return 2;
1809 } else {
1810 return 4;
1811 }
1812}
1813#endif
1814
1815/*============================ MACROFIED FUNCTIONS ===========================*/
1816
1818#if VSF_SPI_CFG_FUNCTION_RENAME == ENABLED
1819# define __vsf_spi_t VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_t)
1820# define vsf_spi_init(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_init) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1821# define vsf_spi_fini(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_fini) ((__vsf_spi_t *)(__SPI))
1822# define vsf_spi_get_configuration(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_get_configuration) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1823# define vsf_spi_enable(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_enable) ((__vsf_spi_t *)(__SPI))
1824# define vsf_spi_disable(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_disable) ((__vsf_spi_t *)(__SPI))
1825# define vsf_spi_irq_enable(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_enable) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1826# define vsf_spi_irq_disable(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_disable) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1827# define vsf_spi_irq_clear(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_irq_clear) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1828# define vsf_spi_status(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_status) ((__vsf_spi_t *)(__SPI))
1829# define vsf_spi_capability(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_capability) ((__vsf_spi_t *)(__SPI))
1830# define vsf_spi_cs_active(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cs_active) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1831# define vsf_spi_cs_inactive(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cs_inactive) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1832# define vsf_spi_fifo_transfer(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_fifo_transfer) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1833# define vsf_spi_request_transfer(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_request_transfer) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1834# define vsf_spi_cancel_transfer(__SPI) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_cancel_transfer) ((__vsf_spi_t *)(__SPI))
1835# define vsf_spi_get_transferred_count(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_get_transferred_count)((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1836# define vsf_spi_ctrl(__SPI, ...) VSF_MCONNECT(VSF_SPI_CFG_PREFIX, _spi_ctrl) ((__vsf_spi_t *)(__SPI), ##__VA_ARGS__)
1837
1838# define vsf_qspi_t vsf_spi_t
1839# define vsf_qspi_mode_t vsf_spi_mode_t
1840# define vsf_qspi_irq_mask_t vsf_spi_irq_mask_t
1841# define vsf_qspi_status_t vsf_spi_status_t
1842# define vsf_qspi_capability_t vsf_spi_capability_t
1843# define vsf_qspi_isr_handler_t vsf_spi_isr_handler_t
1844# define vsf_qspi_isr_t vsf_spi_isr_t
1845# define vsf_qspi_cfg_t vsf_spi_cfg_t
1846# define vsf_qspi_ctrl_t vsf_spi_ctrl_t
1847
1862# define vsf_qspi_init(__SPI, __CFG_PTR) vsf_spi_init((__vsf_spi_t *)(__SPI), (__CFG_PTR))
1863
1876# define vsf_qspi_fini(__SPI) vsf_spi_fini((__vsf_spi_t *)(__SPI))
1877
1890# define vsf_qspi_enable(__SPI) vsf_spi_enable((__vsf_spi_t *)(__SPI))
1891
1904# define vsf_qspi_disable(__SPI) vsf_spi_disable((__vsf_spi_t *)(__SPI))
1905
1920# define vsf_qspi_irq_enable(__SPI, __IRQ_MASK) vsf_spi_irq_enable((__vsf_spi_t *)(__SPI), (__IRQ_MASK))
1921
1936# define vsf_qspi_irq_disable(__SPI, __IRQ_MASK) vsf_spi_irq_disable((__vsf_spi_t *)(__SPI), (__IRQ_MASK))
1937
1950# define vsf_qspi_status(__SPI) vsf_spi_status((__vsf_spi_t *)(__SPI))
1951
1964# define vsf_qspi_capability(__SPI) vsf_spi_capability((__vsf_spi_t *)(__SPI))
1965
1986# define vsf_qspi_fifo_write(__SPI, __OUT_BUFFER_PTR, __OUT_OFFSET_PTR, __COUNT) \
1987 vsf_spi_fifo_transfer((__vsf_spi_t *)(__SPI), (__OUT_BUFFER_PTR), (__OUT_OFFSET_PTR), NULL, NULL, (__COUNT))
1988
2009# define vsf_qspi_fifo_read(__SPI, __IN_BUFFER_PTR, __IN_OFFSET_PTR, __COUNT) \
2010 vsf_spi_fifo_transfer((__vsf_spi_t *)(__SPI), NULL, NULL, (__IN_BUFFER_PTR), (__IN_OFFSET_PTR), (__COUNT))
2011
2030# define vsf_qspi_request_tx(__SPI, __OUT_BUF, __CNT) vsf_spi_request_transfer((__vsf_spi_t *)(__SPI), (__OUT_BUF), NULL, (__CNT))
2031
2050# define vsf_qspi_request_rx(__SPI, __IN_BUF, __CNT) vsf_spi_request_transfer((__vsf_spi_t *)(__SPI), NULL, (__IN_BUF), (__CNT))
2051
2075# define vsf_qspi_cancel_transfer(__SPI) vsf_spi_cancel_transfer((__vsf_spi_t *)(__SPI))
2076
2093# define vsf_qspi_get_transferred_count(__SPI, __TX_CNT, __RX_CNT) \
2094 vsf_spi_get_transferred_count((__vsf_spi_t *)(__SPI), (__TX_CNT), (__RX_CNT))
2095
2112# define vsf_qspi_ctrl(__SPI, __CTRL, __PARAM) vsf_spi_ctrl((__vsf_spi_t *)(__SPI), (__CTRL), (__PARAM))
2113#endif
2115
2116#ifdef __cplusplus
2117}
2118#endif
2119
2120#endif /*__VSF_TEMPLATE_SPI_H__*/
2121
vsf_err_t
vsf_err_t
Definition __type.h:42
vsf_spi_mode_t
vsf_spi_mode_t
Definition spi.h:33
VSF_SPI_DATASIZE_31
@ VSF_SPI_DATASIZE_31
Definition spi.h:72
VSF_SPI_DATASIZE_28
@ VSF_SPI_DATASIZE_28
Definition spi.h:69
VSF_SPI_DATASIZE_6
@ VSF_SPI_DATASIZE_6
Definition spi.h:103
VSF_SPI_DATASIZE_17
@ VSF_SPI_DATASIZE_17
Definition spi.h:58
VSF_SPI_DATASIZE_9
@ VSF_SPI_DATASIZE_9
Definition spi.h:50
VSF_SPI_DATASIZE_18
@ VSF_SPI_DATASIZE_18
Definition spi.h:59
VSF_SPI_DATASIZE_11
@ VSF_SPI_DATASIZE_11
Definition spi.h:52
VSF_SPI_DATASIZE_20
@ VSF_SPI_DATASIZE_20
Definition spi.h:61
VSF_SPI_DATASIZE_21
@ VSF_SPI_DATASIZE_21
Definition spi.h:62
VSF_SPI_DATASIZE_27
@ VSF_SPI_DATASIZE_27
Definition spi.h:68
VSF_SPI_DATASIZE_14
@ VSF_SPI_DATASIZE_14
Definition spi.h:55
VSF_SPI_DATASIZE_26
@ VSF_SPI_DATASIZE_26
Definition spi.h:67
VSF_SPI_DATASIZE_13
@ VSF_SPI_DATASIZE_13
Definition spi.h:54
VSF_SPI_DATASIZE_7
@ VSF_SPI_DATASIZE_7
Definition spi.h:104
VSF_SPI_DATASIZE_5
@ VSF_SPI_DATASIZE_5
Definition spi.h:102
VSF_SPI_DATASIZE_12
@ VSF_SPI_DATASIZE_12
Definition spi.h:53
VSF_SPI_DATASIZE_22
@ VSF_SPI_DATASIZE_22
Definition spi.h:63
VSF_SPI_DATASIZE_24
@ VSF_SPI_DATASIZE_24
Definition spi.h:65
VSF_SPI_DATASIZE_4
@ VSF_SPI_DATASIZE_4
datasize is 8 bits
Definition spi.h:101
VSF_SPI_DATASIZE_29
@ VSF_SPI_DATASIZE_29
Definition spi.h:70
VSF_SPI_DATASIZE_25
@ VSF_SPI_DATASIZE_25
Definition spi.h:66
VSF_SPI_DATASIZE_30
@ VSF_SPI_DATASIZE_30
Definition spi.h:71
VSF_SPI_DATASIZE_19
@ VSF_SPI_DATASIZE_19
Definition spi.h:60
VSF_SPI_DATASIZE_23
@ VSF_SPI_DATASIZE_23
Definition spi.h:64
VSF_SPI_DATASIZE_10
@ VSF_SPI_DATASIZE_10
Definition spi.h:51
VSF_SPI_DATASIZE_15
@ VSF_SPI_DATASIZE_15
Definition spi.h:56
VSF_SPI_CPOL_HIGH
#define VSF_SPI_CPOL_HIGH
Definition spi.h:123
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Definition spi.h:159
VSF_SPI_TI_MODE
#define VSF_SPI_TI_MODE
Definition spi.h:95
VSF_SPI_CPHA_HIGH
#define VSF_SPI_CPHA_HIGH
Definition spi.h:128
VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX
#define VSF_SPI_DATALINE_2_LINE_FULL_DUPLEX
Definition spi.h:110
VSF_SPI_CRC_ENABLED
@ VSF_SPI_CRC_ENABLED
Definition spi.h:116
VSF_SPI_CRC_DISABLED
@ VSF_SPI_CRC_DISABLED
Definition spi.h:115
VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX
#define VSF_SPI_DATALINE_1_LINE_HALF_DUPLEX
Definition spi.h:112
VSF_SPI_DATALINE_2_LINE_RX_ONLY
#define VSF_SPI_DATALINE_2_LINE_RX_ONLY
Definition spi.h:111
VSF_SPI_CPHA_LOW
#define VSF_SPI_CPHA_LOW
Definition spi.h:126
VSF_SPI_CPOL_LOW
#define VSF_SPI_CPOL_LOW
Definition spi.h:121
VSF_SPI_MOTOROLA_MODE
#define VSF_SPI_MOTOROLA_MODE
Definition spi.h:94
VSF_SPI_MOTOROLA_TI_MASK
#define VSF_SPI_MOTOROLA_TI_MASK
Definition spi.h:96
vsf_arch_prio_t
vsf_arch_prio_t
Definition cortex_a_generic.h:88
irq_mask
const i_spi_t vsf_spi_irq_mask_t irq_mask
Definition spi_interface.h:38
uint_fast8_t
unsigned char uint_fast8_t
Definition stdint.h:23
uint32_t
unsigned uint32_t
Definition stdint.h:9
uint_fast32_t
unsigned int uint_fast32_t
Definition stdint.h:27
uint8_t
unsigned char uint8_t
Definition stdint.h:5
vsf_peripheral_capability_t
Definition vsf_template_hal_driver.h:204
vsf_peripheral_status_t
Definition vsf_template_hal_driver.h:197
vsf_spi_capability_t
Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware...
Definition vsf_template_spi.h:739
vsf_spi_capability_t::support_software_cs
uint8_t support_software_cs
Hardware chip select support (1: supported, 0: not supported)
Definition vsf_template_spi.h:746
vsf_spi_capability_t::max_clock_hz
uint32_t max_clock_hz
Number of available chip select lines (0-63)
Definition vsf_template_spi.h:749
vsf_spi_capability_t::cs_count
uint8_t cs_count
Software chip select support (1: supported, 0: not supported)
Definition vsf_template_spi.h:747
vsf_spi_capability_t::irq_mask
vsf_spi_irq_mask_t irq_mask
Definition spi.h:137
vsf_spi_capability_t::support_hardware_cs
uint8_t support_hardware_cs
Supported interrupt masks for SPI operations.
Definition vsf_template_spi.h:745
vsf_spi_capability_t::min_clock_hz
uint32_t min_clock_hz
Maximum supported SPI clock frequency in Hz.
Definition vsf_template_spi.h:750
vsf_spi_capability_t::inherit
inherit(vsf_peripheral_capability_t) vsf_spi_irq_mask_t irq_mask
Inherit peripheral capabilities.
vsf_spi_cfg_t
Configuration structure for SPI.
Definition vsf_template_spi.h:797
vsf_spi_cfg_t::clock_hz
uint32_t clock_hz
SPI operating mode (master/slave, CPOL/CPHA, bit order, data size)
Definition vsf_template_spi.h:799
vsf_spi_cfg_t::isr
vsf_spi_isr_t isr
SPI clock frequency in Hz (must be between min_clock_hz and max_clock_hz)
Definition vsf_template_spi.h:800
vsf_spi_cfg_t::mode
vsf_spi_mode_t mode
Definition vsf_template_spi.h:798
vsf_spi_cfg_t::auto_cs_index
uint8_t auto_cs_index
Interrupt configuration (handler, target pointer, priority)
Definition vsf_template_spi.h:803
vsf_spi_isr_t
SPI interrupt service routine configuration structure.
Definition vsf_template_spi.h:785
vsf_spi_isr_t::handler_fn
vsf_spi_isr_handler_t * handler_fn
Definition vsf_template_spi.h:786
vsf_spi_isr_t::target_ptr
void * target_ptr
Interrupt handler function (NULL to disable interrupts)
Definition vsf_template_spi.h:787
vsf_spi_isr_t::prio
vsf_arch_prio_t prio
User context pointer passed to handler.
Definition vsf_template_spi.h:788
vsf_spi_op_t
SPI operation function pointer type, used for SPI Multi Class support.
Definition vsf_template_spi.h:1115
vsf_spi_status_t
Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doe...
Definition vsf_template_spi.h:719
vsf_spi_status_t::is_busy
uint32_t is_busy
Definition spi.h:127
vsf_spi_t
SPI instance structure, used for SPI Multi Class support, not needed in non Multi Class mode.
Definition vsf_template_spi.h:1131
vsf_spi_t::op
const vsf_spi_op_t * op
Definition vsf_template_spi.h:1132
vsf_spi_isr_handler_t
void vsf_spi_isr_handler_t(void *target_ptr, vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Definition spi.h:189
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Definition spi.h:148
vsf_spi_mode_t
vsf_spi_mode_t
Definition spi.h:119
VSF_SPI_DATASIZE_BIT_OFFSET
#define VSF_SPI_DATASIZE_BIT_OFFSET
Definition spi.h:224
VSF_SPI_DATASIZE_VALUE_OFFSET
#define VSF_SPI_DATASIZE_VALUE_OFFSET
Definition spi.h:227
vsf_arch.h
fsm_rt_t
fsm_rt_t
Definition vsf_fsm.h:315
vsf_spi
vsf_spi_t vsf_spi[SPI_COUNT]
Definition vsf_spi.c:3
vsf_template_hal_driver.h
vsf_spi_fifo_transfer
void vsf_spi_fifo_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr, uint_fast32_t *out_offset_ptr, void *in_buffer_ptr, uint_fast32_t *in_offset_ptr, uint_fast32_t count)
Perform FIFO-based data transfer on a SPI instance.
Definition spi_common.c:137
vsf_spi_isr_t
struct vsf_spi_isr_t vsf_spi_isr_t
SPI interrupt service routine configuration structure.
vsf_spi_isr_handler_t
void vsf_spi_isr_handler_t(void *target_ptr, vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
SPI interrupt handler type declaration.
Definition vsf_template_spi.h:774
VSF_SPI_MODE_MASK
@ VSF_SPI_MODE_MASK
SPI mode mask for clock polarity and phase configuration.
Definition vsf_template_spi.h:564
VSF_SPI_BIT_ORDER_MASK
@ VSF_SPI_BIT_ORDER_MASK
SPI bit order mask for MSB/LSB first selection.
Definition vsf_template_spi.h:553
VSF_SPI_DIR_MODE_MASK
@ VSF_SPI_DIR_MODE_MASK
SPI direction mode mask for master/slave selection.
Definition vsf_template_spi.h:542
VSF_SPI_CS_MODE_MASK
@ VSF_SPI_CS_MODE_MASK
Definition vsf_template_spi.h:574
VSF_SPI_MODE_ALL_BITS_MASK
@ VSF_SPI_MODE_ALL_BITS_MASK
Definition vsf_template_spi.h:601
VSF_SPI_DATASIZE_MASK
@ VSF_SPI_DATASIZE_MASK
Definition vsf_template_spi.h:591
vsf_spi_status
vsf_spi_status_t vsf_spi_status(vsf_spi_t *spi_ptr)
Get the current status of a SPI instance.
Definition spi_common.c:110
vsf_spi_request_transfer
vsf_err_t vsf_spi_request_transfer(vsf_spi_t *spi_ptr, void *out_buffer_ptr, void *in_buffer_ptr, uint_fast32_t count)
Request a SPI data transfer operation.
Definition spi_common.c:149
vsf_spi_cfg_t
struct vsf_spi_cfg_t vsf_spi_cfg_t
Configuration structure for SPI.
vsf_spi_capability_t
struct vsf_spi_capability_t vsf_spi_capability_t
Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware...
VSF_SPI_APIS
#define VSF_SPI_APIS(__prefix_name)
SPI API template, used to generate SPI type, specific prefix function declarations,...
Definition vsf_template_spi.h:273
vsf_spi_get_configuration
vsf_err_t vsf_spi_get_configuration(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr)
Get current configuration of a SPI instance.
Definition spi_common.c:55
vsf_spi_get_transferred_count
void vsf_spi_get_transferred_count(vsf_spi_t *spi_ptr, uint_fast32_t *sent_count, uint_fast32_t *received_count)
Get the number of data units transferred in the current or last SPI operation.
Definition spi_common.c:169
vsf_spi_cs_active
vsf_err_t vsf_spi_cs_active(vsf_spi_t *spi_ptr, uint_fast8_t index)
Activate (assert) a SPI chip select line.
Definition spi_common.c:119
vsf_spi_irq_mask_t
vsf_spi_irq_mask_t
Predefined VSF SPI interrupt masks that can be reimplemented in specific HAL drivers....
Definition vsf_template_spi.h:633
VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR
@ VSF_SPI_IRQ_MASK_RX_OVERFLOW_ERR
RX complete interrupt (triggers when RX transfer is complete)
Definition vsf_template_spi.h:638
VSF_SPI_IRQ_MASK_RX_CPL
@ VSF_SPI_IRQ_MASK_RX_CPL
TX complete interrupt (triggers when all TX data has been sent)
Definition vsf_template_spi.h:637
VSF_SPI_IRQ_MASK_RX
@ VSF_SPI_IRQ_MASK_RX
TX FIFO threshold interrupt (triggers when TX FIFO level is below threshold)
Definition vsf_template_spi.h:635
VSF_SPI_IRQ_MASK_TX
@ VSF_SPI_IRQ_MASK_TX
Definition vsf_template_spi.h:634
VSF_SPI_IRQ_MASK_TX_CPL
@ VSF_SPI_IRQ_MASK_TX_CPL
RX FIFO threshold interrupt (triggers when RX FIFO level is above threshold)
Definition vsf_template_spi.h:636
vsf_spi_ctrl
vsf_err_t vsf_spi_ctrl(vsf_spi_t *spi_ptr, vsf_spi_ctrl_t ctrl, void *param)
Execute a control command on the SPI instance.
Definition spi_common.c:188
vsf_spi_enable
fsm_rt_t vsf_spi_enable(vsf_spi_t *spi_ptr)
Enable a SPI instance for operation.
Definition spi_common.c:65
vsf_spi_irq_clear
vsf_spi_irq_mask_t vsf_spi_irq_clear(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Clear interrupt flags of SPI instance and return previous state.
Definition spi_common.c:101
vsf_spi_disable
fsm_rt_t vsf_spi_disable(vsf_spi_t *spi_ptr)
Disable a SPI instance from operation.
Definition spi_common.c:74
vsf_spi_status_t
struct vsf_spi_status_t vsf_spi_status_t
Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doe...
vsf_spi_mode_t
vsf_spi_mode_t
Predefined VSF SPI modes that can be reimplemented in specific HAL drivers.
Definition vsf_template_spi.h:359
VSF_SPI_SLAVE
@ VSF_SPI_SLAVE
Master mode (controller)
Definition vsf_template_spi.h:362
VSF_SPI_DATASIZE_16
@ VSF_SPI_DATASIZE_16
8-bit data transfer size (requires 1-byte buffer)
Definition vsf_template_spi.h:386
VSF_SPI_LSB_FIRST
@ VSF_SPI_LSB_FIRST
Most Significant Bit (MSB) first.
Definition vsf_template_spi.h:366
VSF_SPI_MODE_1
@ VSF_SPI_MODE_1
Mode 0: CPOL=0 (idle low), CPHA=0 (sample on first edge)
Definition vsf_template_spi.h:370
VSF_SPI_DATASIZE_8
@ VSF_SPI_DATASIZE_8
Definition vsf_template_spi.h:385
VSF_SPI_MASTER
@ VSF_SPI_MASTER
Definition vsf_template_spi.h:361
VSF_SPI_MSB_FIRST
@ VSF_SPI_MSB_FIRST
Slave mode (peripheral)
Definition vsf_template_spi.h:365
VSF_SPI_DATASIZE_32
@ VSF_SPI_DATASIZE_32
16-bit data transfer size (requires 2-byte buffer)
Definition vsf_template_spi.h:387
VSF_SPI_CS_SOFTWARE_MODE
@ VSF_SPI_CS_SOFTWARE_MODE
Mode 3: CPOL=1 (idle high), CPHA=1 (sample on second edge)
Definition vsf_template_spi.h:377
VSF_SPI_MODE_0
@ VSF_SPI_MODE_0
Least Significant Bit (LSB) first.
Definition vsf_template_spi.h:369
VSF_SPI_CS_HARDWARE_MODE
@ VSF_SPI_CS_HARDWARE_MODE
Definition vsf_template_spi.h:380
VSF_SPI_MODE_3
@ VSF_SPI_MODE_3
Mode 2: CPOL=1 (idle high), CPHA=0 (sample on first edge)
Definition vsf_template_spi.h:372
VSF_SPI_MODE_2
@ VSF_SPI_MODE_2
Mode 1: CPOL=0 (idle low), CPHA=1 (sample on second edge)
Definition vsf_template_spi.h:371
VSF_SPI_IRQ_MASK_CPL
@ VSF_SPI_IRQ_MASK_CPL
Alias for VSF_SPI_IRQ_MASK_RX.
Definition vsf_template_spi.h:684
VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD
@ VSF_SPI_IRQ_MASK_TX_FIFO_THRESHOLD
Definition vsf_template_spi.h:677
VSF_SPI_IRQ_ALL_BITS_MASK
@ VSF_SPI_IRQ_ALL_BITS_MASK
Definition vsf_template_spi.h:700
VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD
@ VSF_SPI_IRQ_MASK_RX_FIFO_THRESHOLD
Alias for VSF_SPI_IRQ_MASK_TX.
Definition vsf_template_spi.h:678
VSF_SPI_IRQ_MASK_ERR
@ VSF_SPI_IRQ_MASK_ERR
Definition vsf_template_spi.h:691
vsf_spi_irq_disable
void vsf_spi_irq_disable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Disable specific interrupts for a SPI instance.
Definition spi_common.c:92
vsf_spi_ctrl_t
vsf_spi_ctrl_t
Predefined VSF SPI control commands that can be reimplemented in specific HAL drivers.
Definition vsf_template_spi.h:842
__VSF_SPI_CTRL_DUMMY
@ __VSF_SPI_CTRL_DUMMY
Dummy value for compilation, required when no actual control commands are defined.
Definition vsf_template_spi.h:860
vsf_spi_init
vsf_err_t vsf_spi_init(vsf_spi_t *spi_ptr, vsf_spi_cfg_t *cfg_ptr)
Initialize a SPI instance.
Definition spi_common.c:37
vsf_spi_irq_enable
void vsf_spi_irq_enable(vsf_spi_t *spi_ptr, vsf_spi_irq_mask_t irq_mask)
Enable specific interrupts for a SPI instance.
Definition spi_common.c:83
vsf_spi_fini
void vsf_spi_fini(vsf_spi_t *spi_ptr)
Finalize (deinitialize) a SPI instance.
Definition spi_common.c:46
vsf_spi_cs_inactive
vsf_err_t vsf_spi_cs_inactive(vsf_spi_t *spi_ptr, uint_fast8_t index)
Deactivate (deassert) a SPI chip select line.
Definition spi_common.c:128
vsf_spi_cancel_transfer
vsf_err_t vsf_spi_cancel_transfer(vsf_spi_t *spi_ptr)
Cancel an ongoing SPI transfer operation.
Definition spi_common.c:160
vsf_spi_capability
vsf_spi_capability_t vsf_spi_capability(vsf_spi_t *spi_ptr)
Get the capabilities of a SPI instance.
Definition spi_common.c:179
Generated from commit: vsfteam/vsf@b2e9e8a