Go to the source code of this file.
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class | vsf_$ |
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struct | vsf_spi_status_t |
| Predefined VSF SPI status that can be reimplemented in specific HAL drivers. Even if the hardware doesn't support these features, these status must be kept. More...
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struct | vsf_spi_capability_t |
| Predefined VSF SPI capability that can be reimplemented in specific HAL drivers. Even if the hardware doesn't support these features, these capabilities must be kept. More...
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struct | vsf_spi_isr_t |
| SPI interrupt service routine configuration structure. More...
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struct | vsf_spi_cfg_t |
| Configuration structure for SPI. More...
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enum | vsf_spi_mode_t {
VSF_SPI_MASTER = 0x00ul << 0
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VSF_SPI_SLAVE = 0x01ul << 0
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VSF_SPI_MSB_FIRST = 0x00ul << 1
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VSF_SPI_LSB_FIRST = 0x01ul << 1
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VSF_SPI_CPOL_LOW = 0x00ul << 2
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VSF_SPI_CPOL_HIGH = 0x01ul << 2
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VSF_SPI_CPHA_LOW = 0x00ul << 2
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VSF_SPI_CPHA_HIGH = 0x01ul << 2
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VSF_SPI_MODE_0 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_LOW
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VSF_SPI_MODE_1 = VSF_SPI_CPOL_LOW | VSF_SPI_CPHA_HIGH
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VSF_SPI_MODE_2 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_LOW
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VSF_SPI_MODE_3 = VSF_SPI_CPOL_HIGH | VSF_SPI_CPHA_HIGH
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VSF_SPI_CS_SOFTWARE_MODE = 0x00ul << 4
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VSF_SPI_CS_HARDWARE_MODE = 0x01ul << 4
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VSF_SPI_DATASIZE_8 = 0x00ul << 8
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VSF_SPI_DATASIZE_16 = 0x01ul << 8
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VSF_SPI_DATASIZE_32 = 0x02ul << 8
} |
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enum | vsf_spi_irq_mask_t {
VSF_SPI_IRQ_MASK_TX = 0x01ul << 0
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VSF_SPI_IRQ_MASK_RX = 0x01ul << 1
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VSF_SPI_IRQ_MASK_TX_CPL = 0x01ul << 2
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VSF_SPI_IRQ_MASK_CPL = 0x01ul << 3
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VSF_SPI_IRQ_MASK_OVERFLOW_ERR = 0x01ul << 4
} |
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enum | vsf_spi_ctrl_t { __VSF_SPI_CTRL_DUMMY = 0
} |
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◆ __HAL_DRIVER_
#define __HAL_DRIVER_ ${SERIES/SPI_IP}_SPI_H__ |
◆ VSF_
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE
#define VSF_SPI_CFG_REIMPLEMENT_TYPE_MODE ENABLED |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK
#define VSF_SPI_CFG_REIMPLEMENT_TYPE_IRQ_MASK ENABLED |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS
#define VSF_SPI_CFG_REIMPLEMENT_TYPE_STATUS ENABLED |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL
#define VSF_SPI_CFG_REIMPLEMENT_TYPE_CTRL ENABLED |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG
#define VSF_SPI_CFG_REIMPLEMENT_TYPE_CFG ENABLED |
◆ VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY
#define VSF_SPI_CFG_REIMPLEMENT_TYPE_CAPABILITY ENABLED |
◆ vsf_spi_mode_t
◆ vsf_spi_irq_mask_t
◆ vsf_spi_status_t
◆ vsf_spi_capability_t
◆ vsf_spi_t
◆ vsf_spi_isr_handler_t
◆ vsf_spi_isr_t
◆ vsf_spi_cfg_t
◆ vsf_spi_ctrl_t
◆ vsf_spi_mode_t
Enumerator |
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VSF_SPI_MASTER | |
VSF_SPI_SLAVE | |
VSF_SPI_MSB_FIRST | |
VSF_SPI_LSB_FIRST | |
VSF_SPI_CPOL_LOW | |
VSF_SPI_CPOL_HIGH | |
VSF_SPI_CPHA_LOW | |
VSF_SPI_CPHA_HIGH | |
VSF_SPI_MODE_0 | |
VSF_SPI_MODE_1 | |
VSF_SPI_MODE_2 | |
VSF_SPI_MODE_3 | |
VSF_SPI_CS_SOFTWARE_MODE | |
VSF_SPI_CS_HARDWARE_MODE | |
VSF_SPI_DATASIZE_8 | |
VSF_SPI_DATASIZE_16 | |
VSF_SPI_DATASIZE_32 | |
◆ vsf_spi_irq_mask_t
Enumerator |
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VSF_SPI_IRQ_MASK_TX | |
VSF_SPI_IRQ_MASK_RX | |
VSF_SPI_IRQ_MASK_TX_CPL | |
VSF_SPI_IRQ_MASK_CPL | |
VSF_SPI_IRQ_MASK_OVERFLOW_ERR | |
◆ vsf_spi_ctrl_t
Enumerator |
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__VSF_SPI_CTRL_DUMMY | |
◆ reg
◆ isr