usart.h File Reference

#include "hal/vsf_hal_cfg.h"
#include "hal/driver/common/template/vsf_template_hal_driver.h"

Go to the source code of this file.

Macros
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_MODE   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_CTRL   ENABLED
#define	VSF_USART_HALF_DUPLEX_ENABLE   VSF_USART_HALF_DUPLEX_ENABLE
#define	VSF_USART_TX_DISABLE   VSF_USART_TX_DISABLE
#define	VSF_USART_RX_DISABLE   VSF_USART_RX_DISABLE
#define	VSF_USART_RTS_HWCONTROL   VSF_USART_RTS_HWCONTROL
#define	VSF_USART_CTS_HWCONTROL   VSF_USART_CTS_HWCONTROL
#define	VSF_USART_RTS_CTS_HWCONTROL   VSF_USART_RTS_CTS_HWCONTROL
#define	VSF_USART_7_BIT_LENGTH   VSF_USART_7_BIT_LENGTH
#define	VSF_USART_0_5_STOPBIT   VSF_USART_0_5_STOPBIT
#define	VSF_USART_1_5_STOPBIT   VSF_USART_1_5_STOPBIT
#define	VSF_USART_2_STOPBIT   VSF_USART_2_STOPBIT
#define	VSF_USART_SYNC_CLOCK_ENABLE   VSF_USART_SYNC_CLOCK_ENABLE
#define	VSF_USART_SYNC_CLOCK_DISABLE   VSF_USART_SYNC_CLOCK_DISABLE
#define	VSF_USART_SYNC_CLOCK_POLARITY_LOW   VSF_USART_SYNC_CLOCK_POLARITY_LOW
#define	VSF_USART_SYNC_CLOCK_POLARITY_HIGH   VSF_USART_SYNC_CLOCK_POLARITY_HIGH
#define	VSF_USART_SYNC_CLOCK_PHASE_1_EDGE   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE
#define	VSF_USART_SYNC_CLOCK_PHASE_2_EDGE   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE
#define	VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE
#define	VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
#define	VSF_USART_SYNC_CLOCK_LAST_BIT_MASK   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE | VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
#define	VSF_USART_SWAP   VSF_USART_SWAP
#define	VSF_USART_TX_INV   VSF_USART_TX_INV
#define	VSF_USART_RX_INV   VSF_USART_RX_INV
#define	VSF_USART_TX_FIFO_THRESHOLD_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_EMPTY
#define	VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
#define	VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
#define	VSF_USART_RX_FIFO_THRESHOLD_FULL   VSF_USART_RX_FIFO_THRESHOLD_FULL
#define	VSF_USART_IRQ_MASK_TX_IDLE   VSF_USART_IRQ_MASK_TX_IDLE
#define	VSF_USART_IRQ_MASK_RX_IDLE   VSF_USART_IRQ_MASK_RX_IDLE
#define	VSF_USART_CTRL_SEND_BREAK   VSF_USART_CTRL_SEND_BREAK

Typedefs
typedef enum vsf_usart_mode_t	vsf_usart_mode_t
typedef enum vsf_usart_irq_mask_t	vsf_usart_irq_mask_t
typedef enum vsf_usart_ctrl_t	vsf_usart_ctrl_t

Enumerations
enum	vsf_usart_mode_t {   VSF_USART_HALF_DUPLEX_ENABLE = (1 << 3) >> 2 ,   VSF_USART_HALF_DUPLEX_DISABLE = (0 << 3) >> 2 ,   VSF_USART_HALF_DUPLEX_ENABLE = (1 << 3) >> 2 ,   VSF_USART_TX_ENABLE = (1 << 3) ,   VSF_USART_TX_DISABLE = (0 << 3) ,   VSF_USART_RX_ENABLE = (1 << 2) ,   VSF_USART_RX_DISABLE = (0 << 2) ,   VSF_USART_TX_DISABLE = (0 << 3) ,   VSF_USART_RX_DISABLE = (0 << 2) ,   VSF_USART_NO_HWCONTROL = (0) >> 2 ,   VSF_USART_RTS_HWCONTROL = (1 << 8) >> 2 ,   VSF_USART_CTS_HWCONTROL = (1 << 9) >> 2 ,   VSF_USART_RTS_CTS_HWCONTROL ,   VSF_USART_RTS_HWCONTROL = (1 << 8) >> 2 ,   VSF_USART_CTS_HWCONTROL = (1 << 9) >> 2 ,   VSF_USART_RTS_CTS_HWCONTROL ,   VSF_USART_NO_PARITY = (0 << 10) ,   VSF_USART_ODD_PARITY = (1 << 10) | (1 << 9) ,   VSF_USART_EVEN_PARITY = (1 << 10) | (0 << 9) ,   VSF_USART_7_BIT_LENGTH = (0 << 12) | (1 << 28) ,   VSF_USART_8_BIT_LENGTH = (0 << 12) | (0 << 28) ,   VSF_USART_7_BIT_LENGTH = (0 << 12) | (1 << 28) ,   VSF_USART_0_5_STOPBIT = (1 << 12) << 5 ,   VSF_USART_1_STOPBIT = (0 << 12) << 5 ,   VSF_USART_1_5_STOPBIT = (3 << 12) << 5 ,   VSF_USART_2_STOPBIT = (2 << 12) << 5 ,   VSF_USART_0_5_STOPBIT = (1 << 12) << 5 ,   VSF_USART_1_5_STOPBIT = (3 << 12) << 5 ,   VSF_USART_2_STOPBIT = (2 << 12) << 5 ,   VSF_USART_SYNC_CLOCK_ENABLE = (1 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_DISABLE = (0 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_POLARITY_LOW = (0 << 10) << 5 ,   VSF_USART_SYNC_CLOCK_POLARITY_HIGH = (1 << 10) << 5 ,   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE = (0 << 9) << 5 ,   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE = (1 << 9) << 5 ,   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE = (1 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE = (0 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_ENABLE = (1 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_DISABLE = (0 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_POLARITY_LOW = (0 << 10) << 5 ,   VSF_USART_SYNC_CLOCK_POLARITY_HIGH = (1 << 10) << 5 ,   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE = (0 << 9) << 5 ,   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE = (1 << 9) << 5 ,   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE = (1 << 11) << 5 ,   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE = (0 << 11) << 5 ,   VSF_USART_SWAP = (1 << 15) << 5 ,   VSF_USART_SWAP = (1 << 15) << 5 ,   VSF_USART_TX_INV = (1 << 17) << 5 ,   VSF_USART_RX_INV = (1 << 16) << 5 ,   VSF_USART_TX_INV = (1 << 17) << 5 ,   VSF_USART_RX_INV = (1 << 16) << 5 ,   __VSF_HW_USART_CTRL1_MASK ,   __VSF_HW_USART_CTRL2_MASK ,   __VSF_HW_USART_CTRL2_SHIFT_BITS = 5 ,   __VSF_HW_USART_CTRL3_MASK ,   __VSF_HW_USART_CTRL3_SHIFT_BITS = 2 ,   VSF_USART_5_BIT_LENGTH = (1 << 23) ,   VSF_USART_6_BIT_LENGTH = (2 << 23) ,   VSF_USART_9_BIT_LENGTH = (3 << 23) ,   VSF_USART_10_BIT_LENGTH = (4 << 23) ,   VSF_USART_TX_FIFO_THRESHOLD_EMPTY = (0 << 26) ,   VSF_USART_TX_FIFO_THRESHOLD_EMPTY = (0 << 26) ,   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = (1 << 26) ,   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = (2 << 26) ,   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = (2 << 26) ,   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = (0 << 29) ,   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = (0 << 29) ,   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = (1 << 29) ,   VSF_USART_RX_FIFO_THRESHOLD_FULL = (2 << 29) ,   VSF_USART_RX_FIFO_THRESHOLD_FULL = (2 << 29) ,   VSF_USART_FORCE_0_PARITY = (0 << 31) ,   VSF_USART_FORCE_1_PARITY = (1 << 31) ,   __VSF_HW_USART_NOT_SUPPORT_MASK }
enum	vsf_usart_irq_mask_t {   VSF_USART_IRQ_MASK_TX_CPL = (1 << 12) ,   VSF_USART_IRQ_MASK_RX_CPL = (1 << 13) ,   VSF_USART_IRQ_MASK_TX = (1 << 7) ,   VSF_USART_IRQ_MASK_TX_IDLE = (1 << 6) ,   VSF_USART_IRQ_MASK_TX_IDLE = (1 << 6) ,   VSF_USART_IRQ_MASK_RX = (1 << 5) ,   VSF_USART_IRQ_MASK_RX_TIMEOUT = (1 << 11) ,   VSF_USART_IRQ_MASK_RX_IDLE = (1 << 4) ,   VSF_USART_IRQ_MASK_RX_IDLE = (1 << 4) ,   VSF_USART_IRQ_MASK_CTS = (1 << 9) ,   VSF_USART_IRQ_MASK_FRAME_ERR = (1 << 1) ,   VSF_USART_IRQ_MASK_NOISE_ERR = (1 << 2) ,   VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR = (1 << 3) ,   VSF_USART_IRQ_MASK_PARITY_ERR = (1 << 0) ,   VSF_USART_IRQ_MASK_BREAK_ERR = (1 << 8) ,   __VSF_HW_USART_IRQ_MASK_CTRL1 }
enum	vsf_usart_ctrl_t {   VSF_USART_CTRL_SEND_BREAK = (1 << 0) ,   VSF_USART_CTRL_SEND_BREAK = (1 << 0) ,   __VSF_HW_USART_SUPPORT_CMD_MASK = VSF_USART_CTRL_SEND_BREAK ,   VSF_USART_CTRL_SET_BREAK = (1 << 8) ,   VSF_USART_CTRL_CLEAR_BREAK = (1 << 9) }

Macro Definition Documentation

VSF_USART_CFG_REIMPLEMENT_TYPE_MODE

#define VSF_USART_CFG_REIMPLEMENT_TYPE_MODE   ENABLED

Note

When vsf_peripheral_status_t is inherited, vsf_template_hal_driver.h needs to be included

VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK

#define VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_CTRL

#define VSF_USART_CFG_REIMPLEMENT_TYPE_CTRL   ENABLED

VSF_USART_HALF_DUPLEX_ENABLE

#define VSF_USART_HALF_DUPLEX_ENABLE   VSF_USART_HALF_DUPLEX_ENABLE

VSF_USART_TX_DISABLE

#define VSF_USART_TX_DISABLE   VSF_USART_TX_DISABLE

VSF_USART_RX_DISABLE

#define VSF_USART_RX_DISABLE   VSF_USART_RX_DISABLE

VSF_USART_RTS_HWCONTROL

#define VSF_USART_RTS_HWCONTROL   VSF_USART_RTS_HWCONTROL

VSF_USART_CTS_HWCONTROL

#define VSF_USART_CTS_HWCONTROL   VSF_USART_CTS_HWCONTROL

VSF_USART_RTS_CTS_HWCONTROL

#define VSF_USART_RTS_CTS_HWCONTROL   VSF_USART_RTS_CTS_HWCONTROL

VSF_USART_7_BIT_LENGTH

#define VSF_USART_7_BIT_LENGTH   VSF_USART_7_BIT_LENGTH

VSF_USART_0_5_STOPBIT

#define VSF_USART_0_5_STOPBIT   VSF_USART_0_5_STOPBIT

VSF_USART_1_5_STOPBIT

#define VSF_USART_1_5_STOPBIT   VSF_USART_1_5_STOPBIT

VSF_USART_2_STOPBIT

#define VSF_USART_2_STOPBIT   VSF_USART_2_STOPBIT

VSF_USART_SYNC_CLOCK_ENABLE

#define VSF_USART_SYNC_CLOCK_ENABLE   VSF_USART_SYNC_CLOCK_ENABLE

VSF_USART_SYNC_CLOCK_DISABLE

#define VSF_USART_SYNC_CLOCK_DISABLE   VSF_USART_SYNC_CLOCK_DISABLE

VSF_USART_SYNC_CLOCK_POLARITY_LOW

#define VSF_USART_SYNC_CLOCK_POLARITY_LOW   VSF_USART_SYNC_CLOCK_POLARITY_LOW

VSF_USART_SYNC_CLOCK_POLARITY_HIGH

#define VSF_USART_SYNC_CLOCK_POLARITY_HIGH   VSF_USART_SYNC_CLOCK_POLARITY_HIGH

VSF_USART_SYNC_CLOCK_PHASE_1_EDGE

#define VSF_USART_SYNC_CLOCK_PHASE_1_EDGE   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE

VSF_USART_SYNC_CLOCK_PHASE_2_EDGE

#define VSF_USART_SYNC_CLOCK_PHASE_2_EDGE   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE

VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE

#define VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE

VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE

#define VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE

VSF_USART_SYNC_CLOCK_LAST_BIT_MASK

#define VSF_USART_SYNC_CLOCK_LAST_BIT_MASK   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE | VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE

VSF_USART_SWAP

#define VSF_USART_SWAP   VSF_USART_SWAP

VSF_USART_TX_INV

#define VSF_USART_TX_INV   VSF_USART_TX_INV

VSF_USART_RX_INV

#define VSF_USART_RX_INV   VSF_USART_RX_INV

VSF_USART_TX_FIFO_THRESHOLD_EMPTY

#define VSF_USART_TX_FIFO_THRESHOLD_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_EMPTY

VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL

#define VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL

VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY

#define VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY

VSF_USART_RX_FIFO_THRESHOLD_FULL

#define VSF_USART_RX_FIFO_THRESHOLD_FULL   VSF_USART_RX_FIFO_THRESHOLD_FULL

VSF_USART_IRQ_MASK_TX_IDLE

#define VSF_USART_IRQ_MASK_TX_IDLE   VSF_USART_IRQ_MASK_TX_IDLE

VSF_USART_IRQ_MASK_RX_IDLE

#define VSF_USART_IRQ_MASK_RX_IDLE   VSF_USART_IRQ_MASK_RX_IDLE

VSF_USART_CTRL_SEND_BREAK

#define VSF_USART_CTRL_SEND_BREAK   VSF_USART_CTRL_SEND_BREAK

Typedef Documentation

vsf_usart_mode_t

typedef enum vsf_usart_mode_t vsf_usart_mode_t

vsf_usart_irq_mask_t

typedef enum vsf_usart_irq_mask_t vsf_usart_irq_mask_t

vsf_usart_ctrl_t

typedef enum vsf_usart_ctrl_t vsf_usart_ctrl_t

Enumeration Type Documentation

vsf_usart_mode_t

enum vsf_usart_mode_t

Enumerator
VSF_USART_HALF_DUPLEX_ENABLE
VSF_USART_HALF_DUPLEX_DISABLE
VSF_USART_HALF_DUPLEX_ENABLE
VSF_USART_TX_ENABLE
VSF_USART_TX_DISABLE
VSF_USART_RX_ENABLE
VSF_USART_RX_DISABLE
VSF_USART_TX_DISABLE
VSF_USART_RX_DISABLE
VSF_USART_NO_HWCONTROL
VSF_USART_RTS_HWCONTROL
VSF_USART_CTS_HWCONTROL
VSF_USART_RTS_CTS_HWCONTROL
VSF_USART_RTS_HWCONTROL
VSF_USART_CTS_HWCONTROL
VSF_USART_RTS_CTS_HWCONTROL
VSF_USART_NO_PARITY
VSF_USART_ODD_PARITY
VSF_USART_EVEN_PARITY
VSF_USART_7_BIT_LENGTH
VSF_USART_8_BIT_LENGTH
VSF_USART_7_BIT_LENGTH
VSF_USART_0_5_STOPBIT
VSF_USART_1_STOPBIT
VSF_USART_1_5_STOPBIT
VSF_USART_2_STOPBIT
VSF_USART_0_5_STOPBIT
VSF_USART_1_5_STOPBIT
VSF_USART_2_STOPBIT
VSF_USART_SYNC_CLOCK_ENABLE
VSF_USART_SYNC_CLOCK_DISABLE
VSF_USART_SYNC_CLOCK_POLARITY_LOW
VSF_USART_SYNC_CLOCK_POLARITY_HIGH
VSF_USART_SYNC_CLOCK_PHASE_1_EDGE
VSF_USART_SYNC_CLOCK_PHASE_2_EDGE
VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE
VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
VSF_USART_SYNC_CLOCK_ENABLE
VSF_USART_SYNC_CLOCK_DISABLE
VSF_USART_SYNC_CLOCK_POLARITY_LOW
VSF_USART_SYNC_CLOCK_POLARITY_HIGH
VSF_USART_SYNC_CLOCK_PHASE_1_EDGE
VSF_USART_SYNC_CLOCK_PHASE_2_EDGE
VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE
VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
VSF_USART_SWAP
VSF_USART_SWAP
VSF_USART_TX_INV
VSF_USART_RX_INV
VSF_USART_TX_INV
VSF_USART_RX_INV
__VSF_HW_USART_CTRL1_MASK
__VSF_HW_USART_CTRL2_MASK
__VSF_HW_USART_CTRL2_SHIFT_BITS
__VSF_HW_USART_CTRL3_MASK
__VSF_HW_USART_CTRL3_SHIFT_BITS
VSF_USART_5_BIT_LENGTH
VSF_USART_6_BIT_LENGTH
VSF_USART_9_BIT_LENGTH
VSF_USART_10_BIT_LENGTH
VSF_USART_TX_FIFO_THRESHOLD_EMPTY	TX FIFO empty.
VSF_USART_TX_FIFO_THRESHOLD_EMPTY	TX FIFO empty.
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY	TX FIFO half empty.
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL	TX FIFO not full.
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL	TX FIFO not full.
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY	RX FIFO not empty.
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY	RX FIFO not empty.
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL	RX FIFO half full.
VSF_USART_RX_FIFO_THRESHOLD_FULL	RX FIFO full.
VSF_USART_RX_FIFO_THRESHOLD_FULL	RX FIFO full.
VSF_USART_FORCE_0_PARITY
VSF_USART_FORCE_1_PARITY
__VSF_HW_USART_NOT_SUPPORT_MASK

vsf_usart_irq_mask_t

enum vsf_usart_irq_mask_t

Enumerator
VSF_USART_IRQ_MASK_TX_CPL
VSF_USART_IRQ_MASK_RX_CPL
VSF_USART_IRQ_MASK_TX
VSF_USART_IRQ_MASK_TX_IDLE
VSF_USART_IRQ_MASK_TX_IDLE
VSF_USART_IRQ_MASK_RX
VSF_USART_IRQ_MASK_RX_TIMEOUT
VSF_USART_IRQ_MASK_RX_IDLE
VSF_USART_IRQ_MASK_RX_IDLE
VSF_USART_IRQ_MASK_CTS
VSF_USART_IRQ_MASK_FRAME_ERR
VSF_USART_IRQ_MASK_NOISE_ERR
VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR
VSF_USART_IRQ_MASK_PARITY_ERR
VSF_USART_IRQ_MASK_BREAK_ERR
__VSF_HW_USART_IRQ_MASK_CTRL1

vsf_usart_ctrl_t

enum vsf_usart_ctrl_t

Enumerator
VSF_USART_CTRL_SEND_BREAK
VSF_USART_CTRL_SEND_BREAK
__VSF_HW_USART_SUPPORT_CMD_MASK
VSF_USART_CTRL_SET_BREAK
VSF_USART_CTRL_CLEAR_BREAK