VSF Documented
CMSDK_ARMv8MBL.h
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1/**************************************************************************/
8/* Copyright (c) 2015 - 2016 ARM LIMITED
9
10 All rights reserved.
11 Redistribution and use in source and binary forms, with or without
12 modification, are permitted provided that the following conditions are met:
13 - Redistributions of source code must retain the above copyright
14 notice, this list of conditions and the following disclaimer.
15 - Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18 - Neither the name of ARM nor the names of its contributors may be used
19 to endorse or promote products derived from this software without
20 specific prior written permission.
21 *
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 POSSIBILITY OF SUCH DAMAGE.
33 ---------------------------------------------------------------------------*/
34
35
36#ifndef CMSDK_ARMv8MBL_H
37#define CMSDK_ARMv8MBL_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43
44/* ------------------------- Interrupt Number Definition ------------------------ */
45
46typedef enum IRQn
47{
48/* -------------------- ARMv8MBL Processor Exceptions Numbers ------------------- */
49 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
50 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
51
52
53
54
55 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
56
57 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
58 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
59
60/* -------------------- ARMv8MBL Specific Interrupt Numbers --------------------- */
61 UART0RX_IRQn = 0, /* UART 0 receive interrupt */
62 UART0TX_IRQn = 1, /* UART 0 transmit interrupt */
63 UART1RX_IRQn = 2, /* UART 1 receive interrupt */
64 UART1TX_IRQn = 3, /* UART 1 transmit interrupt */
65 UART2RX_IRQn = 4, /* UART 2 receive interrupt */
66 UART2TX_IRQn = 5, /* UART 2 transmit interrupt */
67 GPIO0ALL_IRQn = 6, /* GPIO 0 combined interrupt */
68 GPIO1ALL_IRQn = 7, /* GPIO 1 combined interrupt */
69 TIMER0_IRQn = 8, /* Timer 0 interrupt */
70 TIMER1_IRQn = 9, /* Timer 1 interrupt */
71 DUALTIMER_IRQn = 10, /* Dual Timer interrupt */
72 SPI_0_1_IRQn = 11, /* SPI #0, #1 interrupt */
73 UART_0_1_2_OVF_IRQn = 12, /* UART overflow (0, 1 & 2) interrupt */
74 ETHERNET_IRQn = 13, /* Ethernet interrupt */
75 I2S_IRQn = 14, /* Audio I2S interrupt */
76 TOUCHSCREEN_IRQn = 15, /* Touch Screen interrupt */
77 GPIO2_IRQn = 16, /* GPIO 2 combined interrupt */
78 GPIO3_IRQn = 17, /* GPIO 3 combined interrupt */
79 UART3RX_IRQn = 18, /* UART 3 receive interrupt */
80 UART3TX_IRQn = 19, /* UART 3 transmit interrupt */
81 UART4RX_IRQn = 20, /* UART 4 receive interrupt */
82 UART4TX_IRQn = 21, /* UART 4 transmit interrupt */
83 SPI_2_IRQn = 22, /* SPI #2 interrupt */
84 SPI_3_4_IRQn = 23, /* SPI #3, SPI #4 interrupt */
85 GPIO0_0_IRQn = 24, /* GPIO 0 individual interrupt ( 0) */
86 GPIO0_1_IRQn = 25, /* GPIO 0 individual interrupt ( 1) */
87 GPIO0_2_IRQn = 26, /* GPIO 0 individual interrupt ( 2) */
88 GPIO0_3_IRQn = 27, /* GPIO 0 individual interrupt ( 3) */
89 GPIO0_4_IRQn = 28, /* GPIO 0 individual interrupt ( 4) */
90 GPIO0_5_IRQn = 29, /* GPIO 0 individual interrupt ( 5) */
91 GPIO0_6_IRQn = 30, /* GPIO 0 individual interrupt ( 6) */
92 GPIO0_7_IRQn = 31, /* GPIO 0 individual interrupt ( 7) */
93 GPIO1_0_IRQn = 32, /* GPIO 1 individual interrupt ( 0) */
94 GPIO1_1_IRQn = 33, /* GPIO 1 individual interrupt ( 1) */
95 GPIO1_2_IRQn = 34, /* GPIO 1 individual interrupt ( 2) */
96 GPIO1_3_IRQn = 35, /* GPIO 1 individual interrupt ( 3) */
97 GPIO1_4_IRQn = 36, /* GPIO 1 individual interrupt ( 4) */
98 GPIO1_5_IRQn = 37, /* GPIO 1 individual interrupt ( 5) */
99 GPIO1_6_IRQn = 38, /* GPIO 1 individual interrupt ( 6) */
100 GPIO1_7_IRQn = 39, /* GPIO 1 individual interrupt ( 7) */
101 GPIO1_8_IRQn = 40, /* GPIO 1 individual interrupt ( 0) */
102 GPIO1_9_IRQn = 41, /* GPIO 1 individual interrupt ( 9) */
103 GPIO1_10_IRQn = 42, /* GPIO 1 individual interrupt (10) */
104 GPIO1_11_IRQn = 43, /* GPIO 1 individual interrupt (11) */
105 GPIO1_12_IRQn = 44, /* GPIO 1 individual interrupt (12) */
106 GPIO1_13_IRQn = 45, /* GPIO 1 individual interrupt (13) */
107 GPIO1_14_IRQn = 46, /* GPIO 1 individual interrupt (14) */
108 GPIO1_15_IRQn = 47, /* GPIO 1 individual interrupt (15) */
109 SPI_0B_IRQn = 48, /* SPI #0 interrupt */
110 Reserved_IRQn = 49, /* Reserved */
111 SECURETIMER0_IRQn = 50, /* Secure Timer 0 interrupt */
112 SECURETIMER1_IRQn = 51, /* Secure Timer 1 interrupt */
113 SPI_1B_IRQn = 52, /* SPI #1 interrupt */
114 SPI_2B_IRQn = 53, /* SPI #2 interrupt */
115 SPI_3B_IRQn = 54, /* SPI #3 interrupt */
116 SPI_4B_IRQn = 55 /* SPI #4 interrupt */
117} IRQn_Type;
118
119
120/* ================================================================================ */
121/* ================ Processor and Core Peripheral Section ================ */
122/* ================================================================================ */
123
124/* ------- Start of section using anonymous unions and disabling warnings ------- */
125#if defined (__CC_ARM)
126 #pragma push
127 #pragma anon_unions
128#elif defined (__ICCARM__)
129 #pragma language=extended
130#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
131 #pragma clang diagnostic push
132 #pragma clang diagnostic ignored "-Wc11-extensions"
133 #pragma clang diagnostic ignored "-Wreserved-id-macro"
134#elif defined (__GNUC__)
135 /* anonymous unions are enabled by default */
136#elif defined (__TMS470__)
137 /* anonymous unions are enabled by default */
138#elif defined (__TASKING__)
139 #pragma warning 586
140#elif defined (__CSMC__)
141 /* anonymous unions are enabled by default */
142#else
143 #warning Not supported compiler type
144#endif
145
146
147/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
148#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
149#define __SAUREGION_PRESENT 1U /* SAU regions are present */
150#define __MPU_PRESENT 1U /* MPU present */
151#define __VTOR_PRESENT 1U /* VTOR present */
152#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
153#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
154
155#include "core_armv8mbl.h" /* Processor and core peripherals */
156#include "system_CMSDK_ARMv8MBL.h" /* System Header */
157
158
159/* ================================================================================ */
160/* ================ Device Specific Peripheral Section ================ */
161/* ================================================================================ */
162
163/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
164typedef struct
165{
166 __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
167 __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
168 __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
169 union {
170 __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
171 __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
172 };
173 __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
174
175} CMSDK_UART_TypeDef;
176
177/* CMSDK_UART DATA Register Definitions */
178#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
179#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
180
181/* CMSDK_UART STATE Register Definitions */
182#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
183#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
184
185#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
186#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
187
188#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
189#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
190
191#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
192#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
193
194/* CMSDK_UART CTRL Register Definitions */
195#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
196#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
197
198#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
199#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
200
201#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
202#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
203
204#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
205#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
206
207#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
208#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
209
210#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
211#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
212
213#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
214#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
215
216#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
217#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
218
219#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
220#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
221
222#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
223#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
224
225#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
226#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
227
228/* CMSDK_UART BAUDDIV Register Definitions */
229#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
230#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
231
232
233/*----------------------------- Timer (TIMER) -------------------------------*/
234typedef struct
235{
236 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
237 __IOM uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
238 __IOM uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
239 union {
240 __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
241 __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
242 };
243
244} CMSDK_TIMER_TypeDef;
245
246/* CMSDK_TIMER CTRL Register Definitions */
247#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
248#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
249
250#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
251#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
252
253#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
254#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
255
256#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
257#define CMSDK_TIMER_CTRL_EN_Msk (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */
258
259/* CMSDK_TIMER VAL Register Definitions */
260#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
261#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */
262
263/* CMSDK_TIMER RELOAD Register Definitions */
264#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
265#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */
266
267/* CMSDK_TIMER INTSTATUS Register Definitions */
268#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
269#define CMSDK_TIMER_INTSTATUS_Msk (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
270
271/* CMSDK_TIMER INTCLEAR Register Definitions */
272#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
273#define CMSDK_TIMER_INTCLEAR_Msk (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
274
275
276/*------------- Timer (TIM) --------------------------------------------------*/
277typedef struct
278{
279 __IOM uint32_t T1LOAD; /* Offset: 0x000 (R/W) Timer 1 Load */
280 __IM uint32_t T1VALUE; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
281 __IOM uint32_t T1CTRL; /* Offset: 0x008 (R/W) Timer 1 Control */
282 __OM uint32_t T1INTCLR; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
283 __IM uint32_t T1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
284 __IM uint32_t T1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
285 __IOM uint32_t T1BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */
286 uint32_t RESERVED0;
287 __IOM uint32_t T2LOAD; /* Offset: 0x020 (R/W) Timer 2 Load */
288 __IM uint32_t T2VALUE; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
289 __IOM uint32_t T2CTRL; /* Offset: 0x028 (R/W) Timer 2 Control */
290 __OM uint32_t T2INTCLR; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
291 __IM uint32_t T2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
292 __IM uint32_t T2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
293 __IOM uint32_t T2BGLOAD; /* Offset: 0x038 (R/W) Background Load Register */
294 uint32_t RESERVED1[945];
295 __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
296 __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
297} CMSDK_DUALTIMER_BOTH_TypeDef;
298
299
300typedef struct
301{
302 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Timer Load */
303 __IM uint32_t VALUE; /* Offset: 0x000 (R/W) Timer Counter Current Value */
304 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Timer Control */
305 __OM uint32_t INTCLR; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
306 __IM uint32_t RIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
307 __IM uint32_t MIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
308 __IOM uint32_t BGLOAD; /* Offset: 0x000 (R/W) Background Load Register */
309} CMSDK_DUALTIMER_SINGLE_TypeDef;
310
311/* CMSDK_DUALTIMER_SINGLE LOAD Register Definitions */
312#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
313#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
314
315/* CMSDK_DUALTIMER_SINGLE VALUE Register Definitions */
316#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
317#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
318
319/* CMSDK_DUALTIMER_SINGLE CTRL Register Definitions */
320#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
321#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
322
323#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
324#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
325
326#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
327#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
328
329#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
330#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
331
332#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
333#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
334
335#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
336#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
337
338/* CMSDK_DUALTIMER_SINGLE INTCLR Register Definitions */
339#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
340#define CMSDK_DUALTIMER_INTCLR_Msk (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
341
342/* CMSDK_DUALTIMER_SINGLE RIS Register Definitions */
343#define CMSDK_DUALTIMER_RIS_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
344#define CMSDK_DUALTIMER_RIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
345
346/* CMSDK_DUALTIMER_SINGLE MIS Register Definitions */
347#define CMSDK_DUALTIMER_MIS_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
348#define CMSDK_DUALTIMER_MIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
349
350/* CMSDK_DUALTIMER_SINGLE BGLOAD Register Definitions */
351#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
352#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
353
354
355/*-------------------- General Purpose Input Output (GPIO) -------------------*/
356typedef struct
357{
358 __IOM uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
359 __IOM uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
360 uint32_t RESERVED0[2];
361 __IOM uint32_t OUTENSET; /* Offset: 0x010 (R/W) Output Enable Set Register */
362 __IOM uint32_t OUTENCLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
363 __IOM uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
364 __IOM uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
365 __IOM uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
366 __IOM uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
367 __IOM uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
368 __IOM uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
369 __IOM uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
370 __IOM uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
371 union {
372 __IM uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
373 __OM uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
374 };
375 uint32_t RESERVED1[241];
376 __IOM uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
377 __IOM uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
378} CMSDK_GPIO_TypeDef;
379
380/* CMSDK_GPIO DATA Register Definitions */
381#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
382#define CMSDK_GPIO_DATA_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */
383
384/* CMSDK_GPIO DATAOUT Register Definitions */
385#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
386#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
387
388/* CMSDK_GPIO OUTENSET Register Definitions */
389#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
390#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
391
392/* CMSDK_GPIO OUTENCLR Register Definitions */
393#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
394#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
395
396/* CMSDK_GPIO ALTFUNCSET Register Definitions */
397#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
398#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
399
400/* CMSDK_GPIO ALTFUNCCLR Register Definitions */
401#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
402#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
403
404/* CMSDK_GPIO INTENSET Register Definitions */
405#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
406#define CMSDK_GPIO_INTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
407
408/* CMSDK_GPIO INTENCLR Register Definitions */
409#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
410#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
411
412/* CMSDK_GPIO INTTYPESET Register Definitions */
413#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
414#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
415
416/* CMSDK_GPIO INTTYPECLR Register Definitions */
417#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
418#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
419
420/* CMSDK_GPIO INTPOLSET Register Definitions */
421#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
422#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
423
424/* CMSDK_GPIO INTPOLCLR Register Definitions */
425#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
426#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
427
428/* CMSDK_GPIO INTCLEAR Register Definitions */
429#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
430#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
431
432/* CMSDK_GPIO INTCLEAR Register Definitions */
433#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
434#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
435
436/* CMSDK_GPIO MASKLOWBYTE Register Definitions */
437#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
438#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
439
440/* CMSDK_GPIO MASKHIGHBYTE Register Definitions */
441#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
442#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
443
444
445/*------------- System Control (SYSCON) --------------------------------------*/
446typedef struct
447{
448 __IOM uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
449 __IOM uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
450 __IOM uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
451 __IOM uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
452 __IOM uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
453} CMSDK_SYSCON_TypeDef;
454
455/* CMSDK_SYSCON REMAP Register Definitions */
456#define CMSDK_SYSCON_REMAP_Pos 0
457#define CMSDK_SYSCON_REMAP_Msk (0x1UL /*<< CMSDK_SYSCON_REMAP_Pos*/) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
458
459/* CMSDK_SYSCON PMUCTRL Register Definitions */
460#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
461#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x1UL /*<< CMSDK_SYSCON_PMUCTRL_EN_Pos*/) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
462
463/* CMSDK_SYSCON LOCKUPRST Register Definitions */
464#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
465#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x1UL /*<< CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos*/) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
466
467/* CMSDK_SYSCON EMICTRL Register Definitions */
468#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
469#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
470
471#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
472#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
473
474#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
475#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
476
477#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
478#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x7UL /*<< CMSDK_SYSCON_EMICTRL_RCYC_Pos*/) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
479
480/* CMSDK_SYSCON RSTINFO Register Definitions */
481#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
482#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
483
484#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
485#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
486
487#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
488#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x1UL /*<< CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos*/) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
489
490
491/*------------------- Watchdog ----------------------------------------------*/
492typedef struct
493{
494
495 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
496 __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
497 __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
498 __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
499 __IM uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
500 __IM uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
501 uint32_t RESERVED0[762];
502 __IOM uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
503 uint32_t RESERVED1[191];
504 __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
505 __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
506}CMSDK_WATCHDOG_TypeDef;
507
508/* CMSDK_WATCHDOG LOAD Register Definitions */
509#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
510#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */
511
512/* CMSDK_WATCHDOG VALUE Register Definitions */
513#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
514#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */
515
516/* CMSDK_WATCHDOG CTRL Register Definitions */
517#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
518#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
519
520#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
521#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
522
523/* CMSDK_WATCHDOG INTCLR Register Definitions */
524#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
525#define CMSDK_Watchdog_INTCLR_Msk (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
526
527/* CMSDK_WATCHDOG RAWINTSTAT Register Definitions */
528#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
529#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
530
531/* CMSDK_WATCHDOG MASKINTSTAT Register Definitions */
532#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
533#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
534
535/* CMSDK_WATCHDOG LOCK Register Definitions */
536#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
537#define CMSDK_Watchdog_LOCK_Msk (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */
538
539/* CMSDK_WATCHDOG INTEGTESTEN Register Definitions */
540#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
541#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
542
543/* CMSDK_WATCHDOG INTEGTESTOUTSET Register Definitions */
544#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
545#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
546
547
548
549/* -------------------- End of section using anonymous unions ------------------- */
550#if defined (__CC_ARM)
551 #pragma pop
552#elif defined (__ICCARM__)
553 /* leave anonymous unions enabled */
554#elif (__ARMCC_VERSION >= 6010050)
555 #pragma clang diagnostic pop
556#elif defined (__GNUC__)
557 /* anonymous unions are enabled by default */
558#elif defined (__TMS470__)
559 /* anonymous unions are enabled by default */
560#elif defined (__TASKING__)
561 #pragma warning restore
562#elif defined (__CSMC__)
563 /* anonymous unions are enabled by default */
564#else
565 #warning Not supported compiler type
566#endif
567
568
569
570
571/* ================================================================================ */
572/* ================ Peripheral memory map ================ */
573/* ================================================================================ */
574
575/* Peripheral and SRAM base address */
576#define CMSDK_FLASH_BASE (0x00000000UL)
577#define CMSDK_SRAM_BASE (0x20000000UL)
578#define CMSDK_PERIPH_BASE (0x40000000UL)
579
580#define CMSDK_RAM_BASE (0x20000000UL)
581#define CMSDK_APB_BASE (0x40000000UL)
582#define CMSDK_AHB_BASE (0x40010000UL)
583#define CMSDK_S_APB_BASE (0x50000000UL)
584
585/* APB peripherals */
586#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
587#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
588#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
589#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
590#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
591#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
592#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
593#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
594#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
595
596/* AHB peripherals */
597#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
598#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
599#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
600
601/* Secure APB peripherals */
602#define CMSDK_SECURETIMER0_BASE (CMSDK_S_APB_BASE + 0x0000UL)
603#define CMSDK_SECURETIMER1_BASE (CMSDK_S_APB_BASE + 0x1000UL)
604
605
606/* ================================================================================ */
607/* ================ Peripheral declaration ================ */
608/* ================================================================================ */
609
610#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
611#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
612#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
613#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
614#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
615#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
616#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
617#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
618#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
619#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
620#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
621#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
622#define CMSDK_SECURETIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER0_BASE)
623#define CMSDK_SECURETIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER1_BASE)
624
625
626#ifdef __cplusplus
627}
628#endif
629
630#endif /* CMSDK_ARMv8MBL_H */
IRQn_Type
enum IRQn IRQn_Type
SPI_0B_IRQn
@ SPI_0B_IRQn
Definition CMSDK_ARMv8MBL.h:109
GPIO2_IRQn
@ GPIO2_IRQn
Definition CMSDK_ARMv8MBL.h:77
GPIO1_14_IRQn
@ GPIO1_14_IRQn
Definition CMSDK_ARMv8MBL.h:107
PendSV_IRQn
@ PendSV_IRQn
Definition CMSDK_ARMv8MBL.h:57
UART4TX_IRQn
@ UART4TX_IRQn
Definition CMSDK_ARMv8MBL.h:82
TIMER1_IRQn
@ TIMER1_IRQn
Definition CMSDK_ARMv8MBL.h:70
UART2RX_IRQn
@ UART2RX_IRQn
Definition CMSDK_ARMv8MBL.h:65
I2S_IRQn
@ I2S_IRQn
Definition CMSDK_ARMv8MBL.h:75
UART4RX_IRQn
@ UART4RX_IRQn
Definition CMSDK_ARMv8MBL.h:81
SECURETIMER0_IRQn
@ SECURETIMER0_IRQn
Definition CMSDK_ARMv8MBL.h:111
UART2TX_IRQn
@ UART2TX_IRQn
Definition CMSDK_ARMv8MBL.h:66
TIMER0_IRQn
@ TIMER0_IRQn
Definition CMSDK_ARMv8MBL.h:69
UART3TX_IRQn
@ UART3TX_IRQn
Definition CMSDK_ARMv8MBL.h:80
GPIO1_6_IRQn
@ GPIO1_6_IRQn
Definition CMSDK_ARMv8MBL.h:99
GPIO0_6_IRQn
@ GPIO0_6_IRQn
Definition CMSDK_ARMv8MBL.h:91
SPI_3B_IRQn
@ SPI_3B_IRQn
Definition CMSDK_ARMv8MBL.h:115
SPI_4B_IRQn
@ SPI_4B_IRQn
Definition CMSDK_ARMv8MBL.h:116
SVCall_IRQn
@ SVCall_IRQn
Definition CMSDK_ARMv8MBL.h:55
GPIO1_10_IRQn
@ GPIO1_10_IRQn
Definition CMSDK_ARMv8MBL.h:103
UART0TX_IRQn
@ UART0TX_IRQn
Definition CMSDK_ARMv8MBL.h:62
GPIO1_5_IRQn
@ GPIO1_5_IRQn
Definition CMSDK_ARMv8MBL.h:98
GPIO0_2_IRQn
@ GPIO0_2_IRQn
Definition CMSDK_ARMv8MBL.h:87
GPIO3_IRQn
@ GPIO3_IRQn
Definition CMSDK_ARMv8MBL.h:78
SPI_2B_IRQn
@ SPI_2B_IRQn
Definition CMSDK_ARMv8MBL.h:114
GPIO1ALL_IRQn
@ GPIO1ALL_IRQn
Definition CMSDK_ARMv8MBL.h:68
GPIO1_13_IRQn
@ GPIO1_13_IRQn
Definition CMSDK_ARMv8MBL.h:106
UART_0_1_2_OVF_IRQn
@ UART_0_1_2_OVF_IRQn
Definition CMSDK_ARMv8MBL.h:73
SysTick_IRQn
@ SysTick_IRQn
Definition CMSDK_ARMv8MBL.h:58
GPIO1_1_IRQn
@ GPIO1_1_IRQn
Definition CMSDK_ARMv8MBL.h:94
GPIO0_3_IRQn
@ GPIO0_3_IRQn
Definition CMSDK_ARMv8MBL.h:88
ETHERNET_IRQn
@ ETHERNET_IRQn
Definition CMSDK_ARMv8MBL.h:74
GPIO1_7_IRQn
@ GPIO1_7_IRQn
Definition CMSDK_ARMv8MBL.h:100
UART1TX_IRQn
@ UART1TX_IRQn
Definition CMSDK_ARMv8MBL.h:64
GPIO1_4_IRQn
@ GPIO1_4_IRQn
Definition CMSDK_ARMv8MBL.h:97
GPIO1_11_IRQn
@ GPIO1_11_IRQn
Definition CMSDK_ARMv8MBL.h:104
GPIO0ALL_IRQn
@ GPIO0ALL_IRQn
Definition CMSDK_ARMv8MBL.h:67
GPIO0_5_IRQn
@ GPIO0_5_IRQn
Definition CMSDK_ARMv8MBL.h:90
UART0RX_IRQn
@ UART0RX_IRQn
Definition CMSDK_ARMv8MBL.h:61
GPIO1_12_IRQn
@ GPIO1_12_IRQn
Definition CMSDK_ARMv8MBL.h:105
HardFault_IRQn
@ HardFault_IRQn
Definition CMSDK_ARMv8MBL.h:50
GPIO0_4_IRQn
@ GPIO0_4_IRQn
Definition CMSDK_ARMv8MBL.h:89
DUALTIMER_IRQn
@ DUALTIMER_IRQn
Definition CMSDK_ARMv8MBL.h:71
GPIO1_0_IRQn
@ GPIO1_0_IRQn
Definition CMSDK_ARMv8MBL.h:93
GPIO1_9_IRQn
@ GPIO1_9_IRQn
Definition CMSDK_ARMv8MBL.h:102
GPIO0_1_IRQn
@ GPIO0_1_IRQn
Definition CMSDK_ARMv8MBL.h:86
GPIO1_3_IRQn
@ GPIO1_3_IRQn
Definition CMSDK_ARMv8MBL.h:96
SPI_1B_IRQn
@ SPI_1B_IRQn
Definition CMSDK_ARMv8MBL.h:113
TOUCHSCREEN_IRQn
@ TOUCHSCREEN_IRQn
Definition CMSDK_ARMv8MBL.h:76
GPIO1_8_IRQn
@ GPIO1_8_IRQn
Definition CMSDK_ARMv8MBL.h:101
GPIO1_2_IRQn
@ GPIO1_2_IRQn
Definition CMSDK_ARMv8MBL.h:95
SPI_3_4_IRQn
@ SPI_3_4_IRQn
Definition CMSDK_ARMv8MBL.h:84
SECURETIMER1_IRQn
@ SECURETIMER1_IRQn
Definition CMSDK_ARMv8MBL.h:112
Reserved_IRQn
@ Reserved_IRQn
Definition CMSDK_ARMv8MBL.h:110
UART1RX_IRQn
@ UART1RX_IRQn
Definition CMSDK_ARMv8MBL.h:63
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition CMSDK_ARMv8MBL.h:49
GPIO0_7_IRQn
@ GPIO0_7_IRQn
Definition CMSDK_ARMv8MBL.h:92
SPI_2_IRQn
@ SPI_2_IRQn
Definition CMSDK_ARMv8MBL.h:83
SPI_0_1_IRQn
@ SPI_0_1_IRQn
Definition CMSDK_ARMv8MBL.h:72
GPIO1_15_IRQn
@ GPIO1_15_IRQn
Definition CMSDK_ARMv8MBL.h:108
UART3RX_IRQn
@ UART3RX_IRQn
Definition CMSDK_ARMv8MBL.h:79
GPIO0_0_IRQn
@ GPIO0_0_IRQn
Definition CMSDK_ARMv8MBL.h:85
IRQn
IRQn
Definition f1c100s_reg.h:1131
__OM
#define __OM
Definition i_reg_gpio.h:47
__IM
#define __IM
Definition i_reg_gpio.h:42
__IOM
#define __IOM
Definition i_reg_gpio.h:52
uint32_t
unsigned uint32_t
Definition stdint.h:9
CMSDK_DUALTIMER_BOTH_TypeDef
Definition CMSDK_ARMv8MBL.h:278
CMSDK_DUALTIMER_BOTH_TypeDef::T2VALUE
__IM uint32_t T2VALUE
Definition CMSDK_ARMv8MBL.h:288
CMSDK_DUALTIMER_BOTH_TypeDef::T1CTRL
__IOM uint32_t T1CTRL
Definition CMSDK_ARMv8MBL.h:281
CMSDK_DUALTIMER_BOTH_TypeDef::T2LOAD
__IOM uint32_t T2LOAD
Definition CMSDK_ARMv8MBL.h:287
CMSDK_DUALTIMER_BOTH_TypeDef::T1MIS
__IM uint32_t T1MIS
Definition CMSDK_ARMv8MBL.h:284
CMSDK_DUALTIMER_BOTH_TypeDef::T1BGLOAD
__IOM uint32_t T1BGLOAD
Definition CMSDK_ARMv8MBL.h:285
CMSDK_DUALTIMER_BOTH_TypeDef::T2RIS
__IM uint32_t T2RIS
Definition CMSDK_ARMv8MBL.h:291
CMSDK_DUALTIMER_BOTH_TypeDef::T1VALUE
__IM uint32_t T1VALUE
Definition CMSDK_ARMv8MBL.h:280
CMSDK_DUALTIMER_BOTH_TypeDef::T1LOAD
__IOM uint32_t T1LOAD
Definition CMSDK_ARMv8MBL.h:279
CMSDK_DUALTIMER_BOTH_TypeDef::T2BGLOAD
__IOM uint32_t T2BGLOAD
Definition CMSDK_ARMv8MBL.h:293
CMSDK_DUALTIMER_BOTH_TypeDef::T2MIS
__IM uint32_t T2MIS
Definition CMSDK_ARMv8MBL.h:292
CMSDK_DUALTIMER_BOTH_TypeDef::T1INTCLR
__OM uint32_t T1INTCLR
Definition CMSDK_ARMv8MBL.h:282
CMSDK_DUALTIMER_BOTH_TypeDef::RESERVED0
uint32_t RESERVED0
Definition CMSDK_ARMv8MBL.h:286
CMSDK_DUALTIMER_BOTH_TypeDef::ITOP
__OM uint32_t ITOP
Definition CMSDK_ARMv8MBL.h:296
CMSDK_DUALTIMER_BOTH_TypeDef::T2CTRL
__IOM uint32_t T2CTRL
Definition CMSDK_ARMv8MBL.h:289
CMSDK_DUALTIMER_BOTH_TypeDef::T1RIS
__IM uint32_t T1RIS
Definition CMSDK_ARMv8MBL.h:283
CMSDK_DUALTIMER_BOTH_TypeDef::ITCR
__IOM uint32_t ITCR
Definition CMSDK_ARMv8MBL.h:295
CMSDK_DUALTIMER_BOTH_TypeDef::T2INTCLR
__OM uint32_t T2INTCLR
Definition CMSDK_ARMv8MBL.h:290
CMSDK_DUALTIMER_SINGLE_TypeDef
Definition CMSDK_ARMv8MBL.h:301
CMSDK_DUALTIMER_SINGLE_TypeDef::MIS
__IM uint32_t MIS
Definition CMSDK_ARMv8MBL.h:307
CMSDK_DUALTIMER_SINGLE_TypeDef::RIS
__IM uint32_t RIS
Definition CMSDK_ARMv8MBL.h:306
CMSDK_DUALTIMER_SINGLE_TypeDef::INTCLR
__OM uint32_t INTCLR
Definition CMSDK_ARMv8MBL.h:305
CMSDK_DUALTIMER_SINGLE_TypeDef::CTRL
__IOM uint32_t CTRL
Definition CMSDK_ARMv8MBL.h:304
CMSDK_DUALTIMER_SINGLE_TypeDef::LOAD
__IOM uint32_t LOAD
Definition CMSDK_ARMv8MBL.h:302
CMSDK_DUALTIMER_SINGLE_TypeDef::BGLOAD
__IOM uint32_t BGLOAD
Definition CMSDK_ARMv8MBL.h:308
CMSDK_DUALTIMER_SINGLE_TypeDef::VALUE
__IM uint32_t VALUE
Definition CMSDK_ARMv8MBL.h:303
CMSDK_GPIO_TypeDef
Definition CMSDK_ARMv8MBL.h:357
CMSDK_GPIO_TypeDef::INTPOLCLR
__IOM uint32_t INTPOLCLR
Definition CMSDK_ARMv8MBL.h:370
CMSDK_GPIO_TypeDef::OUTENCLR
__IOM uint32_t OUTENCLR
Definition CMSDK_ARMv8MBL.h:362
CMSDK_GPIO_TypeDef::DATA
__IOM uint32_t DATA
Definition CMSDK_ARMv8MBL.h:358
CMSDK_GPIO_TypeDef::INTTYPECLR
__IOM uint32_t INTTYPECLR
Definition CMSDK_ARMv8MBL.h:368
CMSDK_GPIO_TypeDef::INTTYPESET
__IOM uint32_t INTTYPESET
Definition CMSDK_ARMv8MBL.h:367
CMSDK_GPIO_TypeDef::INTENCLR
__IOM uint32_t INTENCLR
Definition CMSDK_ARMv8MBL.h:366
CMSDK_GPIO_TypeDef::INTSTATUS
__IM uint32_t INTSTATUS
Definition CMSDK_ARMv8MBL.h:372
CMSDK_GPIO_TypeDef::INTPOLSET
__IOM uint32_t INTPOLSET
Definition CMSDK_ARMv8MBL.h:369
CMSDK_GPIO_TypeDef::INTENSET
__IOM uint32_t INTENSET
Definition CMSDK_ARMv8MBL.h:365
CMSDK_GPIO_TypeDef::ALTFUNCSET
__IOM uint32_t ALTFUNCSET
Definition CMSDK_ARMv8MBL.h:363
CMSDK_GPIO_TypeDef::OUTENSET
__IOM uint32_t OUTENSET
Definition CMSDK_ARMv8MBL.h:361
CMSDK_GPIO_TypeDef::DATAOUT
__IOM uint32_t DATAOUT
Definition CMSDK_ARMv8MBL.h:359
CMSDK_GPIO_TypeDef::INTCLEAR
__OM uint32_t INTCLEAR
Definition CMSDK_ARMv8MBL.h:373
CMSDK_GPIO_TypeDef::ALTFUNCCLR
__IOM uint32_t ALTFUNCCLR
Definition CMSDK_ARMv8MBL.h:364
CMSDK_SYSCON_TypeDef
Definition CMSDK_ARMv8MBL.h:447
CMSDK_SYSCON_TypeDef::RSTINFO
__IOM uint32_t RSTINFO
Definition CMSDK_ARMv8MBL.h:452
CMSDK_SYSCON_TypeDef::PMUCTRL
__IOM uint32_t PMUCTRL
Definition CMSDK_ARMv8MBL.h:449
CMSDK_SYSCON_TypeDef::REMAP
__IOM uint32_t REMAP
Definition CMSDK_ARMv8MBL.h:448
CMSDK_SYSCON_TypeDef::EMICTRL
__IOM uint32_t EMICTRL
Definition CMSDK_ARMv8MBL.h:451
CMSDK_SYSCON_TypeDef::RESETOP
__IOM uint32_t RESETOP
Definition CMSDK_ARMv8MBL.h:450
CMSDK_TIMER_TypeDef
Definition CMSDK_ARMv8MBL.h:235
CMSDK_TIMER_TypeDef::VALUE
__IOM uint32_t VALUE
Definition CMSDK_ARMv8MBL.h:237
CMSDK_TIMER_TypeDef::CTRL
__IOM uint32_t CTRL
Definition CMSDK_ARMv8MBL.h:236
CMSDK_TIMER_TypeDef::RELOAD
__IOM uint32_t RELOAD
Definition CMSDK_ARMv8MBL.h:238
CMSDK_TIMER_TypeDef::INTCLEAR
__OM uint32_t INTCLEAR
Definition CMSDK_ARMv8MBL.h:241
CMSDK_TIMER_TypeDef::INTSTATUS
__IM uint32_t INTSTATUS
Definition CMSDK_ARMv8MBL.h:240
CMSDK_UART_TypeDef
Definition CMSDK_ARMv8MBL.h:165
CMSDK_UART_TypeDef::DATA
__IOM uint32_t DATA
Definition CMSDK_ARMv8MBL.h:166
CMSDK_UART_TypeDef::STATE
__IOM uint32_t STATE
Definition CMSDK_ARMv8MBL.h:167
CMSDK_UART_TypeDef::INTSTATUS
__IM uint32_t INTSTATUS
Definition CMSDK_ARMv8MBL.h:170
CMSDK_UART_TypeDef::INTCLEAR
__OM uint32_t INTCLEAR
Definition CMSDK_ARMv8MBL.h:171
CMSDK_UART_TypeDef::CTRL
__IOM uint32_t CTRL
Definition CMSDK_ARMv8MBL.h:168
CMSDK_UART_TypeDef::BAUDDIV
__IOM uint32_t BAUDDIV
Definition CMSDK_ARMv8MBL.h:173
CMSDK_WATCHDOG_TypeDef
Definition CMSDK_ARMv8MBL.h:493
CMSDK_WATCHDOG_TypeDef::LOCK
__IOM uint32_t LOCK
Definition CMSDK_ARMv8MBL.h:502
CMSDK_WATCHDOG_TypeDef::INTCLR
__OM uint32_t INTCLR
Definition CMSDK_ARMv8MBL.h:498
CMSDK_WATCHDOG_TypeDef::ITCR
__IOM uint32_t ITCR
Definition CMSDK_ARMv8MBL.h:504
CMSDK_WATCHDOG_TypeDef::ITOP
__OM uint32_t ITOP
Definition CMSDK_ARMv8MBL.h:505
CMSDK_WATCHDOG_TypeDef::LOAD
__IOM uint32_t LOAD
Definition CMSDK_ARMv8MBL.h:495
CMSDK_WATCHDOG_TypeDef::RAWINTSTAT
__IM uint32_t RAWINTSTAT
Definition CMSDK_ARMv8MBL.h:499
CMSDK_WATCHDOG_TypeDef::VALUE
__IM uint32_t VALUE
Definition CMSDK_ARMv8MBL.h:496
CMSDK_WATCHDOG_TypeDef::MASKINTSTAT
__IM uint32_t MASKINTSTAT
Definition CMSDK_ARMv8MBL.h:500
CMSDK_WATCHDOG_TypeDef::CTRL
__IOM uint32_t CTRL
Definition CMSDK_ARMv8MBL.h:497
system_CMSDK_ARMv8MBL.h
CMSIS Device System Header File for CMSDK_ARMv8MBL Device.
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