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Data Structures | Macros | Typedefs | Enumerations
CMSDK_ARMv8MBL.h File Reference

CMSIS Core Peripheral Access Layer Header File for CMSDK_ARMv8MBL Device. More...

#include "core_armv8mbl.h"
#include "system_CMSDK_ARMv8MBL.h"

Go to the source code of this file.

Data Structures

struct  CMSDK_UART_TypeDef
 
struct  CMSDK_TIMER_TypeDef
 
struct  CMSDK_DUALTIMER_BOTH_TypeDef
 
struct  CMSDK_DUALTIMER_SINGLE_TypeDef
 
struct  CMSDK_GPIO_TypeDef
 
struct  CMSDK_SYSCON_TypeDef
 
struct  CMSDK_WATCHDOG_TypeDef
 

Macros

#define __ARMv8MBL_REV   0x0000U /* Core revision r0p0 */
 
#define __SAUREGION_PRESENT   1U /* SAU regions are present */
 
#define __MPU_PRESENT   1U /* MPU present */
 
#define __VTOR_PRESENT   1U /* VTOR present */
 
#define __NVIC_PRIO_BITS   2U /* Number of Bits used for Priority Levels */
 
#define __Vendor_SysTickConfig   0U /* Set to 1 if different SysTick Config is used */
 
#define CMSDK_UART_DATA_Pos   0 /* CMSDK_UART_DATA_Pos: DATA Position */
 
#define CMSDK_UART_DATA_Msk   (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
 
#define CMSDK_UART_STATE_RXOR_Pos   3 /* CMSDK_UART STATE: RXOR Position */
 
#define CMSDK_UART_STATE_RXOR_Msk   (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
 
#define CMSDK_UART_STATE_TXOR_Pos   2 /* CMSDK_UART STATE: TXOR Position */
 
#define CMSDK_UART_STATE_TXOR_Msk   (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
 
#define CMSDK_UART_STATE_RXBF_Pos   1 /* CMSDK_UART STATE: RXBF Position */
 
#define CMSDK_UART_STATE_RXBF_Msk   (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
 
#define CMSDK_UART_STATE_TXBF_Pos   0 /* CMSDK_UART STATE: TXBF Position */
 
#define CMSDK_UART_STATE_TXBF_Msk   (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
 
#define CMSDK_UART_CTRL_HSTM_Pos   6 /* CMSDK_UART CTRL: HSTM Position */
 
#define CMSDK_UART_CTRL_HSTM_Msk   (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
 
#define CMSDK_UART_CTRL_RXORIRQEN_Pos   5 /* CMSDK_UART CTRL: RXORIRQEN Position */
 
#define CMSDK_UART_CTRL_RXORIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
 
#define CMSDK_UART_CTRL_TXORIRQEN_Pos   4 /* CMSDK_UART CTRL: TXORIRQEN Position */
 
#define CMSDK_UART_CTRL_TXORIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
 
#define CMSDK_UART_CTRL_RXIRQEN_Pos   3 /* CMSDK_UART CTRL: RXIRQEN Position */
 
#define CMSDK_UART_CTRL_RXIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
 
#define CMSDK_UART_CTRL_TXIRQEN_Pos   2 /* CMSDK_UART CTRL: TXIRQEN Position */
 
#define CMSDK_UART_CTRL_TXIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
 
#define CMSDK_UART_CTRL_RXEN_Pos   1 /* CMSDK_UART CTRL: RXEN Position */
 
#define CMSDK_UART_CTRL_RXEN_Msk   (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
 
#define CMSDK_UART_CTRL_TXEN_Pos   0 /* CMSDK_UART CTRL: TXEN Position */
 
#define CMSDK_UART_CTRL_TXEN_Msk   (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
 
#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos   3 /* CMSDK_UART CTRL: RXORIRQ Position */
 
#define CMSDK_UART_CTRL_RXORIRQ_Msk   (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
 
#define CMSDK_UART_CTRL_TXORIRQ_Pos   2 /* CMSDK_UART CTRL: TXORIRQ Position */
 
#define CMSDK_UART_CTRL_TXORIRQ_Msk   (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
 
#define CMSDK_UART_CTRL_RXIRQ_Pos   1 /* CMSDK_UART CTRL: RXIRQ Position */
 
#define CMSDK_UART_CTRL_RXIRQ_Msk   (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
 
#define CMSDK_UART_CTRL_TXIRQ_Pos   0 /* CMSDK_UART CTRL: TXIRQ Position */
 
#define CMSDK_UART_CTRL_TXIRQ_Msk   (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
 
#define CMSDK_UART_BAUDDIV_Pos   0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
 
#define CMSDK_UART_BAUDDIV_Msk   (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
 
#define CMSDK_TIMER_CTRL_IRQEN_Pos   3 /* CMSDK_TIMER CTRL: IRQEN Position */
 
#define CMSDK_TIMER_CTRL_IRQEN_Msk   (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
 
#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos   2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
 
#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk   (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
 
#define CMSDK_TIMER_CTRL_SELEXTEN_Pos   1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
 
#define CMSDK_TIMER_CTRL_SELEXTEN_Msk   (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
 
#define CMSDK_TIMER_CTRL_EN_Pos   0 /* CMSDK_TIMER CTRL: EN Position */
 
#define CMSDK_TIMER_CTRL_EN_Msk   (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */
 
#define CMSDK_TIMER_VAL_CURRENT_Pos   0 /* CMSDK_TIMER VALUE: CURRENT Position */
 
#define CMSDK_TIMER_VAL_CURRENT_Msk   (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */
 
#define CMSDK_TIMER_RELOAD_VAL_Pos   0 /* CMSDK_TIMER RELOAD: RELOAD Position */
 
#define CMSDK_TIMER_RELOAD_VAL_Msk   (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */
 
#define CMSDK_TIMER_INTSTATUS_Pos   0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
 
#define CMSDK_TIMER_INTSTATUS_Msk   (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
 
#define CMSDK_TIMER_INTCLEAR_Pos   0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
 
#define CMSDK_TIMER_INTCLEAR_Msk   (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
 
#define CMSDK_DUALTIMER_LOAD_Pos   0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
 
#define CMSDK_DUALTIMER_LOAD_Msk   (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
 
#define CMSDK_DUALTIMER_VALUE_Pos   0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
 
#define CMSDK_DUALTIMER_VALUE_Msk   (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
 
#define CMSDK_DUALTIMER_CTRL_EN_Pos   7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
 
#define CMSDK_DUALTIMER_CTRL_EN_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
 
#define CMSDK_DUALTIMER_CTRL_MODE_Pos   6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
 
#define CMSDK_DUALTIMER_CTRL_MODE_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
 
#define CMSDK_DUALTIMER_CTRL_INTEN_Pos   5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
 
#define CMSDK_DUALTIMER_CTRL_INTEN_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
 
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos   2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
 
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk   (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
 
#define CMSDK_DUALTIMER_CTRL_SIZE_Pos   1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
 
#define CMSDK_DUALTIMER_CTRL_SIZE_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
 
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos   0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
 
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk   (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
 
#define CMSDK_DUALTIMER_INTCLR_Pos   0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
 
#define CMSDK_DUALTIMER_INTCLR_Msk   (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
 
#define CMSDK_DUALTIMER_RIS_Pos   0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
 
#define CMSDK_DUALTIMER_RIS_Msk   (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
 
#define CMSDK_DUALTIMER_MIS_Pos   0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
 
#define CMSDK_DUALTIMER_MIS_Msk   (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
 
#define CMSDK_DUALTIMER_BGLOAD_Pos   0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
 
#define CMSDK_DUALTIMER_BGLOAD_Msk   (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
 
#define CMSDK_GPIO_DATA_Pos   0 /* CMSDK_GPIO DATA: DATA Position */
 
#define CMSDK_GPIO_DATA_Msk   (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */
 
#define CMSDK_GPIO_DATAOUT_Pos   0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
 
#define CMSDK_GPIO_DATAOUT_Msk   (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
 
#define CMSDK_GPIO_OUTENSET_Pos   0 /* CMSDK_GPIO OUTEN: OUTEN Position */
 
#define CMSDK_GPIO_OUTENSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
 
#define CMSDK_GPIO_OUTENCLR_Pos   0 /* CMSDK_GPIO OUTEN: OUTEN Position */
 
#define CMSDK_GPIO_OUTENCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */
 
#define CMSDK_GPIO_ALTFUNCSET_Pos   0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
 
#define CMSDK_GPIO_ALTFUNCSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
 
#define CMSDK_GPIO_ALTFUNCCLR_Pos   0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
 
#define CMSDK_GPIO_ALTFUNCCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
 
#define CMSDK_GPIO_INTENSET_Pos   0 /* CMSDK_GPIO INTEN: INTEN Position */
 
#define CMSDK_GPIO_INTENSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
 
#define CMSDK_GPIO_INTENCLR_Pos   0 /* CMSDK_GPIO INTEN: INTEN Position */
 
#define CMSDK_GPIO_INTENCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */
 
#define CMSDK_GPIO_INTTYPESET_Pos   0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
 
#define CMSDK_GPIO_INTTYPESET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
 
#define CMSDK_GPIO_INTTYPECLR_Pos   0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
 
#define CMSDK_GPIO_INTTYPECLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
 
#define CMSDK_GPIO_INTPOLSET_Pos   0 /* CMSDK_GPIO INTPOL: INTPOL Position */
 
#define CMSDK_GPIO_INTPOLSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
 
#define CMSDK_GPIO_INTPOLCLR_Pos   0 /* CMSDK_GPIO INTPOL: INTPOL Position */
 
#define CMSDK_GPIO_INTPOLCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */
 
#define CMSDK_GPIO_INTSTATUS_Pos   0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
 
#define CMSDK_GPIO_INTCLEAR_Msk   (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
 
#define CMSDK_GPIO_INTCLEAR_Pos   0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
 
#define CMSDK_GPIO_INTCLEAR_Msk   (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
 
#define CMSDK_GPIO_MASKLOWBYTE_Pos   0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
 
#define CMSDK_GPIO_MASKLOWBYTE_Msk   (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
 
#define CMSDK_GPIO_MASKHIGHBYTE_Pos   0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
 
#define CMSDK_GPIO_MASKHIGHBYTE_Msk   (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
 
#define CMSDK_SYSCON_REMAP_Pos   0
 
#define CMSDK_SYSCON_REMAP_Msk   (0x1UL /*<< CMSDK_SYSCON_REMAP_Pos*/) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
 
#define CMSDK_SYSCON_PMUCTRL_EN_Pos   0
 
#define CMSDK_SYSCON_PMUCTRL_EN_Msk   (0x1UL /*<< CMSDK_SYSCON_PMUCTRL_EN_Pos*/) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
 
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos   0
 
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk   (0x1UL /*<< CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos*/) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
 
#define CMSDK_SYSCON_EMICTRL_SIZE_Pos   24
 
#define CMSDK_SYSCON_EMICTRL_SIZE_Msk   (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
 
#define CMSDK_SYSCON_EMICTRL_TACYC_Pos   16
 
#define CMSDK_SYSCON_EMICTRL_TACYC_Msk   (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
 
#define CMSDK_SYSCON_EMICTRL_WCYC_Pos   8
 
#define CMSDK_SYSCON_EMICTRL_WCYC_Msk   (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
 
#define CMSDK_SYSCON_EMICTRL_RCYC_Pos   0
 
#define CMSDK_SYSCON_EMICTRL_RCYC_Msk   (0x7UL /*<< CMSDK_SYSCON_EMICTRL_RCYC_Pos*/) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
 
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos   2
 
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk   (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
 
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos   1
 
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk   (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
 
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos   0
 
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk   (0x1UL /*<< CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos*/) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
 
#define CMSDK_Watchdog_LOAD_Pos   0 /* CMSDK_Watchdog LOAD: LOAD Position */
 
#define CMSDK_Watchdog_LOAD_Msk   (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */
 
#define CMSDK_Watchdog_VALUE_Pos   0 /* CMSDK_Watchdog VALUE: VALUE Position */
 
#define CMSDK_Watchdog_VALUE_Msk   (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */
 
#define CMSDK_Watchdog_CTRL_RESEN_Pos   1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
 
#define CMSDK_Watchdog_CTRL_RESEN_Msk   (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
 
#define CMSDK_Watchdog_CTRL_INTEN_Pos   0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
 
#define CMSDK_Watchdog_CTRL_INTEN_Msk   (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
 
#define CMSDK_Watchdog_INTCLR_Pos   0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
 
#define CMSDK_Watchdog_INTCLR_Msk   (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
 
#define CMSDK_Watchdog_RAWINTSTAT_Pos   0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
 
#define CMSDK_Watchdog_RAWINTSTAT_Msk   (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
 
#define CMSDK_Watchdog_MASKINTSTAT_Pos   0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
 
#define CMSDK_Watchdog_MASKINTSTAT_Msk   (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
 
#define CMSDK_Watchdog_LOCK_Pos   0 /* CMSDK_Watchdog LOCK: LOCK Position */
 
#define CMSDK_Watchdog_LOCK_Msk   (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */
 
#define CMSDK_Watchdog_INTEGTESTEN_Pos   0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
 
#define CMSDK_Watchdog_INTEGTESTEN_Msk   (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
 
#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos   1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
 
#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk   (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
 
#define CMSDK_FLASH_BASE   (0x00000000UL)
 
#define CMSDK_SRAM_BASE   (0x20000000UL)
 
#define CMSDK_PERIPH_BASE   (0x40000000UL)
 
#define CMSDK_RAM_BASE   (0x20000000UL)
 
#define CMSDK_APB_BASE   (0x40000000UL)
 
#define CMSDK_AHB_BASE   (0x40010000UL)
 
#define CMSDK_S_APB_BASE   (0x50000000UL)
 
#define CMSDK_TIMER0_BASE   (CMSDK_APB_BASE + 0x0000UL)
 
#define CMSDK_TIMER1_BASE   (CMSDK_APB_BASE + 0x1000UL)
 
#define CMSDK_DUALTIMER_BASE   (CMSDK_APB_BASE + 0x2000UL)
 
#define CMSDK_DUALTIMER_1_BASE   (CMSDK_DUALTIMER_BASE)
 
#define CMSDK_DUALTIMER_2_BASE   (CMSDK_DUALTIMER_BASE + 0x20UL)
 
#define CMSDK_UART0_BASE   (CMSDK_APB_BASE + 0x4000UL)
 
#define CMSDK_UART1_BASE   (CMSDK_APB_BASE + 0x5000UL)
 
#define CMSDK_UART2_BASE   (CMSDK_APB_BASE + 0x6000UL)
 
#define CMSDK_WATCHDOG_BASE   (CMSDK_APB_BASE + 0x8000UL)
 
#define CMSDK_GPIO0_BASE   (CMSDK_AHB_BASE + 0x0000UL)
 
#define CMSDK_GPIO1_BASE   (CMSDK_AHB_BASE + 0x1000UL)
 
#define CMSDK_SYSCTRL_BASE   (CMSDK_AHB_BASE + 0xF000UL)
 
#define CMSDK_SECURETIMER0_BASE   (CMSDK_S_APB_BASE + 0x0000UL)
 
#define CMSDK_SECURETIMER1_BASE   (CMSDK_S_APB_BASE + 0x1000UL)
 
#define CMSDK_UART0   ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
 
#define CMSDK_UART1   ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
 
#define CMSDK_UART2   ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
 
#define CMSDK_TIMER0   ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
 
#define CMSDK_TIMER1   ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
 
#define CMSDK_DUALTIMER   ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
 
#define CMSDK_DUALTIMER1   ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
 
#define CMSDK_DUALTIMER2   ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
 
#define CMSDK_WATCHDOG   ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
 
#define CMSDK_GPIO0   ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
 
#define CMSDK_GPIO1   ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
 
#define CMSDK_SYSCON   ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
 
#define CMSDK_SECURETIMER0   ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER0_BASE)
 
#define CMSDK_SECURETIMER1   ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER1_BASE)
 

Typedefs

typedef enum IRQn IRQn_Type
 

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14 ,
  HardFault_IRQn = -13 ,
  SVCall_IRQn = -5 ,
  PendSV_IRQn = -2 ,
  SysTick_IRQn = -1 ,
  UART0RX_IRQn = 0 ,
  UART0TX_IRQn = 1 ,
  UART1RX_IRQn = 2 ,
  UART1TX_IRQn = 3 ,
  UART2RX_IRQn = 4 ,
  UART2TX_IRQn = 5 ,
  GPIO0ALL_IRQn = 6 ,
  GPIO1ALL_IRQn = 7 ,
  TIMER0_IRQn = 8 ,
  TIMER1_IRQn = 9 ,
  DUALTIMER_IRQn = 10 ,
  SPI_0_1_IRQn = 11 ,
  UART_0_1_2_OVF_IRQn = 12 ,
  ETHERNET_IRQn = 13 ,
  I2S_IRQn = 14 ,
  TOUCHSCREEN_IRQn = 15 ,
  GPIO2_IRQn = 16 ,
  GPIO3_IRQn = 17 ,
  UART3RX_IRQn = 18 ,
  UART3TX_IRQn = 19 ,
  UART4RX_IRQn = 20 ,
  UART4TX_IRQn = 21 ,
  SPI_2_IRQn = 22 ,
  SPI_3_4_IRQn = 23 ,
  GPIO0_0_IRQn = 24 ,
  GPIO0_1_IRQn = 25 ,
  GPIO0_2_IRQn = 26 ,
  GPIO0_3_IRQn = 27 ,
  GPIO0_4_IRQn = 28 ,
  GPIO0_5_IRQn = 29 ,
  GPIO0_6_IRQn = 30 ,
  GPIO0_7_IRQn = 31 ,
  GPIO1_0_IRQn = 32 ,
  GPIO1_1_IRQn = 33 ,
  GPIO1_2_IRQn = 34 ,
  GPIO1_3_IRQn = 35 ,
  GPIO1_4_IRQn = 36 ,
  GPIO1_5_IRQn = 37 ,
  GPIO1_6_IRQn = 38 ,
  GPIO1_7_IRQn = 39 ,
  GPIO1_8_IRQn = 40 ,
  GPIO1_9_IRQn = 41 ,
  GPIO1_10_IRQn = 42 ,
  GPIO1_11_IRQn = 43 ,
  GPIO1_12_IRQn = 44 ,
  GPIO1_13_IRQn = 45 ,
  GPIO1_14_IRQn = 46 ,
  GPIO1_15_IRQn = 47 ,
  SPI_0B_IRQn = 48 ,
  Reserved_IRQn = 49 ,
  SECURETIMER0_IRQn = 50 ,
  SECURETIMER1_IRQn = 51 ,
  SPI_1B_IRQn = 52 ,
  SPI_2B_IRQn = 53 ,
  SPI_3B_IRQn = 54 ,
  SPI_4B_IRQn = 55
}
 

Detailed Description

CMSIS Core Peripheral Access Layer Header File for CMSDK_ARMv8MBL Device.

Version
V4.06
Date
04. July 2016

Macro Definition Documentation

◆ __ARMv8MBL_REV

#define __ARMv8MBL_REV   0x0000U /* Core revision r0p0 */

◆ __SAUREGION_PRESENT

#define __SAUREGION_PRESENT   1U /* SAU regions are present */

◆ __MPU_PRESENT

#define __MPU_PRESENT   1U /* MPU present */

◆ __VTOR_PRESENT

#define __VTOR_PRESENT   1U /* VTOR present */

◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS   2U /* Number of Bits used for Priority Levels */

◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig   0U /* Set to 1 if different SysTick Config is used */

◆ CMSDK_UART_DATA_Pos

#define CMSDK_UART_DATA_Pos   0 /* CMSDK_UART_DATA_Pos: DATA Position */

◆ CMSDK_UART_DATA_Msk

#define CMSDK_UART_DATA_Msk   (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */

◆ CMSDK_UART_STATE_RXOR_Pos

#define CMSDK_UART_STATE_RXOR_Pos   3 /* CMSDK_UART STATE: RXOR Position */

◆ CMSDK_UART_STATE_RXOR_Msk

#define CMSDK_UART_STATE_RXOR_Msk   (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */

◆ CMSDK_UART_STATE_TXOR_Pos

#define CMSDK_UART_STATE_TXOR_Pos   2 /* CMSDK_UART STATE: TXOR Position */

◆ CMSDK_UART_STATE_TXOR_Msk

#define CMSDK_UART_STATE_TXOR_Msk   (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */

◆ CMSDK_UART_STATE_RXBF_Pos

#define CMSDK_UART_STATE_RXBF_Pos   1 /* CMSDK_UART STATE: RXBF Position */

◆ CMSDK_UART_STATE_RXBF_Msk

#define CMSDK_UART_STATE_RXBF_Msk   (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */

◆ CMSDK_UART_STATE_TXBF_Pos

#define CMSDK_UART_STATE_TXBF_Pos   0 /* CMSDK_UART STATE: TXBF Position */

◆ CMSDK_UART_STATE_TXBF_Msk

#define CMSDK_UART_STATE_TXBF_Msk   (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */

◆ CMSDK_UART_CTRL_HSTM_Pos

#define CMSDK_UART_CTRL_HSTM_Pos   6 /* CMSDK_UART CTRL: HSTM Position */

◆ CMSDK_UART_CTRL_HSTM_Msk

#define CMSDK_UART_CTRL_HSTM_Msk   (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */

◆ CMSDK_UART_CTRL_RXORIRQEN_Pos

#define CMSDK_UART_CTRL_RXORIRQEN_Pos   5 /* CMSDK_UART CTRL: RXORIRQEN Position */

◆ CMSDK_UART_CTRL_RXORIRQEN_Msk

#define CMSDK_UART_CTRL_RXORIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */

◆ CMSDK_UART_CTRL_TXORIRQEN_Pos

#define CMSDK_UART_CTRL_TXORIRQEN_Pos   4 /* CMSDK_UART CTRL: TXORIRQEN Position */

◆ CMSDK_UART_CTRL_TXORIRQEN_Msk

#define CMSDK_UART_CTRL_TXORIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */

◆ CMSDK_UART_CTRL_RXIRQEN_Pos

#define CMSDK_UART_CTRL_RXIRQEN_Pos   3 /* CMSDK_UART CTRL: RXIRQEN Position */

◆ CMSDK_UART_CTRL_RXIRQEN_Msk

#define CMSDK_UART_CTRL_RXIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */

◆ CMSDK_UART_CTRL_TXIRQEN_Pos

#define CMSDK_UART_CTRL_TXIRQEN_Pos   2 /* CMSDK_UART CTRL: TXIRQEN Position */

◆ CMSDK_UART_CTRL_TXIRQEN_Msk

#define CMSDK_UART_CTRL_TXIRQEN_Msk   (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */

◆ CMSDK_UART_CTRL_RXEN_Pos

#define CMSDK_UART_CTRL_RXEN_Pos   1 /* CMSDK_UART CTRL: RXEN Position */

◆ CMSDK_UART_CTRL_RXEN_Msk

#define CMSDK_UART_CTRL_RXEN_Msk   (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */

◆ CMSDK_UART_CTRL_TXEN_Pos

#define CMSDK_UART_CTRL_TXEN_Pos   0 /* CMSDK_UART CTRL: TXEN Position */

◆ CMSDK_UART_CTRL_TXEN_Msk

#define CMSDK_UART_CTRL_TXEN_Msk   (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */

◆ CMSDK_UART_INTSTATUS_RXORIRQ_Pos

#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos   3 /* CMSDK_UART CTRL: RXORIRQ Position */

◆ CMSDK_UART_CTRL_RXORIRQ_Msk

#define CMSDK_UART_CTRL_RXORIRQ_Msk   (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */

◆ CMSDK_UART_CTRL_TXORIRQ_Pos

#define CMSDK_UART_CTRL_TXORIRQ_Pos   2 /* CMSDK_UART CTRL: TXORIRQ Position */

◆ CMSDK_UART_CTRL_TXORIRQ_Msk

#define CMSDK_UART_CTRL_TXORIRQ_Msk   (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */

◆ CMSDK_UART_CTRL_RXIRQ_Pos

#define CMSDK_UART_CTRL_RXIRQ_Pos   1 /* CMSDK_UART CTRL: RXIRQ Position */

◆ CMSDK_UART_CTRL_RXIRQ_Msk

#define CMSDK_UART_CTRL_RXIRQ_Msk   (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */

◆ CMSDK_UART_CTRL_TXIRQ_Pos

#define CMSDK_UART_CTRL_TXIRQ_Pos   0 /* CMSDK_UART CTRL: TXIRQ Position */

◆ CMSDK_UART_CTRL_TXIRQ_Msk

#define CMSDK_UART_CTRL_TXIRQ_Msk   (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */

◆ CMSDK_UART_BAUDDIV_Pos

#define CMSDK_UART_BAUDDIV_Pos   0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */

◆ CMSDK_UART_BAUDDIV_Msk

#define CMSDK_UART_BAUDDIV_Msk   (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */

◆ CMSDK_TIMER_CTRL_IRQEN_Pos

#define CMSDK_TIMER_CTRL_IRQEN_Pos   3 /* CMSDK_TIMER CTRL: IRQEN Position */

◆ CMSDK_TIMER_CTRL_IRQEN_Msk

#define CMSDK_TIMER_CTRL_IRQEN_Msk   (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */

◆ CMSDK_TIMER_CTRL_SELEXTCLK_Pos

#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos   2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */

◆ CMSDK_TIMER_CTRL_SELEXTCLK_Msk

#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk   (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */

◆ CMSDK_TIMER_CTRL_SELEXTEN_Pos

#define CMSDK_TIMER_CTRL_SELEXTEN_Pos   1 /* CMSDK_TIMER CTRL: SELEXTEN Position */

◆ CMSDK_TIMER_CTRL_SELEXTEN_Msk

#define CMSDK_TIMER_CTRL_SELEXTEN_Msk   (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */

◆ CMSDK_TIMER_CTRL_EN_Pos

#define CMSDK_TIMER_CTRL_EN_Pos   0 /* CMSDK_TIMER CTRL: EN Position */

◆ CMSDK_TIMER_CTRL_EN_Msk

#define CMSDK_TIMER_CTRL_EN_Msk   (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */

◆ CMSDK_TIMER_VAL_CURRENT_Pos

#define CMSDK_TIMER_VAL_CURRENT_Pos   0 /* CMSDK_TIMER VALUE: CURRENT Position */

◆ CMSDK_TIMER_VAL_CURRENT_Msk

#define CMSDK_TIMER_VAL_CURRENT_Msk   (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */

◆ CMSDK_TIMER_RELOAD_VAL_Pos

#define CMSDK_TIMER_RELOAD_VAL_Pos   0 /* CMSDK_TIMER RELOAD: RELOAD Position */

◆ CMSDK_TIMER_RELOAD_VAL_Msk

#define CMSDK_TIMER_RELOAD_VAL_Msk   (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */

◆ CMSDK_TIMER_INTSTATUS_Pos

#define CMSDK_TIMER_INTSTATUS_Pos   0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */

◆ CMSDK_TIMER_INTSTATUS_Msk

#define CMSDK_TIMER_INTSTATUS_Msk   (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */

◆ CMSDK_TIMER_INTCLEAR_Pos

#define CMSDK_TIMER_INTCLEAR_Pos   0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */

◆ CMSDK_TIMER_INTCLEAR_Msk

#define CMSDK_TIMER_INTCLEAR_Msk   (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */

◆ CMSDK_DUALTIMER_LOAD_Pos

#define CMSDK_DUALTIMER_LOAD_Pos   0 /* CMSDK_DUALTIMER LOAD: LOAD Position */

◆ CMSDK_DUALTIMER_LOAD_Msk

#define CMSDK_DUALTIMER_LOAD_Msk   (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */

◆ CMSDK_DUALTIMER_VALUE_Pos

#define CMSDK_DUALTIMER_VALUE_Pos   0 /* CMSDK_DUALTIMER VALUE: VALUE Position */

◆ CMSDK_DUALTIMER_VALUE_Msk

#define CMSDK_DUALTIMER_VALUE_Msk   (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */

◆ CMSDK_DUALTIMER_CTRL_EN_Pos

#define CMSDK_DUALTIMER_CTRL_EN_Pos   7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */

◆ CMSDK_DUALTIMER_CTRL_EN_Msk

#define CMSDK_DUALTIMER_CTRL_EN_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */

◆ CMSDK_DUALTIMER_CTRL_MODE_Pos

#define CMSDK_DUALTIMER_CTRL_MODE_Pos   6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */

◆ CMSDK_DUALTIMER_CTRL_MODE_Msk

#define CMSDK_DUALTIMER_CTRL_MODE_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */

◆ CMSDK_DUALTIMER_CTRL_INTEN_Pos

#define CMSDK_DUALTIMER_CTRL_INTEN_Pos   5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */

◆ CMSDK_DUALTIMER_CTRL_INTEN_Msk

#define CMSDK_DUALTIMER_CTRL_INTEN_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */

◆ CMSDK_DUALTIMER_CTRL_PRESCALE_Pos

#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos   2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */

◆ CMSDK_DUALTIMER_CTRL_PRESCALE_Msk

#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk   (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */

◆ CMSDK_DUALTIMER_CTRL_SIZE_Pos

#define CMSDK_DUALTIMER_CTRL_SIZE_Pos   1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */

◆ CMSDK_DUALTIMER_CTRL_SIZE_Msk

#define CMSDK_DUALTIMER_CTRL_SIZE_Msk   (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */

◆ CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos

#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos   0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */

◆ CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk

#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk   (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */

◆ CMSDK_DUALTIMER_INTCLR_Pos

#define CMSDK_DUALTIMER_INTCLR_Pos   0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */

◆ CMSDK_DUALTIMER_INTCLR_Msk

#define CMSDK_DUALTIMER_INTCLR_Msk   (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */

◆ CMSDK_DUALTIMER_RIS_Pos

#define CMSDK_DUALTIMER_RIS_Pos   0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */

◆ CMSDK_DUALTIMER_RIS_Msk

#define CMSDK_DUALTIMER_RIS_Msk   (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */

◆ CMSDK_DUALTIMER_MIS_Pos

#define CMSDK_DUALTIMER_MIS_Pos   0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */

◆ CMSDK_DUALTIMER_MIS_Msk

#define CMSDK_DUALTIMER_MIS_Msk   (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */

◆ CMSDK_DUALTIMER_BGLOAD_Pos

#define CMSDK_DUALTIMER_BGLOAD_Pos   0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */

◆ CMSDK_DUALTIMER_BGLOAD_Msk

#define CMSDK_DUALTIMER_BGLOAD_Msk   (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */

◆ CMSDK_GPIO_DATA_Pos

#define CMSDK_GPIO_DATA_Pos   0 /* CMSDK_GPIO DATA: DATA Position */

◆ CMSDK_GPIO_DATA_Msk

#define CMSDK_GPIO_DATA_Msk   (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */

◆ CMSDK_GPIO_DATAOUT_Pos

#define CMSDK_GPIO_DATAOUT_Pos   0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */

◆ CMSDK_GPIO_DATAOUT_Msk

#define CMSDK_GPIO_DATAOUT_Msk   (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */

◆ CMSDK_GPIO_OUTENSET_Pos

#define CMSDK_GPIO_OUTENSET_Pos   0 /* CMSDK_GPIO OUTEN: OUTEN Position */

◆ CMSDK_GPIO_OUTENSET_Msk

#define CMSDK_GPIO_OUTENSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */

◆ CMSDK_GPIO_OUTENCLR_Pos

#define CMSDK_GPIO_OUTENCLR_Pos   0 /* CMSDK_GPIO OUTEN: OUTEN Position */

◆ CMSDK_GPIO_OUTENCLR_Msk

#define CMSDK_GPIO_OUTENCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */

◆ CMSDK_GPIO_ALTFUNCSET_Pos

#define CMSDK_GPIO_ALTFUNCSET_Pos   0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */

◆ CMSDK_GPIO_ALTFUNCSET_Msk

#define CMSDK_GPIO_ALTFUNCSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */

◆ CMSDK_GPIO_ALTFUNCCLR_Pos

#define CMSDK_GPIO_ALTFUNCCLR_Pos   0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */

◆ CMSDK_GPIO_ALTFUNCCLR_Msk

#define CMSDK_GPIO_ALTFUNCCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */

◆ CMSDK_GPIO_INTENSET_Pos

#define CMSDK_GPIO_INTENSET_Pos   0 /* CMSDK_GPIO INTEN: INTEN Position */

◆ CMSDK_GPIO_INTENSET_Msk

#define CMSDK_GPIO_INTENSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */

◆ CMSDK_GPIO_INTENCLR_Pos

#define CMSDK_GPIO_INTENCLR_Pos   0 /* CMSDK_GPIO INTEN: INTEN Position */

◆ CMSDK_GPIO_INTENCLR_Msk

#define CMSDK_GPIO_INTENCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */

◆ CMSDK_GPIO_INTTYPESET_Pos

#define CMSDK_GPIO_INTTYPESET_Pos   0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */

◆ CMSDK_GPIO_INTTYPESET_Msk

#define CMSDK_GPIO_INTTYPESET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */

◆ CMSDK_GPIO_INTTYPECLR_Pos

#define CMSDK_GPIO_INTTYPECLR_Pos   0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */

◆ CMSDK_GPIO_INTTYPECLR_Msk

#define CMSDK_GPIO_INTTYPECLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */

◆ CMSDK_GPIO_INTPOLSET_Pos

#define CMSDK_GPIO_INTPOLSET_Pos   0 /* CMSDK_GPIO INTPOL: INTPOL Position */

◆ CMSDK_GPIO_INTPOLSET_Msk

#define CMSDK_GPIO_INTPOLSET_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */

◆ CMSDK_GPIO_INTPOLCLR_Pos

#define CMSDK_GPIO_INTPOLCLR_Pos   0 /* CMSDK_GPIO INTPOL: INTPOL Position */

◆ CMSDK_GPIO_INTPOLCLR_Msk

#define CMSDK_GPIO_INTPOLCLR_Msk   (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */

◆ CMSDK_GPIO_INTSTATUS_Pos

#define CMSDK_GPIO_INTSTATUS_Pos   0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */

◆ CMSDK_GPIO_INTCLEAR_Msk [1/2]

#define CMSDK_GPIO_INTCLEAR_Msk   (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */

◆ CMSDK_GPIO_INTCLEAR_Pos

#define CMSDK_GPIO_INTCLEAR_Pos   0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */

◆ CMSDK_GPIO_INTCLEAR_Msk [2/2]

#define CMSDK_GPIO_INTCLEAR_Msk   (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */

◆ CMSDK_GPIO_MASKLOWBYTE_Pos

#define CMSDK_GPIO_MASKLOWBYTE_Pos   0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */

◆ CMSDK_GPIO_MASKLOWBYTE_Msk

#define CMSDK_GPIO_MASKLOWBYTE_Msk   (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */

◆ CMSDK_GPIO_MASKHIGHBYTE_Pos

#define CMSDK_GPIO_MASKHIGHBYTE_Pos   0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */

◆ CMSDK_GPIO_MASKHIGHBYTE_Msk

#define CMSDK_GPIO_MASKHIGHBYTE_Msk   (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */

◆ CMSDK_SYSCON_REMAP_Pos

#define CMSDK_SYSCON_REMAP_Pos   0

◆ CMSDK_SYSCON_REMAP_Msk

#define CMSDK_SYSCON_REMAP_Msk   (0x1UL /*<< CMSDK_SYSCON_REMAP_Pos*/) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */

◆ CMSDK_SYSCON_PMUCTRL_EN_Pos

#define CMSDK_SYSCON_PMUCTRL_EN_Pos   0

◆ CMSDK_SYSCON_PMUCTRL_EN_Msk

#define CMSDK_SYSCON_PMUCTRL_EN_Msk   (0x1UL /*<< CMSDK_SYSCON_PMUCTRL_EN_Pos*/) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */

◆ CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos

#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos   0

◆ CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk

#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk   (0x1UL /*<< CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos*/) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */

◆ CMSDK_SYSCON_EMICTRL_SIZE_Pos

#define CMSDK_SYSCON_EMICTRL_SIZE_Pos   24

◆ CMSDK_SYSCON_EMICTRL_SIZE_Msk

#define CMSDK_SYSCON_EMICTRL_SIZE_Msk   (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */

◆ CMSDK_SYSCON_EMICTRL_TACYC_Pos

#define CMSDK_SYSCON_EMICTRL_TACYC_Pos   16

◆ CMSDK_SYSCON_EMICTRL_TACYC_Msk

#define CMSDK_SYSCON_EMICTRL_TACYC_Msk   (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */

◆ CMSDK_SYSCON_EMICTRL_WCYC_Pos

#define CMSDK_SYSCON_EMICTRL_WCYC_Pos   8

◆ CMSDK_SYSCON_EMICTRL_WCYC_Msk

#define CMSDK_SYSCON_EMICTRL_WCYC_Msk   (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */

◆ CMSDK_SYSCON_EMICTRL_RCYC_Pos

#define CMSDK_SYSCON_EMICTRL_RCYC_Pos   0

◆ CMSDK_SYSCON_EMICTRL_RCYC_Msk

#define CMSDK_SYSCON_EMICTRL_RCYC_Msk   (0x7UL /*<< CMSDK_SYSCON_EMICTRL_RCYC_Pos*/) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */

◆ CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos

#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos   2

◆ CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk

#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk   (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */

◆ CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos

#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos   1

◆ CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk

#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk   (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */

◆ CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos

#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos   0

◆ CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk

#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk   (0x1UL /*<< CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos*/) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */

◆ CMSDK_Watchdog_LOAD_Pos

#define CMSDK_Watchdog_LOAD_Pos   0 /* CMSDK_Watchdog LOAD: LOAD Position */

◆ CMSDK_Watchdog_LOAD_Msk

#define CMSDK_Watchdog_LOAD_Msk   (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */

◆ CMSDK_Watchdog_VALUE_Pos

#define CMSDK_Watchdog_VALUE_Pos   0 /* CMSDK_Watchdog VALUE: VALUE Position */

◆ CMSDK_Watchdog_VALUE_Msk

#define CMSDK_Watchdog_VALUE_Msk   (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */

◆ CMSDK_Watchdog_CTRL_RESEN_Pos

#define CMSDK_Watchdog_CTRL_RESEN_Pos   1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */

◆ CMSDK_Watchdog_CTRL_RESEN_Msk

#define CMSDK_Watchdog_CTRL_RESEN_Msk   (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */

◆ CMSDK_Watchdog_CTRL_INTEN_Pos

#define CMSDK_Watchdog_CTRL_INTEN_Pos   0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */

◆ CMSDK_Watchdog_CTRL_INTEN_Msk

#define CMSDK_Watchdog_CTRL_INTEN_Msk   (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */

◆ CMSDK_Watchdog_INTCLR_Pos

#define CMSDK_Watchdog_INTCLR_Pos   0 /* CMSDK_Watchdog INTCLR: Int Clear Position */

◆ CMSDK_Watchdog_INTCLR_Msk

#define CMSDK_Watchdog_INTCLR_Msk   (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */

◆ CMSDK_Watchdog_RAWINTSTAT_Pos

#define CMSDK_Watchdog_RAWINTSTAT_Pos   0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */

◆ CMSDK_Watchdog_RAWINTSTAT_Msk

#define CMSDK_Watchdog_RAWINTSTAT_Msk   (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */

◆ CMSDK_Watchdog_MASKINTSTAT_Pos

#define CMSDK_Watchdog_MASKINTSTAT_Pos   0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */

◆ CMSDK_Watchdog_MASKINTSTAT_Msk

#define CMSDK_Watchdog_MASKINTSTAT_Msk   (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */

◆ CMSDK_Watchdog_LOCK_Pos

#define CMSDK_Watchdog_LOCK_Pos   0 /* CMSDK_Watchdog LOCK: LOCK Position */

◆ CMSDK_Watchdog_LOCK_Msk

#define CMSDK_Watchdog_LOCK_Msk   (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */

◆ CMSDK_Watchdog_INTEGTESTEN_Pos

#define CMSDK_Watchdog_INTEGTESTEN_Pos   0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */

◆ CMSDK_Watchdog_INTEGTESTEN_Msk

#define CMSDK_Watchdog_INTEGTESTEN_Msk   (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */

◆ CMSDK_Watchdog_INTEGTESTOUTSET_Pos

#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos   1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */

◆ CMSDK_Watchdog_INTEGTESTOUTSET_Msk

#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk   (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */

◆ CMSDK_FLASH_BASE

#define CMSDK_FLASH_BASE   (0x00000000UL)

◆ CMSDK_SRAM_BASE

#define CMSDK_SRAM_BASE   (0x20000000UL)

◆ CMSDK_PERIPH_BASE

#define CMSDK_PERIPH_BASE   (0x40000000UL)

◆ CMSDK_RAM_BASE

#define CMSDK_RAM_BASE   (0x20000000UL)

◆ CMSDK_APB_BASE

#define CMSDK_APB_BASE   (0x40000000UL)

◆ CMSDK_AHB_BASE

#define CMSDK_AHB_BASE   (0x40010000UL)

◆ CMSDK_S_APB_BASE

#define CMSDK_S_APB_BASE   (0x50000000UL)

◆ CMSDK_TIMER0_BASE

#define CMSDK_TIMER0_BASE   (CMSDK_APB_BASE + 0x0000UL)

◆ CMSDK_TIMER1_BASE

#define CMSDK_TIMER1_BASE   (CMSDK_APB_BASE + 0x1000UL)

◆ CMSDK_DUALTIMER_BASE

#define CMSDK_DUALTIMER_BASE   (CMSDK_APB_BASE + 0x2000UL)

◆ CMSDK_DUALTIMER_1_BASE

#define CMSDK_DUALTIMER_1_BASE   (CMSDK_DUALTIMER_BASE)

◆ CMSDK_DUALTIMER_2_BASE

#define CMSDK_DUALTIMER_2_BASE   (CMSDK_DUALTIMER_BASE + 0x20UL)

◆ CMSDK_UART0_BASE

#define CMSDK_UART0_BASE   (CMSDK_APB_BASE + 0x4000UL)

◆ CMSDK_UART1_BASE

#define CMSDK_UART1_BASE   (CMSDK_APB_BASE + 0x5000UL)

◆ CMSDK_UART2_BASE

#define CMSDK_UART2_BASE   (CMSDK_APB_BASE + 0x6000UL)

◆ CMSDK_WATCHDOG_BASE

#define CMSDK_WATCHDOG_BASE   (CMSDK_APB_BASE + 0x8000UL)

◆ CMSDK_GPIO0_BASE

#define CMSDK_GPIO0_BASE   (CMSDK_AHB_BASE + 0x0000UL)

◆ CMSDK_GPIO1_BASE

#define CMSDK_GPIO1_BASE   (CMSDK_AHB_BASE + 0x1000UL)

◆ CMSDK_SYSCTRL_BASE

#define CMSDK_SYSCTRL_BASE   (CMSDK_AHB_BASE + 0xF000UL)

◆ CMSDK_SECURETIMER0_BASE

#define CMSDK_SECURETIMER0_BASE   (CMSDK_S_APB_BASE + 0x0000UL)

◆ CMSDK_SECURETIMER1_BASE

#define CMSDK_SECURETIMER1_BASE   (CMSDK_S_APB_BASE + 0x1000UL)

◆ CMSDK_UART0

#define CMSDK_UART0   ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )

◆ CMSDK_UART1

#define CMSDK_UART1   ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )

◆ CMSDK_UART2

#define CMSDK_UART2   ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )

◆ CMSDK_TIMER0

#define CMSDK_TIMER0   ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )

◆ CMSDK_TIMER1

#define CMSDK_TIMER1   ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )

◆ CMSDK_DUALTIMER

#define CMSDK_DUALTIMER   ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )

◆ CMSDK_DUALTIMER1

#define CMSDK_DUALTIMER1   ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )

◆ CMSDK_DUALTIMER2

#define CMSDK_DUALTIMER2   ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )

◆ CMSDK_WATCHDOG

#define CMSDK_WATCHDOG   ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )

◆ CMSDK_GPIO0

#define CMSDK_GPIO0   ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )

◆ CMSDK_GPIO1

#define CMSDK_GPIO1   ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )

◆ CMSDK_SYSCON

#define CMSDK_SYSCON   ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )

◆ CMSDK_SECURETIMER0

#define CMSDK_SECURETIMER0   ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER0_BASE)

◆ CMSDK_SECURETIMER1

#define CMSDK_SECURETIMER1   ((CMSDK_TIMER_TypeDef *) CMSDK_SECURETIMER1_BASE)

Typedef Documentation

◆ IRQn_Type

typedef enum IRQn IRQn_Type

Enumeration Type Documentation

◆ IRQn

enum IRQn
Enumerator
NonMaskableInt_IRQn 
HardFault_IRQn 
SVCall_IRQn 
PendSV_IRQn 
SysTick_IRQn 
UART0RX_IRQn 
UART0TX_IRQn 
UART1RX_IRQn 
UART1TX_IRQn 
UART2RX_IRQn 
UART2TX_IRQn 
GPIO0ALL_IRQn 
GPIO1ALL_IRQn 
TIMER0_IRQn 
TIMER1_IRQn 
DUALTIMER_IRQn 
SPI_0_1_IRQn 
UART_0_1_2_OVF_IRQn 
ETHERNET_IRQn 
I2S_IRQn 
TOUCHSCREEN_IRQn 
GPIO2_IRQn 
GPIO3_IRQn 
UART3RX_IRQn 
UART3TX_IRQn 
UART4RX_IRQn 
UART4TX_IRQn 
SPI_2_IRQn 
SPI_3_4_IRQn 
GPIO0_0_IRQn 
GPIO0_1_IRQn 
GPIO0_2_IRQn 
GPIO0_3_IRQn 
GPIO0_4_IRQn 
GPIO0_5_IRQn 
GPIO0_6_IRQn 
GPIO0_7_IRQn 
GPIO1_0_IRQn 
GPIO1_1_IRQn 
GPIO1_2_IRQn 
GPIO1_3_IRQn 
GPIO1_4_IRQn 
GPIO1_5_IRQn 
GPIO1_6_IRQn 
GPIO1_7_IRQn 
GPIO1_8_IRQn 
GPIO1_9_IRQn 
GPIO1_10_IRQn 
GPIO1_11_IRQn 
GPIO1_12_IRQn 
GPIO1_13_IRQn 
GPIO1_14_IRQn 
GPIO1_15_IRQn 
SPI_0B_IRQn 
Reserved_IRQn 
SECURETIMER0_IRQn 
SECURETIMER1_IRQn 
SPI_1B_IRQn 
SPI_2B_IRQn 
SPI_3B_IRQn 
SPI_4B_IRQn 
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