#include "hal/vsf_hal_cfg.h"
#include "../__device.h"
#include "hal/driver/vendor_driver.h"
#include "hal/driver/common/swi/arm/vsf_swi_template.inc"
#include <math.h>
#include "service/trace/vsf_trace.h"

Data Structures
struct	vsf_hw_clk_t

struct	vsf_hw_pwr_domain_t

struct	vsf_hw_pwr_t

Macros
#define	VCO_MIN 300000000

#define	VCO_MAX 1250000000

#define	REF_MIN 1000000

#define	REF_MAX 64000000

#define	NR_MIN 1

#define	NR_MAX 64

#define	NF_MIN 2

#define	NF_MAX 4095

#define	RCC_REG_BIT_MASK ((uint32_t)0x00000000)

#define	RCC_PLL_BWAJ_MASK (~RCC_PLL1CTRL1_PLL1BWAJ)

#define	RCC_PLL_CLKR_CLKF_MASK (RCC_REG_BIT_MASK)

#define	RCC_PLL_SRC_MASK (~RCC_PLL1CTRL1_PLL1SRC)

#define	RCC_PLL_LOCK_FLAG (RCC_PLL1CTRL1_PLL1PHLK)

#define	RCC_PLL_LDO_ENABLE (RCC_PLL1CTRL1_PLL1LDOEN)

#define	RCC_PLL_ENABLE (RCC_PLL1CTRL1_PLL1EN )

#define	RCC_PLL_RESET_ENABLE (RCC_PLL1CTRL1_PLL1RST )

#define	RCC_PLL_POWER_DOWN (RCC_PLL1CTRL1_PLL1PD )

#define	__RCC_DELAY_US(usec)

Enumerations
enum	{ VSF_HW_CLK_PRESCALER_NONE = 0 , VSF_HW_CLK_PRESCALER_CONST , VSF_HW_CLK_PRESCALER_DIV , VSF_HW_CLK_PRESCALER_FUNC }

enum	{ VSF_HW_CLK_TYPE_CONST , VSF_HW_CLK_TYPE_CLK , VSF_HW_CLK_TYPE_SEL }

Functions

void vsf_hw_clkrst_region_set (uint32_t region, uint_fast8_t value)

uint_fast8_t vsf_hw_clkrst_region_get (uint32_t region)

void vsf_hw_clkrst_region_set_bit (uint32_t region)

void vsf_hw_clkrst_region_clear_bit (uint32_t region)

uint_fast8_t vsf_hw_clkrst_region_get_bit (uint32_t region)

const vsf_hw_clk_t * vsf_hw_clk_get_src (const vsf_hw_clk_t *clk)

uint32_t vsf_hw_clk_get_freq_hz (const vsf_hw_clk_t *clk)

void vsf_hw_clk_enable (const vsf_hw_clk_t *clk)

void vsf_hw_clk_disable (const vsf_hw_clk_t *clk)

bool vsf_hw_clk_is_enabled (const vsf_hw_clk_t *clk)

bool vsf_hw_clk_is_ready (const vsf_hw_clk_t *clk)

vsf_err_t vsf_hw_clk_config (const vsf_hw_clk_t *clk, const vsf_hw_clk_t *clksrc, uint16_t prescaler, uint32_t freq_hz)

RCC_CalculatePLLParam.

*\fun Configures the SHRTPLL clock source and multiplication factor. *
Parameters

fin(SHRTPLL input frequency): *\ 1000000 ~ 64000000 (Hz) *

fout(SHRTPLL output frequency): *\ 75000000 ~ 1250000000 (Hz) *

Cmd *\ - ENABLE
*\ - DISABLE *

Returns
ErrorStatus: *\ - SUCCESS
*\ - ERROR
*

Note
fout = fin*(CLKF[25:0]/16384)/(CLKR[5:0] +1)

ErrorStatus RCC_CalculatePLLParam (uint64_t fin, uint64_t fout, uint32_t *nr, uint32_t *nf, uint32_t *wb)

vsf_err_t vsf_hw_pll_config (const vsf_hw_clk_t *clk, uint32_t out_freq_hz)

configure frequency range of pll input/output clocks

void vsf_hw_power_domain_enable (const vsf_hw_pwr_domain_t *domain)

void vsf_hw_power_domain_disable (const vsf_hw_pwr_domain_t *domain)

bool vsf_hw_power_domain_is_ready (const vsf_hw_pwr_domain_t *domain)

void vsf_hw_power_enable (const vsf_hw_pwr_t *pwr)

void vsf_hw_power_disable (const vsf_hw_pwr_t *pwr)

void HardFault_Handler (void)

void MemManage_Handler (void)

void BusFault_Handler (void)

void vsf_hw_mpu_add_basic_resgions (void)

bool vsf_driver_init (void)

common hal drivers

void vsf_arch_sleep (uint_fast32_t mode)

Variables
const vsf_hw_clk_t	VSF_HW_CLK_HSI

const vsf_hw_clk_t	VSF_HW_CLK_HSI_CG

const vsf_hw_clk_t	VSF_HW_CLK_HSI_KER_CG

const vsf_hw_clk_t	VSF_HW_CLK_MSI

const vsf_hw_clk_t	VSF_HW_CLK_MSI_CG

const vsf_hw_clk_t	VSF_HW_CLK_MSI_KER_CG

const vsf_hw_clk_t	VSF_HW_CLK_LSI

const vsf_hw_clk_t	VSF_HW_CLK_PLL1

const vsf_hw_clk_t	VSF_HW_CLK_PLL2

const vsf_hw_clk_t	VSF_HW_CLK_PLL3

const vsf_hw_clk_t	VSF_HW_CLK_SHRPLL

const vsf_hw_clk_t	VSF_HW_CLK_PLL1A

const vsf_hw_clk_t	VSF_HW_CLK_PLL1B

const vsf_hw_clk_t	VSF_HW_CLK_PLL1C

const vsf_hw_clk_t	VSF_HW_CLK_PLL2A

const vsf_hw_clk_t	VSF_HW_CLK_PLL2B

const vsf_hw_clk_t	VSF_HW_CLK_PLL2C

const vsf_hw_clk_t	VSF_HW_CLK_PLL3A

const vsf_hw_clk_t	VSF_HW_CLK_PLL3B

const vsf_hw_clk_t	VSF_HW_CLK_PLL3C

const vsf_hw_clk_t	VSF_HW_CLK_SYS

const vsf_hw_clk_t	VSF_HW_CLK_SYSBUS

const vsf_hw_clk_t	VSF_HW_CLK_AXISYS

const vsf_hw_clk_t	VSF_HW_CLK_M7HYP

const vsf_hw_clk_t	VSF_HW_CLK_AXIHYP

const vsf_hw_clk_t	VSF_HW_CLK_AXI

const vsf_hw_clk_t	VSF_HW_CLK_APB1

const vsf_hw_clk_t	VSF_HW_CLK_APB2

const vsf_hw_clk_t	VSF_HW_CLK_APB5

const vsf_hw_clk_t	VSF_HW_CLK_APB6

const vsf_hw_clk_t	VSF_HW_CLK_PERI

const vsf_hw_clk_t	VSF_HW_CLK_SDRAM_AXI

const vsf_hw_clk_t	VSF_HW_CLK_SDRAM

const vsf_hw_clk_t	VSF_HW_CLK_SDMMC1_AXI

const vsf_hw_clk_t	VSF_HW_CLK_SDMMC1

const vsf_hw_clk_t	VSF_HW_CLK_SDMMC2

const vsf_hw_clk_t	VSF_HW_CLK_USART1_2

const vsf_hw_clk_t	VSF_HW_CLK_USBREF

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_HCS1

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_HCS2

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_GRC

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_ESC

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_MDMA

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_SHRA

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_SHR2

const vsf_hw_pwr_domain_t	VSF_HW_PWR_DOMAIN_SHR1

const vsf_hw_pwr_t	VSF_HW_PWR_GPU

const vsf_hw_pwr_t	VSF_HW_PWR_LCDC

const vsf_hw_pwr_t	VSF_HW_PWR_JPEG

const vsf_hw_pwr_t	VSF_HW_PWR_DSI

const vsf_hw_pwr_t	VSF_HW_PWR_DVP

const vsf_hw_pwr_t	VSF_HW_PWR_ETH2

const vsf_hw_pwr_t	VSF_HW_PWR_USB2

const vsf_hw_pwr_t	VSF_HW_PWR_SDMMC2

const vsf_hw_pwr_t	VSF_HW_PWR_ETH1

const vsf_hw_pwr_t	VSF_HW_PWR_USB1

const vsf_hw_pwr_t	VSF_HW_PWR_SDMMC1

const vsf_hw_pwr_t	VSF_HW_PWR_FMAC

const vsf_hw_pwr_t	VSF_HW_PWR_ESC

Macro Definition Documentation

◆ VCO_MIN

#define VCO_MIN 300000000

◆ VCO_MAX

#define VCO_MAX 1250000000

◆ REF_MIN

#define REF_MIN 1000000

◆ REF_MAX

#define REF_MAX 64000000

◆ NR_MIN

#define NR_MIN 1

◆ NR_MAX

#define NR_MAX 64

◆ NF_MIN

#define NF_MIN 2

◆ NF_MAX

#define NF_MAX 4095

◆ RCC_REG_BIT_MASK

#define RCC_REG_BIT_MASK ((uint32_t)0x00000000)

RCC R_BIT_MASK

◆ RCC_PLL_BWAJ_MASK

#define RCC_PLL_BWAJ_MASK (~RCC_PLL1CTRL1_PLL1BWAJ)

PLL_clock

◆ RCC_PLL_CLKR_CLKF_MASK

#define RCC_PLL_CLKR_CLKF_MASK (RCC_REG_BIT_MASK)

◆ RCC_PLL_SRC_MASK

#define RCC_PLL_SRC_MASK (~RCC_PLL1CTRL1_PLL1SRC)

◆ RCC_PLL_LOCK_FLAG

#define RCC_PLL_LOCK_FLAG (RCC_PLL1CTRL1_PLL1PHLK)

◆ RCC_PLL_LDO_ENABLE

#define RCC_PLL_LDO_ENABLE (RCC_PLL1CTRL1_PLL1LDOEN)

◆ RCC_PLL_ENABLE

#define RCC_PLL_ENABLE (RCC_PLL1CTRL1_PLL1EN )

◆ RCC_PLL_RESET_ENABLE

#define RCC_PLL_RESET_ENABLE (RCC_PLL1CTRL1_PLL1RST )

◆ RCC_PLL_POWER_DOWN

#define RCC_PLL_POWER_DOWN (RCC_PLL1CTRL1_PLL1PD )

◆ __RCC_DELAY_US

#define __RCC_DELAY_US ( usec )

Value:

                                    do{                                       \
                                    uint32_t delay_end;                   \
                                    CPU_DELAY_INTI();                     \
                                    /* Delay*/                            \
                                    delay_end = DWT_CYCCNT + (usec * (600000000/1000000)); \
                                    while(DWT_CYCCNT < delay_end){};      \
                                    CPU_DELAY_DISABLE();                  \
                                  }while(0)

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
VSF_HW_CLK_PRESCALER_NONE
VSF_HW_CLK_PRESCALER_CONST
VSF_HW_CLK_PRESCALER_DIV
VSF_HW_CLK_PRESCALER_FUNC

◆ anonymous enum

anonymous enum

Enumerator
VSF_HW_CLK_TYPE_CONST
VSF_HW_CLK_TYPE_CLK
VSF_HW_CLK_TYPE_SEL

Function Documentation

◆ vsf_hw_clkrst_region_set()

void vsf_hw_clkrst_region_set	(	uint32_t	region,
		uint_fast8_t	value
	)

◆ vsf_hw_clkrst_region_get()

uint_fast8_t vsf_hw_clkrst_region_get ( uint32_t region )

◆ vsf_hw_clkrst_region_set_bit()

void vsf_hw_clkrst_region_set_bit ( uint32_t region )

◆ vsf_hw_clkrst_region_clear_bit()

void vsf_hw_clkrst_region_clear_bit ( uint32_t region )

◆ vsf_hw_clkrst_region_get_bit()

uint_fast8_t vsf_hw_clkrst_region_get_bit ( uint32_t region )

◆ vsf_hw_clk_get_src()

const vsf_hw_clk_t * vsf_hw_clk_get_src ( const vsf_hw_clk_t * clk )

◆ vsf_hw_clk_get_freq_hz()

uint32_t vsf_hw_clk_get_freq_hz ( const vsf_hw_clk_t * clk )

◆ vsf_hw_clk_enable()

void vsf_hw_clk_enable ( const vsf_hw_clk_t * clk )

◆ vsf_hw_clk_disable()

void vsf_hw_clk_disable ( const vsf_hw_clk_t * clk )

◆ vsf_hw_clk_is_enabled()

bool vsf_hw_clk_is_enabled ( const vsf_hw_clk_t * clk )

◆ vsf_hw_clk_is_ready()

bool vsf_hw_clk_is_ready ( const vsf_hw_clk_t * clk )

◆ vsf_hw_clk_config()

vsf_err_t vsf_hw_clk_config	(	const vsf_hw_clk_t *	clk,
		const vsf_hw_clk_t *	clksrc,
		uint16_t	prescaler,
		uint32_t	freq_hz
	)

◆ RCC_CalculatePLLParam()

ErrorStatus RCC_CalculatePLLParam	(	uint64_t	fin,
		uint64_t	fout,
		uint32_t *	nr,
		uint32_t *	nf,
		uint32_t *	wb
	)

◆ vsf_hw_pll_config()

vsf_err_t vsf_hw_pll_config	(	const vsf_hw_clk_t *	clk,
		uint32_t	out_freq_hz
	)

configure frequency range of pll input/output clocks

Parameters

[in]	clk	a pointer to PLL clock VSF_HW_CLK_PLL1 VSF_HW_CLK_PLL2 VSF_HW_CLK_PLL3
[in]	out_freq_hz	PLL output frequency in Hz

◆ vsf_hw_power_domain_enable()

void vsf_hw_power_domain_enable ( const vsf_hw_pwr_domain_t * domain )

◆ vsf_hw_power_domain_disable()

void vsf_hw_power_domain_disable ( const vsf_hw_pwr_domain_t * domain )

◆ vsf_hw_power_domain_is_ready()

bool vsf_hw_power_domain_is_ready ( const vsf_hw_pwr_domain_t * domain )

◆ vsf_hw_power_enable()

void vsf_hw_power_enable ( const vsf_hw_pwr_t * pwr )

◆ vsf_hw_power_disable()

void vsf_hw_power_disable ( const vsf_hw_pwr_t * pwr )

◆ HardFault_Handler()

void HardFault_Handler ( void )

◆ MemManage_Handler()

void MemManage_Handler ( void )

◆ BusFault_Handler()

void BusFault_Handler ( void )

◆ vsf_hw_mpu_add_basic_resgions()

void vsf_hw_mpu_add_basic_resgions ( void )

◆ vsf_driver_init()

bool vsf_driver_init ( void )

common hal drivers

Note: initialize device driver

Parameters

none

Return values

true	initialization succeeded.
false	initialization failed

initialise interrupt controller;

◆ vsf_arch_sleep()

void vsf_arch_sleep ( uint_fast32_t mode )

Variable Documentation

◆ VSF_HW_CLK_HSI

const vsf_hw_clk_t VSF_HW_CLK_HSI

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x0C, 0, 1), 
    .clkrdy_region              = VSF_HW_CLKRST_REGION(0x0C, 1, 1), 
    
    .clk_freq_hz                = HSI_VALUE,
    .clksrc_type                = VSF_HW_CLK_TYPE_CONST,
 
}

◆ VSF_HW_CLK_HSI_CG

const vsf_hw_clk_t VSF_HW_CLK_HSI_CG

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x5A, 15, 1),
 
    .clksrc                     = &__VSF_HW_CLK_HSI_RDY,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
}

◆ VSF_HW_CLK_HSI_KER_CG

const vsf_hw_clk_t VSF_HW_CLK_HSI_KER_CG

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x5A, 14, 1),
 
    .clksrc                     = &__VSF_HW_CLK_HSI_RDY,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
}

◆ VSF_HW_CLK_MSI

const vsf_hw_clk_t VSF_HW_CLK_MSI

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x0C, 6, 1), 
    .clkdly_region              = VSF_HW_CLKRST_REGION(0x65, 0, 32),
 
    .clk_freq_hz                = MSI_VALUE,
    .clksrc_type                = VSF_HW_CLK_TYPE_CONST,
 
}

◆ VSF_HW_CLK_MSI_CG

const vsf_hw_clk_t VSF_HW_CLK_MSI_CG

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x5A, 11, 1),
 
    .clksrc                     = &__VSF_HW_CLK_MSI_RDY,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
}

◆ VSF_HW_CLK_MSI_KER_CG

const vsf_hw_clk_t VSF_HW_CLK_MSI_KER_CG

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x5A, 10, 1),
 
    .clksrc                     = &__VSF_HW_CLK_MSI_RDY,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
}

◆ VSF_HW_CLK_LSI

const vsf_hw_clk_t VSF_HW_CLK_LSI

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x49, 0, 1), 
 
    .clk_freq_hz                = LSI_VALUE,
    .clksrc_type                = VSF_HW_CLK_TYPE_CONST,
 
}

◆ VSF_HW_CLK_PLL1

const vsf_hw_clk_t VSF_HW_CLK_PLL1

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x00, 18, 1),
    .clksel_region              = VSF_HW_CLKRST_REGION(0x00, 28, 2),
 
    .clksel_mapper              = __VSF_HW_CLK_PLL_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
 
    .getclk                     = __vsf_hw_pll_getclk,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_FUNC,
}

◆ VSF_HW_CLK_PLL2

const vsf_hw_clk_t VSF_HW_CLK_PLL2

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x04, 18, 1),
    .clksel_region              = VSF_HW_CLKRST_REGION(0x04, 28, 2),
 
    .clksel_mapper              = __VSF_HW_CLK_PLL_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
 
    .getclk                     = __vsf_hw_pll_getclk,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_FUNC,
}

◆ VSF_HW_CLK_PLL3

const vsf_hw_clk_t VSF_HW_CLK_PLL3

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x08, 18, 1),
    .clksel_region              = VSF_HW_CLKRST_REGION(0x08, 28, 2),
 
    .clksel_mapper              = __VSF_HW_CLK_PLL_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
 
    .getclk                     = __vsf_hw_pll_getclk,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_FUNC,
}

◆ VSF_HW_CLK_SHRPLL

const vsf_hw_clk_t VSF_HW_CLK_SHRPLL

Initial value:

= {
    .clken_region               = VSF_HW_CLKRST_REGION(0x63, 18, 1),
    .clksel_region              = VSF_HW_CLKRST_REGION(0x63, 28, 2),
 
    .clksel_mapper              = __VSF_HW_CLK_PLL_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
 
    .getclk                     = __vsf_hw_pll_getclk,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_FUNC,
}

◆ VSF_HW_CLK_PLL1A

const vsf_hw_clk_t VSF_HW_CLK_PLL1A

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0D, 0, 6), 
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL1B

const vsf_hw_clk_t VSF_HW_CLK_PLL1B

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0D, 8, 6), 
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL1C

const vsf_hw_clk_t VSF_HW_CLK_PLL1C

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0D, 16, 6),
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL2A

const vsf_hw_clk_t VSF_HW_CLK_PLL2A

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0E, 0, 6), 
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL2B

const vsf_hw_clk_t VSF_HW_CLK_PLL2B

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0E, 8, 6), 
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL2C

const vsf_hw_clk_t VSF_HW_CLK_PLL2C

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0E, 16, 6),
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL3A

const vsf_hw_clk_t VSF_HW_CLK_PLL3A

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0F, 0, 6), 
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL3B

const vsf_hw_clk_t VSF_HW_CLK_PLL3B

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0F, 8, 6), 
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_PLL3C

const vsf_hw_clk_t VSF_HW_CLK_PLL3C

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x0F, 16, 6),
 
    .clksrc                     = &VSF_HW_CLK_PLL1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 1,
    .clkprescaler_max           = 63,
}

◆ VSF_HW_CLK_SYS

const vsf_hw_clk_t VSF_HW_CLK_SYS

Initial value:

= {
    .clksel_region              = VSF_HW_CLKRST_REGION(0x0C, 24, 2),
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x10, 0, 4), 
 
    .clksel_mapper              = __VSF_HW_CLK_SYS_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
}

◆ VSF_HW_CLK_SYSBUS

const vsf_hw_clk_t VSF_HW_CLK_SYSBUS

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x10, 8, 4), 
 
    .clksrc                     = &VSF_HW_CLK_SYS,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
}

◆ VSF_HW_CLK_AXISYS

const vsf_hw_clk_t VSF_HW_CLK_AXISYS

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x10, 12, 4),
 
    .clksrc                     = &VSF_HW_CLK_SYS,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
}

◆ VSF_HW_CLK_M7HYP

const vsf_hw_clk_t VSF_HW_CLK_M7HYP

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x10, 16, 4),
 
    .clksrc                     = &VSF_HW_CLK_PLL2A,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
}

◆ VSF_HW_CLK_AXIHYP

const vsf_hw_clk_t VSF_HW_CLK_AXIHYP

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x10, 24, 4),
 
    .clksrc                     = &VSF_HW_CLK_M7HYP,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
}

◆ VSF_HW_CLK_AXI

const vsf_hw_clk_t VSF_HW_CLK_AXI

Initial value:

= {
    .clksel_region              = VSF_HW_CLKRST_REGION(0x5B, 16, 1),
 
    .clksel_mapper              = __VSF_HW_CLK_AXI_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
}

◆ VSF_HW_CLK_APB1

const vsf_hw_clk_t VSF_HW_CLK_APB1

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x11, 0, 3), 
 
    .clksrc                     = &VSF_HW_CLK_SYSBUS,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_APB_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_APB_PRESCALER) - 1,
}

◆ VSF_HW_CLK_APB2

const vsf_hw_clk_t VSF_HW_CLK_APB2

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x11, 8, 3), 
 
    .clksrc                     = &VSF_HW_CLK_SYSBUS,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_APB_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_APB_PRESCALER) - 1,
}

◆ VSF_HW_CLK_APB5

const vsf_hw_clk_t VSF_HW_CLK_APB5

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x11, 16, 3),
 
    .clksrc                     = &VSF_HW_CLK_SYSBUS,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_APB_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_APB_PRESCALER) - 1,
}

◆ VSF_HW_CLK_APB6

const vsf_hw_clk_t VSF_HW_CLK_APB6

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x11, 24, 3),
 
    .clksrc                     = &VSF_HW_CLK_AXI,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_APB_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_APB_PRESCALER) - 1,
}

◆ VSF_HW_CLK_PERI

const vsf_hw_clk_t VSF_HW_CLK_PERI

Initial value:

= {
    .clksel_region              = VSF_HW_CLKRST_REGION(0x59, 12, 2),
 
    .clksel_mapper              = __VSF_HW_CLK_PERI_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
}

◆ VSF_HW_CLK_SDRAM_AXI

const vsf_hw_clk_t VSF_HW_CLK_SDRAM_AXI

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x5E, 8, 4), 
 
    .clksrc                     = &VSF_HW_CLK_AXI,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
    
}

◆ VSF_HW_CLK_SDRAM

const vsf_hw_clk_t VSF_HW_CLK_SDRAM

Initial value:

= {
    .clksel_region              = VSF_HW_CLKRST_REGION(0x5F, 8, 3), 
 
    .clksel_mapper              = __VSF_HW_CLK_SDRAM_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
}

◆ VSF_HW_CLK_SDMMC1_AXI

const vsf_hw_clk_t VSF_HW_CLK_SDMMC1_AXI

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x4E, 20, 4),
 
    .clksrc                     = &VSF_HW_CLK_AXI,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_SYSBUS_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_SYSBUS_PRESCALER) - 1,
    
}

◆ VSF_HW_CLK_SDMMC1

const vsf_hw_clk_t VSF_HW_CLK_SDMMC1

Initial value:

= {
    .clksel_region              = VSF_HW_CLKRST_REGION(0x4F, 20, 3),
 
    .clksel_mapper              = __VSF_HW_CLK_SDMMC1_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
}

◆ VSF_HW_CLK_SDMMC2

const vsf_hw_clk_t VSF_HW_CLK_SDMMC2

Initial value:

= {
    .clksel_region              = VSF_HW_CLKRST_REGION(0x14, 12, 3),
 
    .clksel_mapper              = __VSF_HW_CLK_SDMMC2_CLKSEL_MAPPER,
    .clksrc_type                = VSF_HW_CLK_TYPE_SEL,
}

◆ VSF_HW_CLK_USART1_2

const vsf_hw_clk_t VSF_HW_CLK_USART1_2

Initial value:

= {
    .clkprescaler_region        = VSF_HW_CLKRST_REGION(0x1D, 28, 3),
 
    .clksrc                     = &VSF_HW_CLK_AHB1,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_APB_PRESCALER,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_APB_PRESCALER) - 1,
}

◆ VSF_HW_CLK_USBREF

const vsf_hw_clk_t VSF_HW_CLK_USBREF

Initial value:

= {
    .clkprescaler_region        = VSF_HW_REG_REGION(0x2A, 9, 4),    
 
    .clksrc                     = &VSF_HW_CLK_HSE,
    .clksrc_type                = VSF_HW_CLK_TYPE_CLK,
 
    .clkprescaler_mapper        = __VSF_HW_CLK_USBHSEDIV,
    .clkprescaler_type          = VSF_HW_CLK_PRESCALER_DIV,
    .clkprescaler_min           = 0,
    .clkprescaler_max           = dimof(__VSF_HW_CLK_USBHSEDIV) - 1,
}

◆ VSF_HW_PWR_DOMAIN_HCS1

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_HCS1

Initial value:

= {
    .mask                       = PWR_IPMEMCTRL_ETH1_PWREN
                                | PWR_IPMEMCTRL_USB1_PWREN
                                | PWR_IPMEMCTRL_SDMMC1_PWREN,
    .reg_word_offset            = 0x4C >> 2,        
    .ack_offset                 = 21,               
    .en_offset                  = 1,                
    .rdy_offset                 = 17,               
    .iso_offset                 = 9,                
    .func_offset                = 5,                
}

◆ VSF_HW_PWR_DOMAIN_HCS2

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_HCS2

Initial value:

= {
    .mask                       = PWR_IPMEMCTRL_ETH2_PWREN
                                | PWR_IPMEMCTRL_USB2_PWREN
                                | PWR_IPMEMCTRL_SDMMC2_PWREN,
    .reg_word_offset            = 0x4C >> 2,        
    .ack_offset                 = 22,               
    .en_offset                  = 2,                
    .rdy_offset                 = 18,               
    .iso_offset                 = 10,               
    .func_offset                = 6,                
}

◆ VSF_HW_PWR_DOMAIN_GRC

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_GRC

Initial value:

= {
    .mask                       = PWR_IPMEMCTRL_GPU_PWREN
                                | PWR_IPMEMCTRL_LCDC_PWREN
                                | PWR_IPMEMCTRL_JPEG_PWREN
                                | PWR_IPMEMCTRL_DSI_PWREN
                                | PWR_IPMEMCTRL_DVP_PWREN,
    .reg_word_offset            = 0x4C >> 2,        
    .ack_offset                 = 20,               
    .en_offset                  = 0,                
    .rdy_offset                 = 16,               
    .iso_offset                 = 8,                
    .func_offset                = 4,                
}

◆ VSF_HW_PWR_DOMAIN_ESC

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_ESC

Initial value:

= {
    .mask                       = PWR_IPMEMCTRL_ESC_PWREN,
    .reg_word_offset            = 0xB8 >> 2,        
    .ack_offset                 = 4,                
    .en_offset                  = 0,                
    .rdy_offset                 = 3,                
    .iso_offset                 = 2,                
    .func_offset                = 1,                
}

◆ VSF_HW_PWR_DOMAIN_MDMA

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_MDMA

Initial value:

= {
    .reg_word_offset            = 0xB4 >> 2,        
    .ack_offset                 = 4,                
    .en_offset                  = 0,                
    .rdy_offset                 = 3,                
    .iso_offset                 = 2,                
    .func_offset                = 1,                
}

◆ VSF_HW_PWR_DOMAIN_SHRA

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_SHRA

Initial value:

= {
    .reg_word_offset            = 0xB0 >> 2,        
    .ack_offset                 = 20,               
    .en_offset                  = 16,               
    .rdy_offset                 = 19,               
    .iso_offset                 = 18,               
    .func_offset                = 17,               
}

◆ VSF_HW_PWR_DOMAIN_SHR2

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_SHR2

Initial value:

= {
    .reg_word_offset            = 0xB0 >> 2,        
    .ack_offset                 = 12,               
    .en_offset                  = 8,                
    .rdy_offset                 = 11,               
    .iso_offset                 = 10,               
    .func_offset                = 9,                
}

◆ VSF_HW_PWR_DOMAIN_SHR1

const vsf_hw_pwr_domain_t VSF_HW_PWR_DOMAIN_SHR1

Initial value:

= {
    .reg_word_offset            = 0xB0 >> 2,        
    .ack_offset                 = 4,                
    .en_offset                  = 0,                
    .rdy_offset                 = 3,                
    .iso_offset                 = 2,                
    .func_offset                = 1,                
}

◆ VSF_HW_PWR_GPU

const vsf_hw_pwr_t VSF_HW_PWR_GPU

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_GRC,
    .ipmem_bitoffset            = 0,
}

◆ VSF_HW_PWR_LCDC

const vsf_hw_pwr_t VSF_HW_PWR_LCDC

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_GRC,
    .ipmem_bitoffset            = 1,
}

◆ VSF_HW_PWR_JPEG

const vsf_hw_pwr_t VSF_HW_PWR_JPEG

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_GRC,
    .ipmem_bitoffset            = 2,
}

◆ VSF_HW_PWR_DSI

const vsf_hw_pwr_t VSF_HW_PWR_DSI

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_GRC,
    .ipmem_bitoffset            = 3,
}

◆ VSF_HW_PWR_DVP

const vsf_hw_pwr_t VSF_HW_PWR_DVP

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_GRC,
    .ipmem_bitoffset            = 4,
}

◆ VSF_HW_PWR_ETH2

const vsf_hw_pwr_t VSF_HW_PWR_ETH2

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_HCS2,
    .ipmem_bitoffset            = 5,
}

◆ VSF_HW_PWR_USB2

const vsf_hw_pwr_t VSF_HW_PWR_USB2

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_HCS2,
    .ipmem_bitoffset            = 6,
}

◆ VSF_HW_PWR_SDMMC2

const vsf_hw_pwr_t VSF_HW_PWR_SDMMC2

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_HCS2,
    .ipmem_bitoffset            = 7,
}

◆ VSF_HW_PWR_ETH1

const vsf_hw_pwr_t VSF_HW_PWR_ETH1

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_HCS1,
    .ipmem_bitoffset            = 8,
}

◆ VSF_HW_PWR_USB1

const vsf_hw_pwr_t VSF_HW_PWR_USB1

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_HCS1,
    .ipmem_bitoffset            = 9,
}

◆ VSF_HW_PWR_SDMMC1

const vsf_hw_pwr_t VSF_HW_PWR_SDMMC1

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_HCS1,
    .ipmem_bitoffset            = 10,
}

◆ VSF_HW_PWR_FMAC

const vsf_hw_pwr_t VSF_HW_PWR_FMAC

Initial value:

= {
    .domain                     = NULL,
    .ipmem_bitoffset            = 11,
}

◆ VSF_HW_PWR_ESC

const vsf_hw_pwr_t VSF_HW_PWR_ESC

Initial value:

= {
    .domain                     = &VSF_HW_PWR_DOMAIN_ESC,
    .ipmem_bitoffset            = 12,
}

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ VCO_MIN

◆ VCO_MAX

◆ REF_MIN

◆ REF_MAX

◆ NR_MIN

◆ NR_MAX

◆ NF_MIN

◆ NF_MAX

◆ RCC_REG_BIT_MASK

◆ RCC_PLL_BWAJ_MASK

◆ RCC_PLL_CLKR_CLKF_MASK

◆ RCC_PLL_SRC_MASK

◆ RCC_PLL_LOCK_FLAG

◆ RCC_PLL_LDO_ENABLE

◆ RCC_PLL_ENABLE

◆ RCC_PLL_RESET_ENABLE

◆ RCC_PLL_POWER_DOWN

◆ __RCC_DELAY_US

Enumeration Type Documentation

◆ anonymous enum

◆ anonymous enum

Function Documentation

◆ vsf_hw_clkrst_region_set()

◆ vsf_hw_clkrst_region_get()

◆ vsf_hw_clkrst_region_set_bit()

◆ vsf_hw_clkrst_region_clear_bit()

◆ vsf_hw_clkrst_region_get_bit()

◆ vsf_hw_clk_get_src()

◆ vsf_hw_clk_get_freq_hz()

◆ vsf_hw_clk_enable()

◆ vsf_hw_clk_disable()

◆ vsf_hw_clk_is_enabled()

◆ vsf_hw_clk_is_ready()

◆ vsf_hw_clk_config()

◆ RCC_CalculatePLLParam()

◆ vsf_hw_pll_config()

◆ vsf_hw_power_domain_enable()

◆ vsf_hw_power_domain_disable()

◆ vsf_hw_power_domain_is_ready()

◆ vsf_hw_power_enable()

◆ vsf_hw_power_disable()

◆ HardFault_Handler()

◆ MemManage_Handler()

◆ BusFault_Handler()

◆ vsf_hw_mpu_add_basic_resgions()

◆ vsf_driver_init()

◆ vsf_arch_sleep()

Variable Documentation

◆ VSF_HW_CLK_HSI

◆ VSF_HW_CLK_HSI_CG

◆ VSF_HW_CLK_HSI_KER_CG

◆ VSF_HW_CLK_MSI

◆ VSF_HW_CLK_MSI_CG

◆ VSF_HW_CLK_MSI_KER_CG

◆ VSF_HW_CLK_LSI

◆ VSF_HW_CLK_PLL1

◆ VSF_HW_CLK_PLL2

◆ VSF_HW_CLK_PLL3

◆ VSF_HW_CLK_SHRPLL

◆ VSF_HW_CLK_PLL1A

◆ VSF_HW_CLK_PLL1B

◆ VSF_HW_CLK_PLL1C

◆ VSF_HW_CLK_PLL2A

◆ VSF_HW_CLK_PLL2B

◆ VSF_HW_CLK_PLL2C

◆ VSF_HW_CLK_PLL3A

◆ VSF_HW_CLK_PLL3B

◆ VSF_HW_CLK_PLL3C

◆ VSF_HW_CLK_SYS

◆ VSF_HW_CLK_SYSBUS

◆ VSF_HW_CLK_AXISYS

◆ VSF_HW_CLK_M7HYP

◆ VSF_HW_CLK_AXIHYP

◆ VSF_HW_CLK_AXI