device.h File Reference

#include "hal/vsf_hal_cfg.h"

Go to the source code of this file.

Macros
#define	__VSF_HAL_DEVICE_   ${VENDOR}_${DEVICE}_H__
#define	VSF_DEV_SWI_NUM   0
#define	VSF_HW_GPIO_PORT_COUNT   1
#define	VSF_HW_GPIO_PIN_COUNT   32
#define	VSF_HW_I2C_COUNT   2
#define	VSF_HW_I2C_MASK   0x05
#define	VSF_HW_I2C0_IRQN   I2C0_IRQn
#define	VSF_HW_I2C0_IRQHandler   I2C0_IRQHandler
#define	VSF_HW_I2C0_REG   I2C0_BASE
#define	VSF_HW_I2C2_IRQN   I2C2_IRQn
#define	VSF_HW_I2C2_IRQHandler   I2C2_IRQHandler
#define	VSF_HW_I2C2_REG   I2C2_BASE
#define	VSF_HW_SPI_COUNT   2
#define	VSF_HW_SPI0_IRQN   SPI0_IRQn
#define	VSF_HW_SPI0_IRQHandler   SPI0_IRQHandler
#define	VSF_HW_SPI0_REG   SPI0_BASE
#define	VSF_HW_SPI1_IRQN   SPI1_IRQn
#define	VSF_HW_SPI1_IRQHandler   SPI1_IRQHandler
#define	VSF_HW_SPI1_REG   SPI1_BASE
#define	VSF_HW_QSPI_COUNT   1
#define	VSF_HW_QSPI0_IRQN   QSPI0_IRQn
#define	VSF_HW_QSPI0_IRQHandler   QSPI0_IRQHandler
#define	VSF_HW_QSPI0_REG   QSPI0_BASE
#define	VSF_HW_QSPI1_IRQN   QSPI1_IRQn
#define	VSF_HW_QSPI1_IRQHandler   QSPI1_IRQHandler
#define	VSF_HW_QSPI1_REG   QSPI1_BASE

Macro Definition Documentation

__VSF_HAL_DEVICE_

#define __VSF_HAL_DEVICE_   ${VENDOR}_${DEVICE}_H__

VSF_DEV_SWI_NUM

#define VSF_DEV_SWI_NUM   0

VSF_HW_GPIO_PORT_COUNT

#define VSF_HW_GPIO_PORT_COUNT   1

VSF_HW_GPIO_PIN_COUNT

#define VSF_HW_GPIO_PIN_COUNT   32

VSF_HW_I2C_COUNT

#define VSF_HW_I2C_COUNT   2

VSF_HW_I2C_MASK

#define VSF_HW_I2C_MASK   0x05

VSF_HW_I2C0_IRQN

#define VSF_HW_I2C0_IRQN   I2C0_IRQn

VSF_HW_I2C0_IRQHandler

#define VSF_HW_I2C0_IRQHandler   I2C0_IRQHandler

VSF_HW_I2C0_REG

#define VSF_HW_I2C0_REG   I2C0_BASE

VSF_HW_I2C2_IRQN

#define VSF_HW_I2C2_IRQN   I2C2_IRQn

VSF_HW_I2C2_IRQHandler

#define VSF_HW_I2C2_IRQHandler   I2C2_IRQHandler

VSF_HW_I2C2_REG

#define VSF_HW_I2C2_REG   I2C2_BASE

VSF_HW_SPI_COUNT

#define VSF_HW_SPI_COUNT   2

VSF_HW_SPI0_IRQN

#define VSF_HW_SPI0_IRQN   SPI0_IRQn

VSF_HW_SPI0_IRQHandler

#define VSF_HW_SPI0_IRQHandler   SPI0_IRQHandler

VSF_HW_SPI0_REG

#define VSF_HW_SPI0_REG   SPI0_BASE

VSF_HW_SPI1_IRQN

#define VSF_HW_SPI1_IRQN   SPI1_IRQn

VSF_HW_SPI1_IRQHandler

#define VSF_HW_SPI1_IRQHandler   SPI1_IRQHandler

VSF_HW_SPI1_REG

#define VSF_HW_SPI1_REG   SPI1_BASE

VSF_HW_QSPI_COUNT

#define VSF_HW_QSPI_COUNT   1

VSF_HW_QSPI0_IRQN

#define VSF_HW_QSPI0_IRQN   QSPI0_IRQn

VSF_HW_QSPI0_IRQHandler

#define VSF_HW_QSPI0_IRQHandler   QSPI0_IRQHandler

VSF_HW_QSPI0_REG

#define VSF_HW_QSPI0_REG   QSPI0_BASE

VSF_HW_QSPI1_IRQN

#define VSF_HW_QSPI1_IRQN   QSPI1_IRQn

VSF_HW_QSPI1_IRQHandler

#define VSF_HW_QSPI1_IRQHandler   QSPI1_IRQHandler

VSF_HW_QSPI1_REG

#define VSF_HW_QSPI1_REG   QSPI1_BASE