Go to the source code of this file.
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enum | vsf_usart_mode_t {
VSF_USART_8_BIT_LENGTH = (0x3ul << 5)
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VSF_USART_7_BIT_LENGTH = (0x2ul << 5)
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VSF_USART_6_BIT_LENGTH = (0x1ul << 5)
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VSF_USART_5_BIT_LENGTH = (0x0ul << 5)
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VSF_USART_1_STOPBIT = (0x0ul << 3)
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VSF_USART_2_STOPBIT = (0x1ul << 3)
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VSF_USART_NO_PARITY = 0x0ul
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VSF_USART_ODD_PARITY = 0x2ul
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VSF_USART_EVEN_PARITY = 0x6ul
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VSF_USART_FORCE_0_PARITY = 0xEul
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VSF_USART_FORCE_1_PARITY = 0xAul
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PL011_USART_BIT_LENGTH_MASK
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PL011_USART_STOPBIT_MASK
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PL011_USART_PARITY_MASK
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PL011_USART_MODE_MASK
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VSF_USART_TX_ENABLE = (0x1ul << (8 + 8))
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VSF_USART_TX_DISABLE = (0x0ul << (8 + 8))
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VSF_USART_RX_ENABLE = (0x1ul << (8 + 9))
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VSF_USART_RX_DISABLE = (0x0ul << (8 + 9))
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VSF_USART_NO_HWCONTROL = (0x0ul << (8 + 14))
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VSF_USART_RTS_HWCONTROL = (0x1ul << (8 + 14))
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VSF_USART_CTS_HWCONTROL = (0x2ul << (8 + 14))
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VSF_USART_RTS_CTS_HWCONTROL = (0x3ul << (8 + 14))
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PL011_USART_ENABLE_MASK
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VSF_USART_9_BIT_LENGTH = (0x1ul << 24)
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VSF_USART_1_5_STOPBIT = (0x1ul << 25)
} |
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enum | vsf_usart_irq_mask_t {
VSF_USART_IRQ_MASK_RX = (0x1ul << 4)
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VSF_USART_IRQ_MASK_TX = (0x1ul << 5)
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VSF_USART_IRQ_MASK_RX_TIMEOUT = (0x1ul << 6)
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VSF_USART_IRQ_MASK_FRAME_ERR = (0x1ul << 7)
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VSF_USART_IRQ_MASK_PARITY_ERR = (0x1ul << 8)
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VSF_USART_IRQ_MASK_BREAK_ERR = (0x1ul << 9)
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VSF_USART_IRQ_MASK_OVERFLOW_ERR = (0x1ul << 10)
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PL011_USART_IRQ_MASK_ERROR
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PL011_USART_IRQ_MASK_FIFO
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PL011_USART_IRQ_MASK
} |
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vsf_err_t | vsf_pl011_usart_init (vsf_pl011_usart_t *pl011_usart_ptr, vsf_usart_cfg_t *cfg_ptr, uint_fast32_t clk_hz) |
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void | vsf_pl011_usart_fini (vsf_pl011_usart_t *pl011_usart_ptr) |
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vsf_usart_capability_t | vsf_pl011_usart_capability (vsf_pl011_usart_t *pl011_usart_ptr, uint_fast32_t clk_hz) |
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fsm_rt_t | vsf_pl011_usart_enable (vsf_pl011_usart_t *pl011_usart_ptr) |
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fsm_rt_t | vsf_pl011_usart_disable (vsf_pl011_usart_t *pl011_usart_ptr) |
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vsf_usart_irq_mask_t | vsf_pl011_usart_irq_enable (vsf_pl011_usart_t *pl011_usart_ptr, vsf_usart_irq_mask_t irq_mask) |
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vsf_usart_irq_mask_t | vsf_pl011_usart_irq_disable (vsf_pl011_usart_t *pl011_usart_ptr, vsf_usart_irq_mask_t irq_mask) |
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vsf_usart_status_t | vsf_pl011_usart_status (vsf_pl011_usart_t *pl011_usart_ptr) |
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uint_fast16_t | vsf_pl011_usart_rxfifo_get_data_count (vsf_pl011_usart_t *pl011_usart_ptr) |
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uint_fast16_t | vsf_pl011_usart_rxfifo_read (vsf_pl011_usart_t *pl011_usart_ptr, void *buffer_ptr, uint_fast16_t count) |
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uint_fast16_t | vsf_pl011_usart_txfifo_get_free_count (vsf_pl011_usart_t *pl011_usart_ptr) |
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uint_fast16_t | vsf_pl011_usart_txfifo_write (vsf_pl011_usart_t *pl011_usart_ptr, void *buffer_ptr, uint_fast16_t count) |
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uintptr_t | vsf_pl011_usart_rxdma_config (vsf_pl011_usart_t *pl011_usart_ptr, bool enable) |
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uintptr_t | vsf_pl011_usart_txdma_config (vsf_pl011_usart_t *pl011_usart_ptr, bool enable) |
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void | vsf_pl011_usart_irqhandler (vsf_pl011_usart_t *pl011_usart_ptr) |
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◆ VSF_PL011_USART_CFG_MULTI_CLASS
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_MODE
#define VSF_USART_CFG_REIMPLEMENT_TYPE_MODE ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK
#define VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS
#define VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS ENABLED |
◆ vsf_usart_mode_t
◆ vsf_usart_irq_mask_t
◆ vsf_usart_status_t
◆ vsf_usart_mode_t
Enumerator |
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VSF_USART_8_BIT_LENGTH | |
VSF_USART_7_BIT_LENGTH | |
VSF_USART_6_BIT_LENGTH | |
VSF_USART_5_BIT_LENGTH | |
VSF_USART_1_STOPBIT | |
VSF_USART_2_STOPBIT | |
VSF_USART_NO_PARITY | |
VSF_USART_ODD_PARITY | |
VSF_USART_EVEN_PARITY | |
VSF_USART_FORCE_0_PARITY | |
VSF_USART_FORCE_1_PARITY | |
PL011_USART_BIT_LENGTH_MASK | |
PL011_USART_STOPBIT_MASK | |
PL011_USART_PARITY_MASK | |
PL011_USART_MODE_MASK | |
VSF_USART_TX_ENABLE | |
VSF_USART_TX_DISABLE | |
VSF_USART_RX_ENABLE | |
VSF_USART_RX_DISABLE | |
VSF_USART_NO_HWCONTROL | |
VSF_USART_RTS_HWCONTROL | |
VSF_USART_CTS_HWCONTROL | |
VSF_USART_RTS_CTS_HWCONTROL | |
PL011_USART_ENABLE_MASK | |
VSF_USART_9_BIT_LENGTH | |
VSF_USART_1_5_STOPBIT | |
◆ vsf_usart_irq_mask_t
Enumerator |
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VSF_USART_IRQ_MASK_RX | |
VSF_USART_IRQ_MASK_TX | |
VSF_USART_IRQ_MASK_RX_TIMEOUT | |
VSF_USART_IRQ_MASK_FRAME_ERR | |
VSF_USART_IRQ_MASK_PARITY_ERR | |
VSF_USART_IRQ_MASK_BREAK_ERR | |
VSF_USART_IRQ_MASK_OVERFLOW_ERR | |
PL011_USART_IRQ_MASK_ERROR | |
PL011_USART_IRQ_MASK_FIFO | |
PL011_USART_IRQ_MASK | |
◆ vsf_pl011_usart_init()
◆ vsf_pl011_usart_fini()
◆ vsf_pl011_usart_capability()
◆ vsf_pl011_usart_enable()
◆ vsf_pl011_usart_disable()
◆ vsf_pl011_usart_irq_enable()
◆ vsf_pl011_usart_irq_disable()
◆ vsf_pl011_usart_status()
◆ vsf_pl011_usart_rxfifo_get_data_count()
◆ vsf_pl011_usart_rxfifo_read()
◆ vsf_pl011_usart_txfifo_get_free_count()
◆ vsf_pl011_usart_txfifo_write()
◆ vsf_pl011_usart_rxdma_config()
◆ vsf_pl011_usart_txdma_config()
◆ vsf_pl011_usart_irqhandler()