vsf_pl011_uart.h File Reference

#include "hal/vsf_hal_cfg.h"
#include "utilities/ooc_class.h"
#include "hal/driver/common/template/vsf_template_usart.h"

Go to the source code of this file.

Data Structures
struct	vsf_usart_status_t
	USART status information structure Contains the current status of USART operations and FIFO thresholds. More...
class	vsf_pl011_usart_t

Macros
#define	VSF_PL011_USART_CFG_MULTI_CLASS   VSF_USART_CFG_MULTI_CLASS
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_MODE   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS   ENABLED
#define	VSF_USART_7_BIT_LENGTH   VSF_USART_7_BIT_LENGTH
#define	VSF_USART_6_BIT_LENGTH   VSF_USART_6_BIT_LENGTH
#define	VSF_USART_5_BIT_LENGTH   VSF_USART_5_BIT_LENGTH
#define	VSF_USART_2_STOPBIT   VSF_USART_2_STOPBIT
#define	VSF_USART_FORCE_0_PARITY   VSF_USART_FORCE_0_PARITY
#define	VSF_USART_FORCE_1_PARITY   VSF_USART_FORCE_1_PARITY
#define	VSF_USART_TX_DISABLE   VSF_USART_TX_DISABLE
#define	VSF_USART_RX_DISABLE   VSF_USART_RX_DISABLE
#define	VSF_USART_RTS_HWCONTROL   VSF_USART_RTS_HWCONTROL
#define	VSF_USART_CTS_HWCONTROL   VSF_USART_CTS_HWCONTROL
#define	VSF_USART_RTS_CTS_HWCONTROL   VSF_USART_RTS_CTS_HWCONTROL
#define	VSF_USART_TX_FIFO_THRESHOLD_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_EMPTY
#define	VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY
#define	VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
#define	VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
#define	VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL
#define	VSF_USART_RX_FIFO_THRESHOLD_FULL   VSF_USART_RX_FIFO_THRESHOLD_FULL
#define	VSF_USART_TX_FIFO_THRESHOLD_MASK   (0x3ul << 8)
#define	VSF_USART_RX_FIFO_THRESHOLD_MASK   (0x3ul << 10)
#define	VSF_USART_IRQ_MASK_RX_TIMEOUT   VSF_USART_IRQ_MASK_RX_TIMEOUT
#define	VSF_USART_IRQ_MASK_FRAME_ERR   VSF_USART_IRQ_MASK_FRAME_ERR
#define	VSF_USART_IRQ_MASK_PARITY_ERR   VSF_USART_IRQ_MASK_PARITY_ERR
#define	VSF_USART_IRQ_MASK_BREAK_ERR   VSF_USART_IRQ_MASK_BREAK_ERR
#define	VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR   VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR
#define	VSF_USART_IRQ_MASK_CTS   VSF_USART_IRQ_MASK_CTS
#define	VSF_USART_IRQ_MASK_RX_IDLE   VSF_USART_IRQ_MASK_RX_IDLE

Typedefs
typedef enum vsf_usart_mode_t	vsf_usart_mode_t
typedef enum vsf_usart_irq_mask_t	vsf_usart_irq_mask_t
typedef struct vsf_usart_status_t	vsf_usart_status_t

Enumerations
enum	vsf_usart_mode_t {   VSF_USART_8_BIT_LENGTH = (0x3ul << 5) ,   VSF_USART_7_BIT_LENGTH = (0x2ul << 5) ,   VSF_USART_7_BIT_LENGTH = (0x2ul << 5) ,   VSF_USART_6_BIT_LENGTH = (0x1ul << 5) ,   VSF_USART_6_BIT_LENGTH = (0x1ul << 5) ,   VSF_USART_5_BIT_LENGTH = (0x0ul << 5) ,   VSF_USART_5_BIT_LENGTH = (0x0ul << 5) ,   VSF_USART_1_STOPBIT = (0x0ul << 3) ,   VSF_USART_2_STOPBIT = (0x1ul << 3) ,   VSF_USART_2_STOPBIT = (0x1ul << 3) ,   VSF_USART_NO_PARITY = 0x0ul ,   VSF_USART_ODD_PARITY = 0x2ul ,   VSF_USART_EVEN_PARITY = 0x6ul ,   VSF_USART_FORCE_0_PARITY = 0xEul ,   VSF_USART_FORCE_0_PARITY = 0xEul ,   VSF_USART_FORCE_1_PARITY = 0xAul ,   VSF_USART_FORCE_1_PARITY = 0xAul ,   PL011_USART_BIT_LENGTH_MASK ,   PL011_USART_STOPBIT_MASK ,   PL011_USART_PARITY_MASK ,   PL011_USART_MODE_MASK ,   VSF_USART_TX_ENABLE = (0x1ul << (8 + 8)) ,   VSF_USART_TX_DISABLE = (0x0ul << (8 + 8)) ,   VSF_USART_TX_DISABLE = (0x0ul << (8 + 8)) ,   VSF_USART_RX_ENABLE = (0x1ul << (8 + 9)) ,   VSF_USART_RX_DISABLE = (0x0ul << (8 + 9)) ,   VSF_USART_RX_DISABLE = (0x0ul << (8 + 9)) ,   VSF_USART_NO_HWCONTROL = (0x0ul << (8 + 14)) ,   VSF_USART_RTS_HWCONTROL = (0x1ul << (8 + 14)) ,   VSF_USART_RTS_HWCONTROL = (0x1ul << (8 + 14)) ,   VSF_USART_CTS_HWCONTROL = (0x2ul << (8 + 14)) ,   VSF_USART_CTS_HWCONTROL = (0x2ul << (8 + 14)) ,   VSF_USART_RTS_CTS_HWCONTROL = (0x3ul << (8 + 14)) ,   VSF_USART_RTS_CTS_HWCONTROL = (0x3ul << (8 + 14)) ,   PL011_USART_ENABLE_MASK ,   VSF_USART_9_BIT_LENGTH = (0x1ul << 24) ,   VSF_USART_1_5_STOPBIT = (0x1ul << 25) ,   VSF_USART_0_5_STOPBIT = (0x1ul << 26) ,   VSF_USART_10_BIT_LENGTH = (0x1ul << 27) ,   VSF_USART_SYNC_CLOCK_ENABLE = (0x1ul << 28) ,   VSF_USART_SYNC_CLOCK_DISABLE = 0 ,   VSF_USART_HALF_DUPLEX_ENABLE = (0x1ul << 29) ,   VSF_USART_HALF_DUPLEX_DISABLE = 0 ,   VSF_USART_TX_FIFO_THRESHOLD_EMPTY = (0x0ul << 8) ,   VSF_USART_TX_FIFO_THRESHOLD_EMPTY = (0x0ul << 8) ,   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = (0x1ul << 8) ,   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = (0x1ul << 8) ,   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = (0x2ul << 8) ,   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = (0x2ul << 8) ,   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = (0x0ul << 10) ,   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = (0x0ul << 10) ,   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = (0x1ul << 10) ,   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = (0x1ul << 10) ,   VSF_USART_RX_FIFO_THRESHOLD_FULL = (0x2ul << 10) ,   VSF_USART_RX_FIFO_THRESHOLD_FULL = (0x2ul << 10) }
enum	vsf_usart_irq_mask_t {   VSF_USART_IRQ_MASK_RX = (0x1ul << 4) ,   VSF_USART_IRQ_MASK_TX = (0x1ul << 5) ,   VSF_USART_IRQ_MASK_RX_TIMEOUT = (0x1ul << 6) ,   VSF_USART_IRQ_MASK_RX_TIMEOUT = (0x1ul << 6) ,   VSF_USART_IRQ_MASK_FRAME_ERR = (0x1ul << 7) ,   VSF_USART_IRQ_MASK_FRAME_ERR = (0x1ul << 7) ,   VSF_USART_IRQ_MASK_PARITY_ERR = (0x1ul << 8) ,   VSF_USART_IRQ_MASK_PARITY_ERR = (0x1ul << 8) ,   VSF_USART_IRQ_MASK_BREAK_ERR = (0x1ul << 9) ,   VSF_USART_IRQ_MASK_BREAK_ERR = (0x1ul << 9) ,   VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR = (0x1ul << 10) ,   VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR = (0x1ul << 10) ,   VSF_USART_IRQ_MASK_CTS = (0x1ul << 1) ,   VSF_USART_IRQ_MASK_CTS = (0x1ul << 1) ,   VSF_USART_IRQ_MASK_RX_IDLE = VSF_USART_IRQ_MASK_RX_TIMEOUT ,   VSF_USART_IRQ_MASK_RX_IDLE = VSF_USART_IRQ_MASK_RX_TIMEOUT ,   PL011_USART_IRQ_MASK_ERROR ,   PL011_USART_IRQ_MASK_FIFO ,   PL011_USART_IRQ_MASK ,   __VSF_USART_IRQ_FORCE_INT32 = 0x7FFFFFFF }

Functions
vsf_err_t	vsf_pl011_usart_init (vsf_pl011_usart_t *pl011_usart_ptr, vsf_usart_cfg_t *cfg_ptr, uint_fast32_t clk_hz)
void	vsf_pl011_usart_fini (vsf_pl011_usart_t *pl011_usart_ptr)
vsf_usart_capability_t	vsf_pl011_usart_capability (vsf_pl011_usart_t *pl011_usart_ptr, uint_fast32_t clk_hz)
fsm_rt_t	vsf_pl011_usart_enable (vsf_pl011_usart_t *pl011_usart_ptr)
fsm_rt_t	vsf_pl011_usart_disable (vsf_pl011_usart_t *pl011_usart_ptr)
vsf_usart_irq_mask_t	vsf_pl011_usart_irq_enable (vsf_pl011_usart_t *pl011_usart_ptr, vsf_usart_irq_mask_t irq_mask)
vsf_usart_irq_mask_t	vsf_pl011_usart_irq_disable (vsf_pl011_usart_t *pl011_usart_ptr, vsf_usart_irq_mask_t irq_mask)
vsf_usart_status_t	vsf_pl011_usart_status (vsf_pl011_usart_t *pl011_usart_ptr)
uint_fast16_t	vsf_pl011_usart_rxfifo_get_data_count (vsf_pl011_usart_t *pl011_usart_ptr)
uint_fast16_t	vsf_pl011_usart_rxfifo_read (vsf_pl011_usart_t *pl011_usart_ptr, void *buffer_ptr, uint_fast16_t count)
uint_fast16_t	vsf_pl011_usart_txfifo_get_free_count (vsf_pl011_usart_t *pl011_usart_ptr)
uint_fast16_t	vsf_pl011_usart_txfifo_write (vsf_pl011_usart_t *pl011_usart_ptr, void *buffer_ptr, uint_fast16_t count)
uintptr_t	vsf_pl011_usart_rxdma_config (vsf_pl011_usart_t *pl011_usart_ptr, bool enable)
uintptr_t	vsf_pl011_usart_txdma_config (vsf_pl011_usart_t *pl011_usart_ptr, bool enable)
void	vsf_pl011_usart_irqhandler (vsf_pl011_usart_t *pl011_usart_ptr)

Macro Definition Documentation

VSF_PL011_USART_CFG_MULTI_CLASS

#define VSF_PL011_USART_CFG_MULTI_CLASS   VSF_USART_CFG_MULTI_CLASS

VSF_USART_CFG_REIMPLEMENT_TYPE_MODE

#define VSF_USART_CFG_REIMPLEMENT_TYPE_MODE   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK

#define VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS

#define VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS   ENABLED

VSF_USART_7_BIT_LENGTH

#define VSF_USART_7_BIT_LENGTH   VSF_USART_7_BIT_LENGTH

VSF_USART_6_BIT_LENGTH

#define VSF_USART_6_BIT_LENGTH   VSF_USART_6_BIT_LENGTH

VSF_USART_5_BIT_LENGTH

#define VSF_USART_5_BIT_LENGTH   VSF_USART_5_BIT_LENGTH

VSF_USART_2_STOPBIT

#define VSF_USART_2_STOPBIT   VSF_USART_2_STOPBIT

VSF_USART_FORCE_0_PARITY

#define VSF_USART_FORCE_0_PARITY   VSF_USART_FORCE_0_PARITY

VSF_USART_FORCE_1_PARITY

#define VSF_USART_FORCE_1_PARITY   VSF_USART_FORCE_1_PARITY

VSF_USART_TX_DISABLE

#define VSF_USART_TX_DISABLE   VSF_USART_TX_DISABLE

VSF_USART_RX_DISABLE

#define VSF_USART_RX_DISABLE   VSF_USART_RX_DISABLE

VSF_USART_RTS_HWCONTROL

#define VSF_USART_RTS_HWCONTROL   VSF_USART_RTS_HWCONTROL

VSF_USART_CTS_HWCONTROL

#define VSF_USART_CTS_HWCONTROL   VSF_USART_CTS_HWCONTROL

VSF_USART_RTS_CTS_HWCONTROL

#define VSF_USART_RTS_CTS_HWCONTROL   VSF_USART_RTS_CTS_HWCONTROL

VSF_USART_TX_FIFO_THRESHOLD_EMPTY

#define VSF_USART_TX_FIFO_THRESHOLD_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_EMPTY

VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY

#define VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY

VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL

#define VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL

VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY

#define VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY

VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL

#define VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL

VSF_USART_RX_FIFO_THRESHOLD_FULL

#define VSF_USART_RX_FIFO_THRESHOLD_FULL   VSF_USART_RX_FIFO_THRESHOLD_FULL

VSF_USART_TX_FIFO_THRESHOLD_MASK

#define VSF_USART_TX_FIFO_THRESHOLD_MASK   (0x3ul << 8)

VSF_USART_RX_FIFO_THRESHOLD_MASK

#define VSF_USART_RX_FIFO_THRESHOLD_MASK   (0x3ul << 10)

VSF_USART_IRQ_MASK_RX_TIMEOUT

#define VSF_USART_IRQ_MASK_RX_TIMEOUT   VSF_USART_IRQ_MASK_RX_TIMEOUT

VSF_USART_IRQ_MASK_FRAME_ERR

#define VSF_USART_IRQ_MASK_FRAME_ERR   VSF_USART_IRQ_MASK_FRAME_ERR

VSF_USART_IRQ_MASK_PARITY_ERR

#define VSF_USART_IRQ_MASK_PARITY_ERR   VSF_USART_IRQ_MASK_PARITY_ERR

VSF_USART_IRQ_MASK_BREAK_ERR

#define VSF_USART_IRQ_MASK_BREAK_ERR   VSF_USART_IRQ_MASK_BREAK_ERR

VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR

#define VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR   VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR

VSF_USART_IRQ_MASK_CTS

#define VSF_USART_IRQ_MASK_CTS   VSF_USART_IRQ_MASK_CTS

VSF_USART_IRQ_MASK_RX_IDLE

#define VSF_USART_IRQ_MASK_RX_IDLE   VSF_USART_IRQ_MASK_RX_IDLE

Typedef Documentation

vsf_usart_mode_t

typedef enum vsf_usart_mode_t vsf_usart_mode_t

vsf_usart_irq_mask_t

typedef enum vsf_usart_irq_mask_t vsf_usart_irq_mask_t

vsf_usart_status_t

typedef struct vsf_usart_status_t vsf_usart_status_t

Enumeration Type Documentation

vsf_usart_mode_t

enum vsf_usart_mode_t

Enumerator
VSF_USART_8_BIT_LENGTH
VSF_USART_7_BIT_LENGTH
VSF_USART_7_BIT_LENGTH
VSF_USART_6_BIT_LENGTH
VSF_USART_6_BIT_LENGTH
VSF_USART_5_BIT_LENGTH
VSF_USART_5_BIT_LENGTH
VSF_USART_1_STOPBIT
VSF_USART_2_STOPBIT
VSF_USART_2_STOPBIT
VSF_USART_NO_PARITY
VSF_USART_ODD_PARITY
VSF_USART_EVEN_PARITY
VSF_USART_FORCE_0_PARITY
VSF_USART_FORCE_0_PARITY
VSF_USART_FORCE_1_PARITY
VSF_USART_FORCE_1_PARITY
PL011_USART_BIT_LENGTH_MASK
PL011_USART_STOPBIT_MASK
PL011_USART_PARITY_MASK
PL011_USART_MODE_MASK
VSF_USART_TX_ENABLE
VSF_USART_TX_DISABLE
VSF_USART_TX_DISABLE
VSF_USART_RX_ENABLE
VSF_USART_RX_DISABLE
VSF_USART_RX_DISABLE
VSF_USART_NO_HWCONTROL
VSF_USART_RTS_HWCONTROL
VSF_USART_RTS_HWCONTROL
VSF_USART_CTS_HWCONTROL
VSF_USART_CTS_HWCONTROL
VSF_USART_RTS_CTS_HWCONTROL
VSF_USART_RTS_CTS_HWCONTROL
PL011_USART_ENABLE_MASK
VSF_USART_9_BIT_LENGTH
VSF_USART_1_5_STOPBIT
VSF_USART_0_5_STOPBIT
VSF_USART_10_BIT_LENGTH
VSF_USART_SYNC_CLOCK_ENABLE
VSF_USART_SYNC_CLOCK_DISABLE
VSF_USART_HALF_DUPLEX_ENABLE
VSF_USART_HALF_DUPLEX_DISABLE
VSF_USART_TX_FIFO_THRESHOLD_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL
VSF_USART_RX_FIFO_THRESHOLD_FULL
VSF_USART_RX_FIFO_THRESHOLD_FULL

vsf_usart_irq_mask_t

enum vsf_usart_irq_mask_t

Enumerator
VSF_USART_IRQ_MASK_RX
VSF_USART_IRQ_MASK_TX
VSF_USART_IRQ_MASK_RX_TIMEOUT
VSF_USART_IRQ_MASK_RX_TIMEOUT
VSF_USART_IRQ_MASK_FRAME_ERR
VSF_USART_IRQ_MASK_FRAME_ERR
VSF_USART_IRQ_MASK_PARITY_ERR
VSF_USART_IRQ_MASK_PARITY_ERR
VSF_USART_IRQ_MASK_BREAK_ERR
VSF_USART_IRQ_MASK_BREAK_ERR
VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR
VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR
VSF_USART_IRQ_MASK_CTS
VSF_USART_IRQ_MASK_CTS
VSF_USART_IRQ_MASK_RX_IDLE
VSF_USART_IRQ_MASK_RX_IDLE
PL011_USART_IRQ_MASK_ERROR
PL011_USART_IRQ_MASK_FIFO
PL011_USART_IRQ_MASK
__VSF_USART_IRQ_FORCE_INT32

Function Documentation

vsf_pl011_usart_init()

vsf_err_t vsf_pl011_usart_init ( vsf_pl011_usart_t *  pl011_usart_ptr, vsf_usart_cfg_t *  cfg_ptr, uint_fast32_t  clk_hz  )

extern

vsf_pl011_usart_fini()

void vsf_pl011_usart_fini ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern

vsf_pl011_usart_capability()

vsf_usart_capability_t vsf_pl011_usart_capability ( vsf_pl011_usart_t *  pl011_usart_ptr, uint_fast32_t  clk_hz  )

extern

vsf_pl011_usart_enable()

fsm_rt_t vsf_pl011_usart_enable ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern

vsf_pl011_usart_disable()

fsm_rt_t vsf_pl011_usart_disable ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern

vsf_pl011_usart_irq_enable()

vsf_usart_irq_mask_t vsf_pl011_usart_irq_enable ( vsf_pl011_usart_t *  pl011_usart_ptr, vsf_usart_irq_mask_t  irq_mask  )

extern

vsf_pl011_usart_irq_disable()

vsf_usart_irq_mask_t vsf_pl011_usart_irq_disable ( vsf_pl011_usart_t *  pl011_usart_ptr, vsf_usart_irq_mask_t  irq_mask  )

extern

vsf_pl011_usart_status()

vsf_usart_status_t vsf_pl011_usart_status ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern

vsf_pl011_usart_rxfifo_get_data_count()

uint_fast16_t vsf_pl011_usart_rxfifo_get_data_count ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern

vsf_pl011_usart_rxfifo_read()

uint_fast16_t vsf_pl011_usart_rxfifo_read ( vsf_pl011_usart_t *  pl011_usart_ptr, void *  buffer_ptr, uint_fast16_t  count  )

extern

vsf_pl011_usart_txfifo_get_free_count()

uint_fast16_t vsf_pl011_usart_txfifo_get_free_count ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern

vsf_pl011_usart_txfifo_write()

uint_fast16_t vsf_pl011_usart_txfifo_write ( vsf_pl011_usart_t *  pl011_usart_ptr, void *  buffer_ptr, uint_fast16_t  count  )

extern

vsf_pl011_usart_rxdma_config()

uintptr_t vsf_pl011_usart_rxdma_config ( vsf_pl011_usart_t *  pl011_usart_ptr, bool  enable  )

extern

vsf_pl011_usart_txdma_config()

uintptr_t vsf_pl011_usart_txdma_config ( vsf_pl011_usart_t *  pl011_usart_ptr, bool  enable  )

extern

vsf_pl011_usart_irqhandler()

void vsf_pl011_usart_irqhandler ( vsf_pl011_usart_t *  pl011_usart_ptr )

extern