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#define | VSF_SDIO_CFG_MULTI_CLASS ENABLED |
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#define | VSF_SDIO_CFG_PREFIX vsf |
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#define | VSF_SDIO_CFG_FUNCTION_RENAME ENABLED |
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#define | VSF_SDIO_CFG_REIMPLEMENT_TYPE_MODE DISABLED |
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#define | VSF_SDIO_CFG_REIMPLEMENT_TYPE_IRQ_MASK DISABLED |
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#define | VSF_SDIO_CFG_REIMPLEMENT_TYPE_STATUS DISABLED |
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#define | VSF_SDIO_CFG_REIMPLEMENT_TYPE_CFG DISABLED |
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#define | VSF_SDIO_CFG_REIMPLEMENT_TYPE_CAPABILITY DISABLED |
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#define | VSF_SDIO_CFG_INHERT_HAL_CAPABILITY ENABLED |
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#define | SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ |
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#define | SD_SEND_RELATIVE_ADDR_OP (SDIO_RESP_R6) |
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#define | SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ |
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#define | SD_SEND_IF_COND_OP (SDIO_RESP_R7) |
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#define | SD_SWITCH_VOLTAGE 11 /* ac R1 */ |
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#define | SD_SWITCH_VOLTAGE_OP (SDIO_RESP_R1 | SDIO_CMDOP_CLKHOLD) |
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#define | SD_SWITCH 6 /* adtc [31:0] See below R1 */ |
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#define | SD_SWITCH_OP (SDIO_RESP_R1) |
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#define | SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */ |
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#define | SD_ERASE_WR_BLK_START_OP (SDIO_RESP_R1) |
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#define | SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */ |
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#define | SD_ERASE_WR_BLK_END_OP (SDIO_RESP_R1) |
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#define | SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ |
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#define | SD_APP_SET_BUS_WIDTH_OP (SDIO_RESP_R1) |
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#define | SD_BUS_WIDTH_1 0 |
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#define | SD_BUS_WIDTH_4 2 |
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#define | SD_BUS_WIDTH_8 3 |
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#define | SD_APP_SD_STATUS 13 /* adtc R1 */ |
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#define | SD_APP_SD_STATUS_OP (SDIO_RESP_R1) |
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#define | SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ |
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#define | SD_APP_SEND_NUM_WR_BLKS_OP (SDIO_RESP_R1) |
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#define | SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ |
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#define | SD_APP_OP_COND_OP (SDIO_RESP_R3) |
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#define | SD_APP_SEND_SCR 51 /* adtc R1 */ |
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#define | SD_APP_SEND_SCR_OP (SDIO_RESP_R1) |
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#define | SD_READ_EXTR_SINGLE 48 /* adtc [31:0] R1 */ |
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#define | SD_READ_EXTR_SINGLE_OP (SDIO_RESP_R1) |
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#define | SD_WRITE_EXTR_SINGLE 49 /* adtc [31:0] R1 */ |
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#define | SD_WRITE_EXTR_SINGLE_OP (SDIO_RESP_R1) |
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#define | SD_OCR_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
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#define | SD_OCR_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
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#define | SD_OCR_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ |
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#define | SD_OCR_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ |
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#define | SD_OCR_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ |
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#define | SD_OCR_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ |
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#define | SD_OCR_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ |
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#define | SD_OCR_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ |
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#define | SD_OCR_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ |
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#define | SD_OCR_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ |
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#define | SD_OCR_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ |
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#define | SD_OCR_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ |
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#define | SD_OCR_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ |
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#define | SD_OCR_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ |
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#define | SD_OCR_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ |
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#define | SD_OCR_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ |
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#define | SD_OCR_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ |
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#define | SD_OCR_VDD_HIGH 0x00FF8000 /* VDD voltage 2.7 ~ 3.6 */ |
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#define | SD_OCR_VDD_LOW 0x00007F80 /* VDD voltage 1.65 ~ 2.7 */ |
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#define | SD_OCR_VDD (SD_OCR_VDD_HIGH | SD_OCR_VDD_LOW) |
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#define | SD_OCR_S18R (1 << 24) /* 1.8V switching request */ |
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#define | SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ |
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#define | SD_OCR_XPC (1 << 28) /* SDXC power control */ |
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#define | SD_OCR_CCS (1 << 30) /* Card Capacity Status */ |
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#define | MMC_GO_IDLE_STATE 0 /* bc */ |
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#define | MMC_GO_IDLE_STATE_OP (SDIO_RESP_NONE) |
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#define | MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ |
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#define | MMC_SEND_OP_COND_OP (SDIO_RESP_R3) |
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#define | MMC_ALL_SEND_CID 2 /* bcr R2 */ |
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#define | MMC_ALL_SEND_CID_OP (SDIO_RESP_R2) |
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#define | MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ |
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#define | MMC_SET_RELATIVE_ADDR_OP (SDIO_RESP_R1) |
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#define | MMC_SET_DSR 4 /* bc [31:16] RCA */ |
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#define | MMC_SET_DSR_OP (SDIO_RESP_NONE) |
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#define | MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ |
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#define | MMC_SLEEP_AWAKE_OP (SDIO_RESP_R1B) |
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#define | MMC_SWITCH 6 /* ac [31:0] See below R1b */ |
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#define | MMC_SWITCH_OP (SDIO_RESP_R1B) |
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#define | MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ |
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#define | MMC_SELECT_CARD_OP (SDIO_RESP_R1) |
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#define | MMC_SEND_EXT_CSD 8 /* adtc R1 */ |
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#define | MMC_SEND_EXT_CSD_OP (SDIO_RESP_R1) |
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#define | MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ |
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#define | MMC_SEND_CSD_OP (SDIO_RESP_R2) |
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#define | MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ |
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#define | MMC_SEND_CID_OP (SDIO_RESP_R2) |
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#define | MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ |
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#define | MMC_READ_DAT_UNTIL_STOP_OP (SDIO_RESP_R1) |
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#define | MMC_STOP_TRANSMISSION 12 /* ac R1b */ |
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#define | MMC_STOP_TRANSMISSION_OP (SDIO_RESP_R1B | SDIO_CMDOP_TRANS_STOP) |
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#define | MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ |
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#define | MMC_SEND_STATUS_OP (SDIO_RESP_R1) |
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#define | MMC_BUS_TEST_R 14 /* adtc R1 */ |
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#define | MMC_BUS_TEST_R_OP (SDIO_RESP_R1) |
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#define | MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ |
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#define | MMC_BUS_TEST_W 19 /* adtc R1 */ |
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#define | MMC_BUS_TEST_W_OP (SDIO_RESP_R1) |
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#define | MMC_SPI_READ_OCR 58 /* spi spi_R3 */ |
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#define | MMC_SPI_READ_OCR_OP (SDIO_RESP_SPI_R3) |
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#define | MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ |
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#define | MMC_SPI_CRC_ON_OFF_OP (SDIO_RESP_SPI_R1) |
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#define | MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ |
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#define | MMC_SET_BLOCKLEN_OP (SDIO_RESP_R1) |
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#define | MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ |
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#define | MMC_READ_SINGLE_BLOCK_OP (SDIO_RESP_R1 | SDIO_CMDOP_SINGLE_BLOCK | SDIO_CMDOP_READ) |
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#define | MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ |
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#define | MMC_READ_MULTIPLE_BLOCK_OP (SDIO_RESP_R1 | SDIO_CMDOP_MULTI_BLOCK | SDIO_CMDOP_READ) |
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#define | MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ |
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#define | MMC_SEND_TUNING_BLOCK_OP (SDIO_RESP_R1) |
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#define | MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ |
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#define | MMC_SEND_TUNING_BLOCK_HS200_OP (SDIO_RESP_R1) |
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#define | MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ |
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#define | MMC_WRITE_DAT_UNTIL_STOP_OP (SDIO_RESP_R1) |
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#define | MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ |
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#define | MMC_SET_BLOCK_COUNT_OP (SDIO_RESP_R1) |
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#define | MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ |
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#define | MMC_WRITE_BLOCK_OP (SDIO_RESP_R1 | SDIO_CMDOP_SINGLE_BLOCK | SDIO_CMDOP_WRITE) |
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#define | MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ |
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#define | MMC_WRITE_MULTIPLE_BLOCK_OP (SDIO_RESP_R1 | SDIO_CMDOP_MULTI_BLOCK | SDIO_CMDOP_WRITE) |
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#define | MMC_PROGRAM_CID 26 /* adtc R1 */ |
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#define | MMC_PROGRAM_CID_OP (SDIO_RESP_R1) |
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#define | MMC_PROGRAM_CSD 27 /* adtc R1 */ |
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#define | MMC_PROGRAM_CSD_OP (SDIO_RESP_R1) |
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#define | MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ |
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#define | MMC_SET_WRITE_PROT_OP (SDIO_RESP_R1B) |
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#define | MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ |
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#define | MMC_CLR_WRITE_PROT_OP (SDIO_RESP_R1B) |
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#define | MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ |
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#define | MMC_SEND_WRITE_PROT_OP (SDIO_RESP_R1) |
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#define | MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ |
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#define | MMC_ERASE_GROUP_START_OP (SDIO_RESP_R1) |
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#define | MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ |
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#define | MMC_ERASE_GROUP_END_OP (SDIO_RESP_R1) |
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#define | MMC_ERASE 38 /* ac R1b */ |
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#define | MMC_ERASE_OP (SDIO_RESP_R1B) |
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#define | MMC_FAST_IO 39 /* ac <Complex> R4 */ |
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#define | MMC_FAST_IO_OP (SDIO_RESP_R4) |
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#define | MMC_GO_IRQ_STATE 40 /* bcr R5 */ |
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#define | MMC_GO_IRQ_STATE_OP (SDIO_RESP_R5) |
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#define | MMC_LOCK_UNLOCK 42 /* adtc R1b */ |
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#define | MMC_LOCK_UNLOCK_OP (SDIO_RESP_R1B) |
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#define | MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ |
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#define | MMC_APP_CMD_OP (SDIO_RESP_R1) |
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#define | MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ |
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#define | MMC_GEN_CMD_OP (SDIO_RESP_R1) |
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#define | MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */ |
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#define | MMC_QUE_TASK_PARAMS_OP (SDIO_RESP_R1) |
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#define | MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */ |
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#define | MMC_QUE_TASK_ADDR_OP (SDIO_RESP_R1) |
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#define | MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */ |
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#define | MMC_EXECUTE_READ_TASK_OP (SDIO_RESP_R1) |
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#define | MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */ |
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#define | MMC_EXECUTE_WRITE_TASK_OP (SDIO_RESP_R1) |
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#define | MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */ |
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#define | MMC_CMDQ_TASK_MGMT_OP (SDIO_RESP_R1B) |
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#define | SD_VERSION_SD (1U << 31) |
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#define | MMC_VERSION_MMC (1U << 30) |
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#define | MAKE_SDMMC_VERSION(a, b, c) ((((uint32_t)(a)) << 16) | ((uint32_t)(b) << 8) | (uint32_t)(c)) |
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#define | MAKE_SD_VERSION(a, b, c) (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) |
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#define | MAKE_MMC_VERSION(a, b, c) (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) |
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#define | EXTRACT_SDMMC_MAJOR_VERSION(x) (((uint32_t)(x) >> 16) & 0xff) |
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#define | EXTRACT_SDMMC_MINOR_VERSION(x) (((uint32_t)(x) >> 8) & 0xff) |
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#define | EXTRACT_SDMMC_CHANGE_VERSION(x) ((uint32_t)(x) & 0xff) |
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#define | SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) |
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#define | SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) |
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#define | SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) |
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#define | SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) |
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#define | MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) |
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#define | MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) |
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#define | MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) |
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#define | MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) |
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#define | MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) |
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#define | MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) |
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#define | MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) |
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#define | MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) |
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#define | MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) |
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#define | MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0) |
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#define | MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) |
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#define | MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) |
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#define | MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) |
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#define | MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) |
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#define | IS_SD(x) ((x) & SD_VERSION_SD) |
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#define | IS_MMC(x) ((x) & MMC_VERSION_MMC) |
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#define | R1_OUT_OF_RANGE (1 << 31) /* er, c */ |
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#define | R1_ADDRESS_ERROR (1 << 30) /* erx, c */ |
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#define | R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ |
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#define | R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ |
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#define | R1_ERASE_PARAM (1 << 27) /* ex, c */ |
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#define | R1_WP_VIOLATION (1 << 26) /* erx, c */ |
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#define | R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ |
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#define | R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ |
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#define | R1_COM_CRC_ERROR (1 << 23) /* er, b */ |
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#define | R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ |
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#define | R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ |
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#define | R1_CC_ERROR (1 << 20) /* erx, c */ |
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#define | R1_ERROR (1 << 19) /* erx, c */ |
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#define | R1_UNDERRUN (1 << 18) /* ex, c */ |
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#define | R1_OVERRUN (1 << 17) /* ex, c */ |
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#define | R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ |
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#define | R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ |
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#define | R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ |
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#define | R1_ERASE_RESET (1 << 13) /* sr, c */ |
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#define | R1_STATUS(x) (x & 0xFFF9A000) |
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#define | R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ |
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#define | R1_READY_FOR_DATA (1 << 8) /* sx, a */ |
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#define | R1_SWITCH_ERROR (1 << 7) /* sx, c */ |
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#define | R1_EXCEPTION_EVENT (1 << 6) /* sr, a */ |
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#define | R1_APP_CMD (1 << 5) /* sr, c */ |
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#define | R1_STATE_IDLE 0 |
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#define | R1_STATE_READY 1 |
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#define | R1_STATE_IDENT 2 |
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#define | R1_STATE_STBY 3 |
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#define | R1_STATE_TRAN 4 |
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#define | R1_STATE_DATA 5 |
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#define | R1_STATE_RCV 6 |
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#define | R1_STATE_PRG 7 |
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#define | R1_STATE_DIS 8 |
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#define | R1_STATE_MASK 0x0FUL |
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#define | R1_CUR_STATE(__S) ((__S) << 9) |
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#define | VSF_SDIO_APIS(__prefix) |
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#define | SDIO_RESP_NONE 0 |
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#define | SDIO_RESP_R1 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT_CRC) |
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#define | SDIO_RESP_R1B (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT_CRC | SDIO_CMDOP_RESP_BUSY) |
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#define | SDIO_RESP_R2 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_LONG_CRC) |
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#define | SDIO_RESP_R3 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT) |
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#define | SDIO_RESP_R4 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT) |
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#define | SDIO_RESP_R5 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT_CRC) |
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#define | SDIO_RESP_R6 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT_CRC) |
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#define | SDIO_RESP_R7 (__SDIO_CMDOP_RESP | __SDIO_CMDOP_RESP_SHORT_CRC) |
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#define | __VSF_HAL_TEMPLATE_API VSF_HAL_TEMPLATE_API_FP |
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#define | __vsf_sdio_t VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_t) |
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#define | vsf_sdio_init(__SDIO, ...) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_init) ((__vsf_sdio_t *)(__SDIO), ##__VA_ARGS__) |
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#define | vsf_sdio_enable(__SDIO) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_enable) ((__vsf_sdio_t *)(__SDIO)) |
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#define | vsf_sdio_disable(__SDIO) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_disable) ((__vsf_sdio_t *)(__SDIO)) |
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#define | vsf_sdio_irq_enable(__SDIO, ...) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_irq_enable) ((__vsf_sdio_t *)(__SDIO), ##__VA_ARGS__) |
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#define | vsf_sdio_irq_disable(__SDIO, ...) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_irq_disable) ((__vsf_sdio_t *)(__SDIO), ##__VA_ARGS__) |
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#define | vsf_sdio_status(__SDIO) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_status) ((__vsf_sdio_t *)(__SDIO)) |
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#define | vsf_sdio_capability(__SDIO) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_capability) ((__vsf_sdio_t *)(__SDIO)) |
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#define | vsf_sdio_set_clock(__SDIO, ...) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_set_clock) ((__vsf_sdio_t *)(__SDIO), ##__VA_ARGS__) |
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#define | vsf_sdio_set_bus_width(__SDIO, ...) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_set_bus_width) ((__vsf_sdio_t *)(__SDIO), ##__VA_ARGS__) |
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#define | vsf_sdio_host_request(__SDIO, ...) VSF_MCONNECT(VSF_SDIO_CFG_PREFIX, _sdio_host_request) ((__vsf_sdio_t *)(__SDIO), ##__VA_ARGS__) |
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