usart.h File Reference

#include "hal/vsf_hal_cfg.h"

Go to the source code of this file.

Data Structures
struct	vsf_usart_status_t
	USART status information structure Contains the current status of USART operations and FIFO thresholds. More...
struct	vsf_usart_isr_t
	USART interrupt configuration structure Contains all necessary information for configuring USART interrupts. More...
struct	vsf_usart_cfg_t
	USART configuration structure Contains all parameters needed to initialize and configure a USART instance. More...
struct	vsf_usart_capability_t
	USART capability structure Defines the hardware capabilities and limitations of the USART interface. More...

Macros
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_MODE   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_CTRL   ENABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_CFG   DISABLED
#define	VSF_USART_CFG_REIMPLEMENT_TYPE_CAPABILITY   DISABLED
#define	VSF_USART_TX_DISABLE   VSF_USART_TX_DISABLE
#define	VSF_USART_RX_DISABLE   VSF_USART_RX_DISABLE
#define	VSF_USART_9_BIT_LENGTH   VSF_USART_9_BIT_LENGTH
#define	VSF_USART_0_5_STOPBIT   VSF_USART_0_5_STOPBIT
#define	VSF_USART_1_5_STOPBIT   VSF_USART_1_5_STOPBIT
#define	VSF_USART_2_STOPBIT   VSF_USART_2_STOPBIT
#define	VSF_USART_SYNC_CLOCK_ENABLE   VSF_USART_SYNC_CLOCK_ENABLE
#define	VSF_USART_SYNC_CLOCK_DISABLE   VSF_USART_SYNC_CLOCK_DISABLE
#define	VSF_USART_SYNC_CLOCK_POLARITY_LOW   VSF_USART_SYNC_CLOCK_POLARITY_LOW
#define	VSF_USART_SYNC_CLOCK_POLARITY_HIGH   VSF_USART_SYNC_CLOCK_POLARITY_HIGH
#define	VSF_USART_SYNC_CLOCK_PHASE_1_EDGE   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE
#define	VSF_USART_SYNC_CLOCK_PHASE_2_EDGE   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE
#define	VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE
#define	VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
#define	VSF_USART_SYNC_CLOCK_LAST_BIT_MASK   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE | VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
#define	VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
#define	VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY
#define	VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH   VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH
#define	VSF_USART_TX_FIFO_THRESHOLD_QUARTER   VSF_USART_TX_FIFO_THRESHOLD_QUARTER
#define	VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH   VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH
#define	VSF_USART_TX_FIFO_THRESHOLD_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_EMPTY
#define	VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
#define	VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL
#define	VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH   VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH
#define	VSF_USART_RX_FIFO_THRESHOLD_QUARTER   VSF_USART_RX_FIFO_THRESHOLD_QUARTER
#define	VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH   VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH
#define	VSF_USART_RX_FIFO_THRESHOLD_FULL   VSF_USART_RX_FIFO_THRESHOLD_FULL
#define	VSF_USART_TX_FIFO_THRESHOLD_MASK
#define	VSF_USART_RX_FIFO_THRESHOLD_MASK
#define	VSF_USART_RTS_HWCONTROL   VSF_USART_RTS_HWCONTROL
#define	VSF_USART_CTS_HWCONTROL   VSF_USART_CTS_HWCONTROL
#define	VSF_USART_RTS_CTS_HWCONTROL   VSF_USART_RTS_CTS_HWCONTROL
#define	VSF_USART_HALF_DUPLEX_ENABLE   VSF_USART_HALF_DUPLEX_ENABLE
#define	VSF_USART_SWAP   VSF_USART_SWAP
#define	VSF_USART_IRQ_MASK_CTS   VSF_USART_IRQ_MASK_CTS
#define	VSF_USART_IRQ_MASK_RX_IDLE   VSF_USART_IRQ_MASK_RX_IDLE
#define	VSF_USART_IRQ_MASK_TX_IDLE   VSF_USART_IRQ_MASK_TX_IDLE
#define	VSF_USART_IRQ_MASK_RX_TIMEOUT   VSF_USART_IRQ_MASK_RX_TIMEOUT
#define	VSF_USART_IRQ_MASK_NOISE_ERR   VSF_USART_IRQ_MASK_NOISE_ERR
#define	VSF_USART_IRQ_MASK_BREAK_ERR   VSF_USART_IRQ_MASK_BREAK_ERR
#define	VSF_USART_CTRL_SEND_BREAK   VSF_USART_CTRL_SEND_BREAK
#define	__VSF_HW_USART_STS_XOR_MASK   (1 << 8)
#define	__VSF_HW_USART_STS_MASK   0xF7FF
#define	VSF_USART_STATUS_BREAK_SENT   11

Typedefs
typedef enum vsf_usart_mode_t	vsf_usart_mode_t
typedef enum vsf_usart_irq_mask_t	vsf_usart_irq_mask_t
typedef enum vsf_usart_ctrl_t	vsf_usart_ctrl_t
typedef struct vsf_usart_status_t	vsf_usart_status_t
typedef struct vsf_usart_t	vsf_usart_t
typedef void	vsf_usart_isr_handler_t(void *target_ptr, vsf_usart_t *usart_ptr, vsf_usart_irq_mask_t irq_mask)
typedef struct vsf_usart_isr_t	vsf_usart_isr_t
typedef struct vsf_usart_cfg_t	vsf_usart_cfg_t
typedef struct vsf_usart_capability_t	vsf_usart_capability_t

Enumerations
enum	vsf_usart_mode_t {   VSF_USART_TX_ENABLE = (1 << 2) ,   VSF_USART_TX_DISABLE = (0 << 2) ,   VSF_USART_TX_DISABLE = (0 << 2) ,   VSF_USART_RX_ENABLE = (1 << 1) ,   VSF_USART_RX_DISABLE = (0 << 1) ,   VSF_USART_RX_DISABLE = (0 << 1) ,   VSF_USART_NO_PARITY = (0 << 4) ,   VSF_USART_ODD_PARITY = (1 << 4) | (1 << 3) ,   VSF_USART_EVEN_PARITY = (1 << 4) ,   VSF_USART_8_BIT_LENGTH = (0 << 5) ,   VSF_USART_9_BIT_LENGTH = (1 << 5) ,   VSF_USART_9_BIT_LENGTH = (1 << 5) ,   VSF_USART_1_STOPBIT = (0 << 5) << 1 ,   VSF_USART_0_5_STOPBIT = (1 << 5) << 1 ,   VSF_USART_0_5_STOPBIT = (1 << 5) << 1 ,   VSF_USART_1_5_STOPBIT = (3 << 5) << 1 ,   VSF_USART_1_5_STOPBIT = (3 << 5) << 1 ,   VSF_USART_2_STOPBIT = (2 << 5) << 1 ,   VSF_USART_2_STOPBIT = (2 << 5) << 1 ,   VSF_USART_SYNC_CLOCK_ENABLE = (8 << 11) ,   VSF_USART_SYNC_CLOCK_ENABLE = (8 << 11) ,   VSF_USART_SYNC_CLOCK_DISABLE = (8 << 11) ,   VSF_USART_SYNC_CLOCK_DISABLE = (8 << 11) ,   VSF_USART_SYNC_CLOCK_POLARITY_LOW = (0 << 9) ,   VSF_USART_SYNC_CLOCK_POLARITY_LOW = (0 << 9) ,   VSF_USART_SYNC_CLOCK_POLARITY_HIGH = (1 << 9) ,   VSF_USART_SYNC_CLOCK_POLARITY_HIGH = (1 << 9) ,   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE = (0 << 10) ,   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE = (0 << 10) ,   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE = (1 << 10) ,   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE = (1 << 10) ,   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE = (1 << 11) ,   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE = (0 << 11) ,   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE = (1 << 11) ,   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE = (0 << 11) ,   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = ((7 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = ((7 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = ((2 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = ((2 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH = ((0 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH = ((0 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_QUARTER = ((1 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_QUARTER = ((1 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH = ((1 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH = ((1 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_EMPTY = ((5 << 2) | (1 << 0)) << 12 ,   VSF_USART_TX_FIFO_THRESHOLD_EMPTY = ((5 << 2) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = ((7 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = ((7 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = ((2 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = ((2 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH = ((0 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH = ((0 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_QUARTER = ((1 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_QUARTER = ((1 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH = ((1 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH = ((1 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_FULL = ((5 << 5) | (1 << 0)) << 12 ,   VSF_USART_RX_FIFO_THRESHOLD_FULL = ((5 << 5) | (1 << 0)) << 12 ,   VSF_USART_NO_HWCONTROL = (0) << 16 ,   VSF_USART_RTS_HWCONTROL = (1 << 2) << 20 ,   VSF_USART_RTS_HWCONTROL = (1 << 2) << 20 ,   VSF_USART_CTS_HWCONTROL = (1 << 0) << 20 ,   VSF_USART_CTS_HWCONTROL = (1 << 0) << 20 ,   VSF_USART_RTS_CTS_HWCONTROL ,   VSF_USART_RTS_CTS_HWCONTROL ,   VSF_USART_HALF_DUPLEX_ENABLE = (1 << 4) << 20 ,   VSF_USART_HALF_DUPLEX_ENABLE = (1 << 4) << 20 ,   VSF_USART_HALF_DUPLEX_DISABLE = 0 ,   VSF_USART_OVERSAMPLE_8 = (1 << 26) ,   VSF_USART_OVERSAMPLE_16 = (0 << 26) ,   VSF_USART_OVERSAMPLE_MASK = (1 << 26) ,   VSF_USART_SWAP = (1 << 27) ,   VSF_USART_SWAP = (1 << 27) ,   __VSF_HW_USART_CTRL1_MASK ,   __VSF_HW_USART_CTRL2_MASK ,   __VSF_HW_USART_CTRL2_SHIFT_MASK ,   __VSF_HW_USART_CTRL2_SHIFT_BITS = 1 ,   __VSF_HW_USART_CTRL3_MASK ,   __VSF_HW_USART_CTRL3_SHIFT_MASK = __VSF_HW_USART_CTRL3_MASK ,   __VSF_HW_USART_CTRL3_SHIFT_BITS = 20 ,   __VSF_HW_USART_FIFO_MASK ,   __VSF_HW_USART_FIFO_SHIFT_MASK = __VSF_HW_USART_FIFO_MASK ,   __VSF_HW_USART_FIFO_SHIFT_BITS = 12 ,   VSF_USART_10_BIT_LENGTH = (1 << 28) ,   VSF_USART_7_BIT_LENGTH = (2 << 28) ,   VSF_USART_6_BIT_LENGTH = (3 << 28) ,   VSF_USART_5_BIT_LENGTH = (4 << 28) ,   VSF_USART_FORCE_0_PARITY = (0 << 31) ,   VSF_USART_FORCE_1_PARITY = (1 << 31) ,   __VSF_HW_USART_NOT_SUPPORT_MASK }
enum	vsf_usart_irq_mask_t {   VSF_USART_IRQ_MASK_CTS = (1 << 3) ,   VSF_USART_IRQ_MASK_CTS = (1 << 3) ,   VSF_USART_IRQ_MASK_RX_CPL = (0) ,   VSF_USART_IRQ_MASK_TX_CPL = (0) ,   VSF_USART_IRQ_MASK_TX = (1 << 7) ,   VSF_USART_IRQ_MASK_RX_IDLE = (1 << 8) ,   VSF_USART_IRQ_MASK_RX_IDLE = (1 << 8) ,   VSF_USART_IRQ_MASK_RX = (1 << 9) ,   VSF_USART_IRQ_MASK_TX_IDLE = (1 << 11) ,   VSF_USART_IRQ_MASK_TX_IDLE = (1 << 11) ,   VSF_USART_IRQ_MASK_PARITY_ERR = (1 << 12) ,   VSF_USART_IRQ_MASK_RX_TIMEOUT = (1 << 15) | (1 << 17) ,   VSF_USART_IRQ_MASK_RX_TIMEOUT = (1 << 15) | (1 << 17) ,   VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR = (1 << 18) ,   VSF_USART_IRQ_MASK_NOISE_ERR = (1 << 19) ,   VSF_USART_IRQ_MASK_NOISE_ERR = (1 << 19) ,   VSF_USART_IRQ_MASK_FRAME_ERR = (1 << 20) ,   VSF_USART_IRQ_MASK_BREAK_ERR = VSF_USART_IRQ_MASK_FRAME_ERR ,   VSF_USART_IRQ_MASK_BREAK_ERR = VSF_USART_IRQ_MASK_FRAME_ERR ,   __VSF_HW_USART_IRQ_MASK ,   __VSF_HW_USART_CTRL1_IRQ_MASK ,   __VSF_HW_USART_CTRL2_IRQ_MASK = VSF_USART_IRQ_MASK_RX_TIMEOUT ,   __VSF_HW_USART_CTRL3_IRQ_MASK = VSF_USART_IRQ_MASK_CTS ,   __VSF_HW_USART_STS_IRQ_MASK }
enum	vsf_usart_ctrl_t {   VSF_USART_CTRL_SEND_BREAK = (1 << 13) ,   VSF_USART_CTRL_SEND_BREAK = (1 << 13) ,   __VSF_HW_USART_SUPPORT_CMD_MASK = VSF_USART_CTRL_SEND_BREAK ,   VSF_USART_CTRL_SET_BREAK = (1 << 8) ,   VSF_USART_CTRL_CLEAR_BREAK = (1 << 9) }

Macro Definition Documentation

VSF_USART_CFG_REIMPLEMENT_TYPE_MODE

#define VSF_USART_CFG_REIMPLEMENT_TYPE_MODE   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS

#define VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK

#define VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_CTRL

#define VSF_USART_CFG_REIMPLEMENT_TYPE_CTRL   ENABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_CFG

#define VSF_USART_CFG_REIMPLEMENT_TYPE_CFG   DISABLED

VSF_USART_CFG_REIMPLEMENT_TYPE_CAPABILITY

#define VSF_USART_CFG_REIMPLEMENT_TYPE_CAPABILITY   DISABLED

VSF_USART_TX_DISABLE

#define VSF_USART_TX_DISABLE   VSF_USART_TX_DISABLE

VSF_USART_RX_DISABLE

#define VSF_USART_RX_DISABLE   VSF_USART_RX_DISABLE

VSF_USART_9_BIT_LENGTH

#define VSF_USART_9_BIT_LENGTH   VSF_USART_9_BIT_LENGTH

VSF_USART_0_5_STOPBIT

#define VSF_USART_0_5_STOPBIT   VSF_USART_0_5_STOPBIT

VSF_USART_1_5_STOPBIT

#define VSF_USART_1_5_STOPBIT   VSF_USART_1_5_STOPBIT

VSF_USART_2_STOPBIT

#define VSF_USART_2_STOPBIT   VSF_USART_2_STOPBIT

VSF_USART_SYNC_CLOCK_ENABLE

#define VSF_USART_SYNC_CLOCK_ENABLE   VSF_USART_SYNC_CLOCK_ENABLE

VSF_USART_SYNC_CLOCK_DISABLE

#define VSF_USART_SYNC_CLOCK_DISABLE   VSF_USART_SYNC_CLOCK_DISABLE

VSF_USART_SYNC_CLOCK_POLARITY_LOW

#define VSF_USART_SYNC_CLOCK_POLARITY_LOW   VSF_USART_SYNC_CLOCK_POLARITY_LOW

VSF_USART_SYNC_CLOCK_POLARITY_HIGH

#define VSF_USART_SYNC_CLOCK_POLARITY_HIGH   VSF_USART_SYNC_CLOCK_POLARITY_HIGH

VSF_USART_SYNC_CLOCK_PHASE_1_EDGE

#define VSF_USART_SYNC_CLOCK_PHASE_1_EDGE   VSF_USART_SYNC_CLOCK_PHASE_1_EDGE

VSF_USART_SYNC_CLOCK_PHASE_2_EDGE

#define VSF_USART_SYNC_CLOCK_PHASE_2_EDGE   VSF_USART_SYNC_CLOCK_PHASE_2_EDGE

VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE

#define VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE

VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE

#define VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE   VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE

VSF_USART_SYNC_CLOCK_LAST_BIT_MASK

#define VSF_USART_SYNC_CLOCK_LAST_BIT_MASK   VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE | VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE

VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL

#define VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL   VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL

VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY

#define VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY

VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH

#define VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH   VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH

VSF_USART_TX_FIFO_THRESHOLD_QUARTER

#define VSF_USART_TX_FIFO_THRESHOLD_QUARTER   VSF_USART_TX_FIFO_THRESHOLD_QUARTER

VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH

#define VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH   VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH

VSF_USART_TX_FIFO_THRESHOLD_EMPTY

#define VSF_USART_TX_FIFO_THRESHOLD_EMPTY   VSF_USART_TX_FIFO_THRESHOLD_EMPTY

VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY

#define VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY   VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY

VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL

#define VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL   VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL

VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH

#define VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH   VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH

VSF_USART_RX_FIFO_THRESHOLD_QUARTER

#define VSF_USART_RX_FIFO_THRESHOLD_QUARTER   VSF_USART_RX_FIFO_THRESHOLD_QUARTER

VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH

#define VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH   VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH

VSF_USART_RX_FIFO_THRESHOLD_FULL

#define VSF_USART_RX_FIFO_THRESHOLD_FULL   VSF_USART_RX_FIFO_THRESHOLD_FULL

VSF_USART_TX_FIFO_THRESHOLD_MASK

#define VSF_USART_TX_FIFO_THRESHOLD_MASK

Value:

                                            ( VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL\
                                            | VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY\
                                            | VSF_USART_TX_FIFO_THRESHOLD_EMPTY\
                                            | VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH\
                                            | VSF_USART_TX_FIFO_THRESHOLD_QUARTER\
                                            | VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH)

VSF_USART_RX_FIFO_THRESHOLD_MASK

#define VSF_USART_RX_FIFO_THRESHOLD_MASK

Value:

                                            ( VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY\
                                            | VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL\
                                            | VSF_USART_RX_FIFO_THRESHOLD_FULL\
                                            | VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH\
                                            | VSF_USART_RX_FIFO_THRESHOLD_QUARTER\
                                            | VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH )

VSF_USART_RTS_HWCONTROL

#define VSF_USART_RTS_HWCONTROL   VSF_USART_RTS_HWCONTROL

VSF_USART_CTS_HWCONTROL

#define VSF_USART_CTS_HWCONTROL   VSF_USART_CTS_HWCONTROL

VSF_USART_RTS_CTS_HWCONTROL

#define VSF_USART_RTS_CTS_HWCONTROL   VSF_USART_RTS_CTS_HWCONTROL

VSF_USART_HALF_DUPLEX_ENABLE

#define VSF_USART_HALF_DUPLEX_ENABLE   VSF_USART_HALF_DUPLEX_ENABLE

VSF_USART_SWAP

#define VSF_USART_SWAP   VSF_USART_SWAP

VSF_USART_IRQ_MASK_CTS

#define VSF_USART_IRQ_MASK_CTS   VSF_USART_IRQ_MASK_CTS

VSF_USART_IRQ_MASK_RX_IDLE

#define VSF_USART_IRQ_MASK_RX_IDLE   VSF_USART_IRQ_MASK_RX_IDLE

VSF_USART_IRQ_MASK_TX_IDLE

#define VSF_USART_IRQ_MASK_TX_IDLE   VSF_USART_IRQ_MASK_TX_IDLE

VSF_USART_IRQ_MASK_RX_TIMEOUT

#define VSF_USART_IRQ_MASK_RX_TIMEOUT   VSF_USART_IRQ_MASK_RX_TIMEOUT

VSF_USART_IRQ_MASK_NOISE_ERR

#define VSF_USART_IRQ_MASK_NOISE_ERR   VSF_USART_IRQ_MASK_NOISE_ERR

VSF_USART_IRQ_MASK_BREAK_ERR

#define VSF_USART_IRQ_MASK_BREAK_ERR   VSF_USART_IRQ_MASK_BREAK_ERR

VSF_USART_CTRL_SEND_BREAK

#define VSF_USART_CTRL_SEND_BREAK   VSF_USART_CTRL_SEND_BREAK

__VSF_HW_USART_STS_XOR_MASK

#define __VSF_HW_USART_STS_XOR_MASK   (1 << 8)

__VSF_HW_USART_STS_MASK

#define __VSF_HW_USART_STS_MASK   0xF7FF

VSF_USART_STATUS_BREAK_SENT

#define VSF_USART_STATUS_BREAK_SENT   11

Typedef Documentation

vsf_usart_mode_t

typedef enum vsf_usart_mode_t vsf_usart_mode_t

vsf_usart_irq_mask_t

typedef enum vsf_usart_irq_mask_t vsf_usart_irq_mask_t

vsf_usart_ctrl_t

typedef enum vsf_usart_ctrl_t vsf_usart_ctrl_t

vsf_usart_status_t

typedef struct vsf_usart_status_t vsf_usart_status_t

Note

It's not obligated to inherit from vsf_peripheral_status_t. If not, there MUST be a is_busy bit in vsf_usart_status_t.

vsf_usart_t

typedef struct vsf_usart_t vsf_usart_t

Note

Redefining vsf_usart_cfg_t usually requires declaring vsf_usart_t and vsf_usart_isr_handler_t types and define vsf_usart_isr_t.

vsf_usart_isr_handler_t

typedef void vsf_usart_isr_handler_t(void *target_ptr, vsf_usart_t *usart_ptr, vsf_usart_irq_mask_t irq_mask)

vsf_usart_isr_t

typedef struct vsf_usart_isr_t vsf_usart_isr_t

vsf_usart_cfg_t

typedef struct vsf_usart_cfg_t vsf_usart_cfg_t

vsf_usart_capability_t

typedef struct vsf_usart_capability_t vsf_usart_capability_t

Enumeration Type Documentation

vsf_usart_mode_t

enum vsf_usart_mode_t

Enumerator
VSF_USART_TX_ENABLE
VSF_USART_TX_DISABLE
VSF_USART_TX_DISABLE
VSF_USART_RX_ENABLE
VSF_USART_RX_DISABLE
VSF_USART_RX_DISABLE
VSF_USART_NO_PARITY
VSF_USART_ODD_PARITY
VSF_USART_EVEN_PARITY
VSF_USART_8_BIT_LENGTH
VSF_USART_9_BIT_LENGTH
VSF_USART_9_BIT_LENGTH
VSF_USART_1_STOPBIT
VSF_USART_0_5_STOPBIT
VSF_USART_0_5_STOPBIT
VSF_USART_1_5_STOPBIT
VSF_USART_1_5_STOPBIT
VSF_USART_2_STOPBIT
VSF_USART_2_STOPBIT
VSF_USART_SYNC_CLOCK_ENABLE
VSF_USART_SYNC_CLOCK_ENABLE
VSF_USART_SYNC_CLOCK_DISABLE
VSF_USART_SYNC_CLOCK_DISABLE
VSF_USART_SYNC_CLOCK_POLARITY_LOW
VSF_USART_SYNC_CLOCK_POLARITY_LOW
VSF_USART_SYNC_CLOCK_POLARITY_HIGH
VSF_USART_SYNC_CLOCK_POLARITY_HIGH
VSF_USART_SYNC_CLOCK_PHASE_1_EDGE
VSF_USART_SYNC_CLOCK_PHASE_1_EDGE
VSF_USART_SYNC_CLOCK_PHASE_2_EDGE
VSF_USART_SYNC_CLOCK_PHASE_2_EDGE
VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE
VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
VSF_USART_SYNC_CLOCK_LAST_BIT_ENABLE
VSF_USART_SYNC_CLOCK_LAST_BIT_DISABLE
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH
VSF_USART_TX_FIFO_THRESHOLD_ONE_EIGHTH
VSF_USART_TX_FIFO_THRESHOLD_QUARTER
VSF_USART_TX_FIFO_THRESHOLD_QUARTER
VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH
VSF_USART_TX_FIFO_THRESHOLD_THREE_FOURTH
VSF_USART_TX_FIFO_THRESHOLD_EMPTY
VSF_USART_TX_FIFO_THRESHOLD_EMPTY
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL
VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH
VSF_USART_RX_FIFO_THRESHOLD_ONE_EIGHTH
VSF_USART_RX_FIFO_THRESHOLD_QUARTER
VSF_USART_RX_FIFO_THRESHOLD_QUARTER
VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH
VSF_USART_RX_FIFO_THRESHOLD_THREE_FOURTH
VSF_USART_RX_FIFO_THRESHOLD_FULL
VSF_USART_RX_FIFO_THRESHOLD_FULL
VSF_USART_NO_HWCONTROL
VSF_USART_RTS_HWCONTROL
VSF_USART_RTS_HWCONTROL
VSF_USART_CTS_HWCONTROL
VSF_USART_CTS_HWCONTROL
VSF_USART_RTS_CTS_HWCONTROL
VSF_USART_RTS_CTS_HWCONTROL
VSF_USART_HALF_DUPLEX_ENABLE
VSF_USART_HALF_DUPLEX_ENABLE
VSF_USART_HALF_DUPLEX_DISABLE
VSF_USART_OVERSAMPLE_8
VSF_USART_OVERSAMPLE_16
VSF_USART_OVERSAMPLE_MASK
VSF_USART_SWAP
VSF_USART_SWAP
__VSF_HW_USART_CTRL1_MASK
__VSF_HW_USART_CTRL2_MASK
__VSF_HW_USART_CTRL2_SHIFT_MASK
__VSF_HW_USART_CTRL2_SHIFT_BITS
__VSF_HW_USART_CTRL3_MASK
__VSF_HW_USART_CTRL3_SHIFT_MASK
__VSF_HW_USART_CTRL3_SHIFT_BITS
__VSF_HW_USART_FIFO_MASK
__VSF_HW_USART_FIFO_SHIFT_MASK
__VSF_HW_USART_FIFO_SHIFT_BITS
VSF_USART_10_BIT_LENGTH
VSF_USART_7_BIT_LENGTH
VSF_USART_6_BIT_LENGTH
VSF_USART_5_BIT_LENGTH
VSF_USART_FORCE_0_PARITY
VSF_USART_FORCE_1_PARITY
__VSF_HW_USART_NOT_SUPPORT_MASK

vsf_usart_irq_mask_t

enum vsf_usart_irq_mask_t

Enumerator
VSF_USART_IRQ_MASK_CTS
VSF_USART_IRQ_MASK_CTS
VSF_USART_IRQ_MASK_RX_CPL
VSF_USART_IRQ_MASK_TX_CPL
VSF_USART_IRQ_MASK_TX
VSF_USART_IRQ_MASK_RX_IDLE
VSF_USART_IRQ_MASK_RX_IDLE
VSF_USART_IRQ_MASK_RX
VSF_USART_IRQ_MASK_TX_IDLE
VSF_USART_IRQ_MASK_TX_IDLE
VSF_USART_IRQ_MASK_PARITY_ERR
VSF_USART_IRQ_MASK_RX_TIMEOUT
VSF_USART_IRQ_MASK_RX_TIMEOUT
VSF_USART_IRQ_MASK_RX_OVERFLOW_ERR
VSF_USART_IRQ_MASK_NOISE_ERR
VSF_USART_IRQ_MASK_NOISE_ERR
VSF_USART_IRQ_MASK_FRAME_ERR
VSF_USART_IRQ_MASK_BREAK_ERR
VSF_USART_IRQ_MASK_BREAK_ERR
__VSF_HW_USART_IRQ_MASK
__VSF_HW_USART_CTRL1_IRQ_MASK
__VSF_HW_USART_CTRL2_IRQ_MASK
__VSF_HW_USART_CTRL3_IRQ_MASK
__VSF_HW_USART_STS_IRQ_MASK

vsf_usart_ctrl_t

enum vsf_usart_ctrl_t

Enumerator
VSF_USART_CTRL_SEND_BREAK
VSF_USART_CTRL_SEND_BREAK
__VSF_HW_USART_SUPPORT_CMD_MASK
VSF_USART_CTRL_SET_BREAK
VSF_USART_CTRL_CLEAR_BREAK