enum | vsf_usart_mode_t {
VSF_USART_0_5_STOPBIT = (1 << 12) >> 12
,
VSF_USART_1_STOPBIT = (0 << 12) >> 12
,
VSF_USART_1_5_STOPBIT = (3 << 12) >> 12
,
VSF_USART_2_STOPBIT = (2 << 12) >> 12
,
VSF_USART_TX_ENABLE = (1 << 3)
,
VSF_USART_TX_DISABLE = (0 << 3)
,
VSF_USART_RX_ENABLE = (1 << 2)
,
VSF_USART_RX_DISABLE = (0 << 2)
,
VSF_USART_NO_HWCONTROL = (0)
,
VSF_USART_RTS_HWCONTROL = (1 << 8) >> 4
,
VSF_USART_CTS_HWCONTROL = (1 << 9) >> 4
,
VSF_USART_RTS_CTS_HWCONTROL
,
VSF_USART_HALF_DUPLEX_ENABLE = (1 << 3) << 3
,
VSF_USART_HALF_DUPLEX_DISABLE = 0
,
VSF_USART_NO_PARITY = (0 << 10)
,
VSF_USART_ODD_PARITY = (1 << 10) | (1 << 9)
,
VSF_USART_EVEN_PARITY = (1 << 10)
,
VSF_USART_SYNC = (1 << 11)
,
VSF_USART_9_BIT_LENGTH = (1 << 12)
,
VSF_USART_8_BIT_LENGTH = (0)
,
VSF_USART_7_BIT_LENGTH = (1 << 28)
,
VSF_USART_SWAP = (1 << 15)
,
VSF_USART_TX_INV = (1 << 17)
,
VSF_USART_RX_INV = (1 << 16)
,
VSF_USART_OVERSAMPLE_8 = (1 << 18)
,
VSF_USART_OVERSAMPLE_16 = (0 << 18)
,
VSF_USART_OVERSAMPLE_MASK = (1 << 18)
,
__VSF_HW_USART_CR1_MASK
,
__VSF_HW_USART_CR2_MASK
,
__VSF_HW_USART_CR3_MASK
,
VSF_USART_6_BIT_LENGTH = (1 << 20)
,
VSF_USART_5_BIT_LENGTH = (2 << 20)
,
VSF_USART_10_BIT_LENGTH = (3 << 20)
,
VSF_USART_FORCE_0_PARITY = (0 << 8)
,
VSF_USART_FORCE_1_PARITY = (1 << 8)
,
VSF_USART_TX_FIFO_THRESHOLD_EMPTY = (0x0ul << 20)
,
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = (0x1ul << 20)
,
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = (0x2ul << 20)
,
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = (0x0ul << 22)
,
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = (0x1ul << 22)
,
VSF_USART_RX_FIFO_THRESHOLD_FULL = (0x2ul << 22)
,
VSF_USART_SYNC_CLOCK_ENABLE = (0x1ul << 23)
,
VSF_USART_SYNC_CLOCK_DISABLE = (0x0ul << 23)
,
VSF_USART_SYNC_CLOCK_POLARITY_LOW = (0x0ul << 24)
,
VSF_USART_SYNC_CLOCK_POLARITY_HIGH = (0x1ul << 24)
,
VSF_USART_SYNC_CLOCK_PHASE_1_EDGE = (0x0ul << 25)
,
VSF_USART_SYNC_CLOCK_PHASE_2_EDGE = (0x1ul << 25)
,
__VSF_HW_USART_NOT_SUPPORT_MASK
} |