Go to the source code of this file.
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enum | vsf_usart_mode_t {
VSF_USART_NO_PARITY = (0x0ul << 0)
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VSF_USART_EVEN_PARITY = (0x1ul << 0)
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VSF_USART_ODD_PARITY = (0x2ul << 0)
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VSF_USART_FORCE_0_PARITY = (0x3ul << 0)
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VSF_USART_FORCE_1_PARITY = (0x4ul << 0)
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VSF_USART_1_STOPBIT = (0x0ul << 3)
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VSF_USART_1_5_STOPBIT = (0x1ul << 3)
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VSF_USART_0_5_STOPBIT = (0x2ul << 3)
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VSF_USART_2_STOPBIT = (0x3ul << 3)
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VSF_USART_5_BIT_LENGTH = (0x0ul << 5)
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VSF_USART_6_BIT_LENGTH = (0x1ul << 5)
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VSF_USART_7_BIT_LENGTH = (0x2ul << 5)
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VSF_USART_8_BIT_LENGTH = (0x3ul << 5)
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VSF_USART_9_BIT_LENGTH = (0x4ul << 5)
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VSF_USART_10_BIT_LENGTH = (0x5ul << 5)
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VSF_USART_NO_HWCONTROL = (0x0ul << 8)
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VSF_USART_RTS_HWCONTROL = (0x1ul << 8)
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VSF_USART_CTS_HWCONTROL = (0x2ul << 8)
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VSF_USART_RTS_CTS_HWCONTROL = (0x3ul << 8)
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VSF_USART_TX_ENABLE = (0x0ul << 9)
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VSF_USART_TX_DISABLE = (0x1ul << 9)
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VSF_USART_RX_ENABLE = (0x0ul << 10)
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VSF_USART_RX_DISABLE = (0x1ul << 10)
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VSF_USART_SYNC_CLOCK_ENABLE = (0x0ul << 11)
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VSF_USART_SYNC_CLOCK_DISABLE = (0x1ul << 11)
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VSF_USART_HALF_DUPLEX_DISABLE = (0x0ul << 12)
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VSF_USART_HALF_DUPLEX_ENABLE = (0x1ul << 12)
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VSF_USART_TX_FIFO_THRESHOLD_EMPTY = (0x0ul << 13)
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VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY = (0x1ul << 13)
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VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL = (0x2ul << 15)
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VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY = (0x0ul << 15)
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VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL = (0x1ul << 15)
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VSF_USART_RX_FIFO_THRESHOLD_FULL = (0x2ul << 15)
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VSF_USART_SYNC_CLOCK_POLARITY_LOW = (0x0ul << 16)
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VSF_USART_SYNC_CLOCK_POLARITY_HIGH = (0x1ul << 16)
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VSF_USART_SYNC_CLOCK_PHASE_1_EDGE = (0x0ul << 17)
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VSF_USART_SYNC_CLOCK_PHASE_2_EDGE = (0x1ul << 17)
} |
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enum | vsf_usart_irq_mask_t {
VSF_USART_IRQ_MASK_TX_CPL = (0x1ul << 0)
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VSF_USART_IRQ_MASK_RX_CPL = (0x1ul << 1)
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VSF_USART_IRQ_MASK_TX = (0x1ul << 2)
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VSF_USART_IRQ_MASK_RX = (0x1ul << 3)
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VSF_USART_IRQ_MASK_RX_TIMEOUT = (0x1ul << 4)
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VSF_USART_IRQ_MASK_CTS = (0x1ul << 5)
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VSF_USART_IRQ_MASK_FRAME_ERR = (0x1ul << 6)
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VSF_USART_IRQ_MASK_PARITY_ERR = (0x1ul << 7)
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VSF_USART_IRQ_MASK_BREAK_ERR = (0x1ul << 8)
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VSF_USART_IRQ_MASK_OVERFLOW_ERR = (0x1ul << 9)
} |
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enum | vsf_usart_cmd_t {
VSF_USART_CMD_SEND_BREAK = (0x01ul << 0)
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VSF_USART_CMD_SET_BREAK = (0x01ul << 1)
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VSF_USART_CMD_CLEAR_BREAK = (0x01ul << 2)
} |
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◆ __HAL_DRIVER_
#define __HAL_DRIVER_ ${SERIES/USART_IP}_USART_H__ |
◆ VSF_
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_MODE
#define VSF_USART_CFG_REIMPLEMENT_TYPE_MODE ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS
#define VSF_USART_CFG_REIMPLEMENT_TYPE_STATUS ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK
#define VSF_USART_CFG_REIMPLEMENT_TYPE_IRQ_MASK ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_CMD
#define VSF_USART_CFG_REIMPLEMENT_TYPE_CMD ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_CFG
#define VSF_USART_CFG_REIMPLEMENT_TYPE_CFG ENABLED |
◆ VSF_USART_CFG_REIMPLEMENT_TYPE_CAPABILITY
#define VSF_USART_CFG_REIMPLEMENT_TYPE_CAPABILITY ENABLED |
◆ vsf_usart_mode_t
◆ vsf_usart_irq_mask_t
◆ vsf_usart_cmd_t
◆ vsf_usart_status_t
◆ vsf_usart_mode_t
Enumerator |
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VSF_USART_NO_PARITY | |
VSF_USART_EVEN_PARITY | |
VSF_USART_ODD_PARITY | |
VSF_USART_FORCE_0_PARITY | |
VSF_USART_FORCE_1_PARITY | |
VSF_USART_1_STOPBIT | |
VSF_USART_1_5_STOPBIT | |
VSF_USART_0_5_STOPBIT | |
VSF_USART_2_STOPBIT | |
VSF_USART_5_BIT_LENGTH | |
VSF_USART_6_BIT_LENGTH | |
VSF_USART_7_BIT_LENGTH | |
VSF_USART_8_BIT_LENGTH | |
VSF_USART_9_BIT_LENGTH | |
VSF_USART_10_BIT_LENGTH | |
VSF_USART_NO_HWCONTROL | |
VSF_USART_RTS_HWCONTROL | |
VSF_USART_CTS_HWCONTROL | |
VSF_USART_RTS_CTS_HWCONTROL | |
VSF_USART_TX_ENABLE | |
VSF_USART_TX_DISABLE | |
VSF_USART_RX_ENABLE | |
VSF_USART_RX_DISABLE | |
VSF_USART_SYNC_CLOCK_ENABLE | |
VSF_USART_SYNC_CLOCK_DISABLE | |
VSF_USART_HALF_DUPLEX_DISABLE | |
VSF_USART_HALF_DUPLEX_ENABLE | |
VSF_USART_TX_FIFO_THRESHOLD_EMPTY | |
VSF_USART_TX_FIFO_THRESHOLD_HALF_EMPTY | |
VSF_USART_TX_FIFO_THRESHOLD_NOT_FULL | |
VSF_USART_RX_FIFO_THRESHOLD_NOT_EMPTY | |
VSF_USART_RX_FIFO_THRESHOLD_HALF_FULL | |
VSF_USART_RX_FIFO_THRESHOLD_FULL | |
VSF_USART_SYNC_CLOCK_POLARITY_LOW | |
VSF_USART_SYNC_CLOCK_POLARITY_HIGH | |
VSF_USART_SYNC_CLOCK_PHASE_1_EDGE | |
VSF_USART_SYNC_CLOCK_PHASE_2_EDGE | |
◆ vsf_usart_irq_mask_t
Enumerator |
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VSF_USART_IRQ_MASK_TX_CPL | |
VSF_USART_IRQ_MASK_RX_CPL | |
VSF_USART_IRQ_MASK_TX | |
VSF_USART_IRQ_MASK_RX | |
VSF_USART_IRQ_MASK_RX_TIMEOUT | |
VSF_USART_IRQ_MASK_CTS | |
VSF_USART_IRQ_MASK_FRAME_ERR | |
VSF_USART_IRQ_MASK_PARITY_ERR | |
VSF_USART_IRQ_MASK_BREAK_ERR | |
VSF_USART_IRQ_MASK_OVERFLOW_ERR | |
◆ vsf_usart_cmd_t
Enumerator |
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VSF_USART_CMD_SEND_BREAK | |
VSF_USART_CMD_SET_BREAK | |
VSF_USART_CMD_CLEAR_BREAK | |
◆ reg
◆ isr